CN116209277A - Current annealing structure and method of ferroelectric capacitor - Google Patents
Current annealing structure and method of ferroelectric capacitor Download PDFInfo
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- CN116209277A CN116209277A CN202310263860.3A CN202310263860A CN116209277A CN 116209277 A CN116209277 A CN 116209277A CN 202310263860 A CN202310263860 A CN 202310263860A CN 116209277 A CN116209277 A CN 116209277A
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Abstract
The present disclosure provides a current annealing structure of a ferroelectric capacitor, comprising: a top electrode metal layer provided with two top electrodes PAD extending out; a bottom electrode metal layer provided with two extended bottom electrodes PAD; the ferroelectric capacitor is arranged between the top electrode metal layer and the bottom electrode metal layer and is attached to the top electrode metal layer and the bottom electrode metal layer; and applying a voltage pulse to the top electrode PAD to enable the voltage pulse to flow through the top electrode metal layer to generate Joule heat, and annealing the ferroelectric capacitor by using the Joule heat. Meanwhile, the present disclosure also provides a method for performing current annealing on a ferroelectric capacitor by using the above current annealing structure, which can alleviate the technical problems in the prior art that the annealing temperature is high, the annealing time is long, the selective heating of a wafer cannot be realized, and the influence of unnecessary high temperature is easily received.
Description
Technical Field
The present disclosure relates to the field of microelectronic device technology, and more particularly, to a current annealing structure and method for hafnium oxide-based ferroelectric capacitors.
Background
Conventional perovskite ferroelectrics, due to their large thickness and lack of viable thin film technology, result in capacitor-based ferroelectric memoryThe device (FRAM) can only be planar capacitive structure and is limited to a minimum 130nm node, due to which the storage density of commercial FRAM products is currently stagnant at 128Mb/cm 2 This has made the development of ferroelectric memories subject to bottlenecks.
Subsequently, hafnium oxide (HfO 2 ) The advantages of wide band gap, high dielectric constant, nanoscale film thickness, compatibility with CMOS integrated process and the like of the base film material are widely studied until 2011, hfO 2 Research on ferroelectric properties of the base film has found that new hopes are brought to the development of ferroelectric memories. Research has found that the formation of metastable non-centrosymmetric orthogonal phases between monoclinic and tetragonal/cubic phase boundaries is HfO 2 The base film exhibits a root cause of ferroelectricity. The formation of the orthogonal phase is closely related to the preparation process of the ferroelectric capacitor, wherein the annealing process has an important influence on the performance of the ferroelectric capacitor device. In the preparation process of the ferroelectric capacitor, a rapid thermal processing method (Rapid Thermal Process, RTP) is generally adopted to anneal the device at a high temperature of 400-550 ℃ for 1 minute. The method limits partial application scenes of the ferroelectric capacitor due to larger energy and time consumption.
Disclosure of Invention
First, the technical problem to be solved
Based on the above problems, the present disclosure provides a current annealing structure and method for a ferroelectric capacitor, so as to alleviate the technical problems in the prior art that when annealing treatment is performed on a ferroelectric capacitor device, the annealing temperature is high, the annealing time is long, selective heating of a wafer cannot be achieved, and the wafer is easily affected by unnecessary high temperature.
(II) technical scheme
In one aspect of the present disclosure, there is provided a current annealing structure of a ferroelectric capacitor, including: a top electrode metal layer provided with two top electrodes PAD extending out; a bottom electrode metal layer provided with two extended bottom electrodes PAD; the ferroelectric capacitor is arranged between the top electrode metal layer and the bottom electrode metal layer and is attached to the top electrode metal layer and the bottom electrode metal layer; and applying a voltage pulse to the top electrode PAD to enable the voltage pulse to flow through the top electrode metal layer to generate Joule heat, and annealing the ferroelectric capacitor by using the Joule heat.
According to an embodiment of the present disclosure, the ferroelectric capacitor is a hafnium oxide based ferroelectric capacitor.
According to an embodiment of the present disclosure, the ferroelectric capacitor is annealed by applying a voltage pulse to the bottom electrode PAD to flow through the bottom electrode metal layer to generate joule heat.
According to an embodiment of the present disclosure, the pulse amplitude and pulse width of the voltage pulse are adjustable.
According to the embodiment of the disclosure, the magnitude of the generated joule heat is adjusted by adjusting the values of the pulse amplitude and the pulse width.
According to embodiments of the present disclosure, pulse amplitude and pulse width are determined based on joule heating required for ferroelectric capacitor annealing.
According to the embodiment of the disclosure, after the ferroelectric capacitor is integrated with other devices, the ferroelectric capacitor in the integrated devices can be annealed after being separated from the process line pair.
According to the embodiment of the disclosure, when a memory cell is formed by a ferroelectric capacitor and a transistor, and a memory array is formed by a plurality of memory cells, any one or more ferroelectric capacitors in the memory array can be designated to be subjected to current annealing.
In another aspect of the present disclosure, there is provided a current annealing method of a ferroelectric capacitor for current annealing the ferroelectric capacitor using the current annealing structure described in any one of the above, the method comprising:
extending two top electrodes PAD from the top electrode metal layer;
extending two bottom electrodes PAD from the bottom electrode metal layer;
arranging a ferroelectric capacitor between the top electrode metal layer and the bottom electrode metal layer and attaching the ferroelectric capacitor to the top electrode metal layer and the bottom electrode metal layer; and
applying a voltage pulse to the top electrode PAD to enable the voltage pulse to flow through the top electrode metal layer to generate Joule heat, and annealing the ferroelectric capacitor by utilizing the Joule heat.
(III) beneficial effects
As can be seen from the above technical solutions, the current annealing structure and method of the ferroelectric capacitor of the present disclosure has at least one or a part of the following advantages:
(1) Annealing the ferroelectric capacitor device by using a conventional thermal annealing process, wherein the annealing is usually performed for more than 1min at 400-550 ℃; the simple current annealing technology has low energy consumption and time consumption, and has great potential in the application of ferroelectric capacitors in the large-scale industrial production of integrated circuits;
(2) Under conventional thermal annealing processes, selective heating within the wafer is not achieved. The layout is inevitably affected by unnecessary high temperature during the thermal annealing. Compared with a thermal annealing process, the current annealing has good annealing selectivity, and other layouts on the wafer are not affected in the annealing process; the ferroelectric capacitor device and other devices are expected to be integrated by utilizing a current annealing technology, so that more breakthroughs are provided in the aspect of circuits, and the ferroelectric capacitor can be applied in more fields;
(3) The in-situ encryption of the information storage node can be realized by using the current annealing technology of the ferroelectric capacitor; for example, after a plurality of ferroelectric memory cells are formed into an array based on a 1T1C structure ferroelectric memory cell formed by ferroelectric capacitors, nonvolatile data storage can be realized by performing current annealing on the designated cells, and the memory cells which are not annealed cannot store data due to poor ferroelectric performance of the ferroelectric capacitors, so that the effect of data encryption can be achieved for the data stored in the designated cells in the whole array.
Drawings
Fig. 1 is a schematic diagram of a current annealing structure of a ferroelectric capacitor according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of voltage pulse application during a current anneal process according to an embodiment of the present disclosure.
Fig. 3a is a schematic diagram of polarization intensity-voltage (P-V) in the electrical characteristics of ferroelectric capacitors after current annealing according to an embodiment of the present disclosure.
Fig. 3b is a schematic diagram of capacitance-voltage (C-V) in the electrical characteristics of ferroelectric capacitors after current annealing in accordance with an embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a ferroelectric capacitor-based 1T1C and 1T-1FeCap integrated structure according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of a principle architecture of implementing in-situ information encryption by a current annealing technology, where a memory array is formed by 1T-1FeCap memory cells of a current annealing structure based on a ferroelectric capacitor according to an embodiment of the disclosure.
[ in the drawings, the main reference numerals of the embodiments of the present disclosure ]
10-a bottom electrode metal layer; 20-top electrode metal layer; 30-ferroelectric capacitor;
A. b, C, D electrode PAD
Detailed Description
The present disclosure provides a current annealing structure and method of a ferroelectric capacitor, which realizes annealing of the ferroelectric capacitor by using joule heat generated by a current flowing through a metal layer by applying a voltage to both sides of a top electrode of the ferroelectric capacitor for a period of time.
The current annealing technology is to apply voltage to two sides of the top electrode of the ferroelectric capacitor for a period of time, and utilize joule heat generated by current flowing through the metal layer to anneal the ferroelectric capacitor. The annealing method is simple and convenient to operate, has high annealing speed, lower energy loss and time consumption, and has great potential in the application of the ferroelectric capacitor to the large-scale industrial production of integrated circuits.
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.
In an embodiment of the present disclosure, a current annealing structure of a ferroelectric capacitor is provided, as shown in fig. 1, including:
a top electrode metal layer provided with two top electrodes PAD extending out;
a bottom electrode metal layer provided with two extended bottom electrodes PAD; and
the ferroelectric capacitor is arranged between the top electrode metal layer and the bottom electrode metal layer and is attached to the top electrode metal layer and the bottom electrode metal layer;
and applying a voltage pulse to the top electrode PAD to enable the voltage pulse to flow through the top electrode metal layer to generate Joule heat, and annealing the ferroelectric capacitor by using the Joule heat.
According to an embodiment of the present disclosure, the ferroelectric capacitor is a hafnium oxide based ferroelectric capacitor.
And applying a voltage pulse to the bottom electrode PAD to enable the voltage pulse to flow through the bottom electrode metal layer to generate Joule heat, and annealing the ferroelectric capacitor by using the Joule heat.
In the embodiment of the disclosure, as shown in fig. 1, 2 PADs are respectively led out from the top electrode metal layer and the bottom electrode metal layer, and 4 PADs are totally led out from the bottom electrode metal layer, PADs marked with letters a and D are led out from the top electrode metal layer, and ferroelectric capacitors are arranged at the junction of the top electrode metal layer and the bottom electrode metal layer. When annealing is performed, voltage pulses are applied to 2 PADs led out from the top metal electrode in the ferroelectric capacitor device, and the current flowing through the metal layer generates Joule heat, so that annealing of the ferroelectric capacitor is realized by using the generated Joule heat.
According to an embodiment of the present disclosure, the pulse amplitude and pulse width of the voltage pulse are adjustable. The pulse amplitude and the pulse width are determined according to the joule heat required by the ferroelectric capacitor annealing in practical application by adjusting the values of the pulse amplitude and the pulse width to achieve the adjustment of the magnitude of the generated joule heat.
According to the embodiment of the disclosure, voltage pulses shown in fig. 2 are applied to 2 PADs (B and C) led out from the top metal electrode, different joule heat is correspondingly generated under different pulse amplitudes (V) and pulse widths (T), and the pulse amplitudes and pulse widths are determined according to the joule heat required by the ferroelectric capacitor annealing, so that the current annealing of the ferroelectric capacitor is realized.
According to the embodiment of the disclosure, as shown in fig. 3a and 3b, the ferroelectric capacitor after the current annealing treatment has ferroelectric characteristics, wherein a P-V curve is a hysteresis loop, when an external voltage is smaller, a ferroelectric domain is turned over under the action of an external electric field, and a polarization intensity value (P) is increased along with the increase of voltages at two ends of the ferroelectric capacitor; when the applied voltage reaches the maximum powerPressure (V) m ) When the ferroelectric domains are all turned over, the polarization intensity reaches a saturated state; when the external voltage is removed, i.e. v=0v, only a few unstable domains return to their original position, i.e. the polarization is in the remnant polarization state (Pr). With positive and negative remnant polarization states, ferroelectric capacitors can store data "0" and "1". The C-V curve presents a typical "butterfly" curve, and theoretically, the capacitance peaks when the voltage across the ferroelectric capacitor is at the positive and negative coercive voltage magnitude (±vc).
According to the embodiment of the disclosure, after the ferroelectric capacitor is integrated with other devices, the ferroelectric capacitor in the integrated devices can be annealed after being separated from the process line pair.
According to the embodiment of the disclosure, when a memory cell is formed by a ferroelectric capacitor and a transistor, and a memory array is formed by a plurality of memory cells, any one or more ferroelectric capacitors in the memory array can be designated to be subjected to current annealing.
According to the embodiments of the present disclosure, it is essential in the manufacturing process, and the conventional thermal annealing process may affect other layouts on the wafer during the annealing process, which makes integration of hafnium oxide-based ferroelectric capacitors with other devices very difficult. The current annealing technology can lead the annealing process to be separated from the process line operation, and other layouts on the wafer are not affected. For example, the combination of 1T1C and 1T-1FeCap into the structure shown in fig. 4, that is, the integration of a volatile memory cell and a nonvolatile memory cell is realized, and the use of the current annealing technology is expected to apply the ferroelectric capacitor to a wider field.
According to the embodiment of the disclosure, as shown in fig. 5, based on the 1T-1FeCap memory cells to form an n×m memory array (n rows and m columns), the ferroelectric capacitor in the designated cell may be subjected to Current Annealing (CA) to make the ferroelectric capacitor have ferroelectric characteristics, and then the memory array is subjected to data writing, so as to realize the specific data storage of the designated memory cell, thereby realizing the in-situ encryption effect of the data.
In another aspect of the present disclosure, there is also provided a current annealing method of a ferroelectric capacitor for current annealing the ferroelectric capacitor using the above-described current annealing structure, the method including:
operation S1: extending two top electrodes PAD from the top electrode metal layer;
operation S2: extending two bottom electrodes PAD from the bottom electrode metal layer;
operation S3: arranging a ferroelectric capacitor between the top electrode metal layer and the bottom electrode metal layer and attaching the ferroelectric capacitor to the top electrode metal layer and the bottom electrode metal layer; and
operation S4: applying a voltage pulse to the top electrode PAD to enable the voltage pulse to flow through the top electrode metal layer to generate Joule heat, and annealing the ferroelectric capacitor by utilizing the Joule heat.
Thus, embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that, in the drawings or the description, implementations which are not drawn or described are all forms known to those skilled in the art, and are not described in detail. Furthermore, the above definitions of the elements and methods are not limited to the specific structures, shapes or modes mentioned in the embodiments, and may be simply modified or replaced by those of ordinary skill in the art.
From the foregoing description, those skilled in the art will be aware of the current annealing structure and method of ferroelectric capacitors of the present disclosure.
In summary, the present disclosure provides a current annealing structure and method for a ferroelectric capacitor, which can realize the application of the ferroelectric capacitor in more fields.
In addition, unless specifically stated otherwise, herein, "first," "second," etc. are used for distinguishing between multiple elements having the same name and not for indicating a level, a hierarchy, an order of execution, or a sequence of processing. A "first" element may occur together with a "second" element in the same component, or may occur in different components. The presence of an element with a larger ordinal number does not necessarily indicate the presence of another element with a smaller ordinal number.
In this context, the so-called feature A "or" (or) or "and/or" (and/or) feature B, unless specifically indicated, refers to the presence of B alone, or both A and B; the feature A "and" (and) or "AND" (and) or "and" (and) feature B, means that the nail and the B coexist; the terms "comprising," "including," "having," "containing," and "containing" are intended to be inclusive and not limited to.
Further, in this document, terms such as "upper," "lower," "left," "right," "front," "back," or "between" are used merely to describe relative positions between elements and are expressly intended to encompass situations of translation, rotation, or mirroring. In addition, in this document, unless specifically indicated otherwise, "an element is on another element" or similar recitation does not necessarily mean that the element contacts the other element.
Furthermore, unless specifically described or steps must occur in sequence, the order of the above steps is not limited to the list above and may be changed or rearranged according to the desired design. In addition, the above embodiments may be mixed with each other or other embodiments based on design and reliability, i.e. the technical features of the different embodiments may be freely combined to form more embodiments.
While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be understood that the foregoing embodiments are merely illustrative of the invention and are not intended to limit the invention, and that any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (9)
1. A current annealing structure of a ferroelectric capacitor, comprising:
a top electrode metal layer provided with two top electrodes PAD extending out;
a bottom electrode metal layer provided with two extended bottom electrodes PAD;
the ferroelectric capacitor is arranged between the top electrode metal layer and the bottom electrode metal layer and is attached to the top electrode metal layer and the bottom electrode metal layer;
and applying a voltage pulse to the top electrode PAD to enable the voltage pulse to flow through the top electrode metal layer to generate Joule heat, and annealing the ferroelectric capacitor by using the Joule heat.
2. The current annealed structure of a ferroelectric capacitor of claim 1, the ferroelectric capacitor being a hafnium oxide based ferroelectric capacitor.
3. The current annealing structure of ferroelectric capacitor according to claim 1, wherein said ferroelectric capacitor is annealed by joule heat generated by applying a voltage pulse to said bottom electrode PAD to flow through a bottom electrode metal layer.
4. The ferroelectric capacitor current annealing structure according to claim 1, wherein a pulse amplitude and a pulse width of the voltage pulse are adjustable.
5. The current annealing structure of ferroelectric capacitor as claimed in claim 4, wherein the magnitude of the generated joule heat is adjusted by adjusting the values of the pulse amplitude and the pulse width.
6. The structure of claim 5, wherein the pulse amplitude and pulse width are determined based on joule heating required for annealing the ferroelectric capacitor.
7. The ferroelectric capacitor current annealing structure according to claim 1, wherein the ferroelectric capacitor is integrated with other devices, and the ferroelectric capacitor in the integrated devices can be annealed off the process line pair.
8. The ferroelectric capacitor current annealing structure according to claim 7, wherein when a memory cell comprising a ferroelectric capacitor and a transistor and a memory array is formed by a plurality of the memory cells, any one or more ferroelectric capacitors in the memory array can be designated for current annealing.
9. A method of current annealing a ferroelectric capacitor for current annealing a ferroelectric capacitor with the current annealing structure of any one of claims 1-8, the method comprising:
extending two top electrodes PAD from the top electrode metal layer;
extending two bottom electrodes PAD from the bottom electrode metal layer;
arranging a ferroelectric capacitor between the top electrode metal layer and the bottom electrode metal layer and attaching the ferroelectric capacitor to the top electrode metal layer and the bottom electrode metal layer; and
applying a voltage pulse to the top electrode PAD to enable the voltage pulse to flow through the top electrode metal layer to generate Joule heat, and annealing the ferroelectric capacitor by utilizing the Joule heat.
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