CN116206980A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Method for manufacturing semiconductor device and semiconductor device Download PDF

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Publication number
CN116206980A
CN116206980A CN202310478314.1A CN202310478314A CN116206980A CN 116206980 A CN116206980 A CN 116206980A CN 202310478314 A CN202310478314 A CN 202310478314A CN 116206980 A CN116206980 A CN 116206980A
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epitaxial layer
substrate
layer
region
epitaxial
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张劲
吕正良
宋聪强
许俊康
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Nexchip Semiconductor Corp
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Nexchip Semiconductor Corp
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Priority to CN202310478314.1A priority Critical patent/CN116206980A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application provides a manufacturing method of a semiconductor device and the semiconductor device, wherein the method comprises the following steps: firstly, providing a substrate comprising a substrate, an epitaxial layer, a first grid structure and a second grid structure, wherein the epitaxial layer comprises a first region and a second region which are arranged left and right and have different doping types; then, carrying out first ion implantation on the epitaxial layers at two sides of the second grid structure to form a first source region and a first drain region; then, forming a stress layer on the second gate structure and a part of the surface, away from the substrate, of the second region of the epitaxial layer; then, carrying out first ion implantation on the epitaxial layers at two sides of the first grid structure to form a second source region and a second drain region, so as to obtain a preparation structure; and finally, annealing the prepared structure to obtain a target structure, and removing the stress layer. The manufacturing process of the semiconductor device is simpler, the cost is lower, and the performance of the semiconductor device is better.

Description

Method for manufacturing semiconductor device and semiconductor device
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
At present, since the PMOS (Positive Channel Metal Oxide Semiconductor, P-type metal oxide semiconductor field effect transistor) and the NMOS (Negative Channel Metal Oxide Semiconductor, N-type metal oxide semiconductor field effect transistor) in the chip need to be implanted with ions of different doping types, during the formation process, the PMOS portion needs to be shielded first, the NMOS ion implantation process is performed, then the NMOS portion is shielded, and the PMOS ion implantation process is performed, and during the NMOS shielding process, ion impurities are easily caused to the PMOS portion, thereby affecting the performance of the device.
In addition, below the current 90nm logic technology node, a stress engineering for improving the speed of the NMOS device is raised, namely a stress memorization technology (Stress Memorization Technique, abbreviated as SMT), and the SMT is a process performed after the NMOS and PMOS ion implantation, and SiN on the PMOS surface needs to be removed by a yellow light process, so that the adverse effect of the stress memorization technology on the PMOS is avoided, and the process is complicated and the cost is high.
Disclosure of Invention
The main purpose of the present application is to provide a method for manufacturing a semiconductor device and a semiconductor device, so as to solve the problems of higher cost and poor device performance caused by complicated doping process in the prior art.
According to an aspect of an embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: providing a substrate, wherein the substrate comprises a substrate, an epitaxial layer, a first grid structure and a second grid structure, the substrate and the epitaxial layer are sequentially laminated, the epitaxial layer comprises a first area and a second area, the doping types of the first area and the second area are different, the first grid structure and the second grid structure are arranged on the surface of a part of the epitaxial layer, which is far away from the substrate, at intervals, the projection of the first grid structure in the epitaxial layer is positioned in the first area, and the projection of the second grid structure in the epitaxial layer is positioned in the second area; performing first ion implantation on the epitaxial layers at two sides of the second grid structure to form a first source region and a first drain region; forming a stress layer on the second gate structure and a part of the surface of the epitaxial layer, which is far away from the substrate, and enabling the projection of the stress layer in the epitaxial layer to cover the second area; performing the first ion implantation on the epitaxial layers at two sides of the first grid structure to form a second source region and a second drain region, so as to obtain a preparation structure; and annealing the preparation structure to obtain a target structure, and removing the stress layer.
Optionally, performing a first ion implantation on the epitaxial layer at two sides of the second gate structure to form a first source region and a first drain region, including: forming a first mask structure on the first gate structure and a part of the surface of the epitaxial layer, which is far away from the substrate, wherein the projection of the first mask structure in the epitaxial layer covers the first area; taking the first mask structure as a mask, and performing first ion implantation on the epitaxial layers at two sides of the second gate structure to obtain the first source region and the first drain region; and removing the first mask structure.
Optionally, forming a stress layer on the second gate structure and a portion of the surface of the epitaxial layer away from the substrate, including: forming a preliminary stress layer on the first gate structure, the second gate structure, and a surface of the epitaxial layer remote from the substrate; forming a second mask structure on a part of the surface of the pre-stress layer, which is far away from the substrate, wherein the projection of the second mask structure in the epitaxial layer covers the second area; and taking the second mask structure as a mask, removing part of the preliminary stress layer, and forming the stress layer by the rest of the preliminary stress layer.
Optionally, the first ion implantation is performed on the epitaxial layer at two sides of the first gate structure to form a second source region and a second drain region, including: taking the second mask structure as a mask, and performing first ion implantation on the epitaxial layers at two sides of the first gate structure to obtain the second source region and the second drain region; and removing the second mask structure.
Optionally, providing a substrate, comprising: providing the laminated substrate and preparing an epitaxial layer; removing part of the preparation epitaxial layer to form a plurality of first grooves which are arranged at intervals, wherein each first groove exposes part of the substrate, and the rest of the preparation epitaxial layer forms the epitaxial layer; forming an isolation material in the first groove to obtain a plurality of isolation layers which are arranged at intervals, and forming an oxide layer on the surface of the epitaxial layer, which is far away from the substrate; performing second ion implantation of different doping types on the epitaxial layers among the isolation layers to obtain the first region and the second region; the first gate structure and the second gate structure are formed on a portion of a surface of the oxide layer remote from the substrate.
Optionally, annealing the preliminary structure to obtain a target structure, and removing the stress layer, including: and carrying out annealing treatment on the preparation structure by using a stress memorization technology to obtain the target structure, and removing the stress layer.
Optionally, the doping type of the first region in the epitaxial layer is N-type, and the doping type of the second region in the epitaxial layer is P-type.
Optionally, the material of the stress layer comprises SiN.
Optionally, the stress layer has a thickness in the range of 100 angstroms to 1000 angstroms.
According to another aspect of the present application, there is further provided a semiconductor device fabricated by any one of the fabrication methods of the semiconductor device.
According to the technical scheme, in the manufacturing method of the semiconductor device, firstly, a substrate comprising a substrate, an epitaxial layer, a first grid structure and a second grid structure is provided, wherein the substrate and the epitaxial layer are laminated, the epitaxial layer comprises a first region and a second region which are arranged left and right and have different doping types, in addition, the first grid structure and the second grid structure are arranged on the surface of a part of the epitaxial layer, which is far away from the substrate, at intervals, the projection of the first grid structure in the epitaxial layer is positioned in the first region, and the projection of the second grid structure in the epitaxial layer is positioned in the second region; then, performing first ion implantation on the epitaxial layers at two sides of the second grid structure to form a first source region and a first drain region; thereafter, forming a stress layer on the second gate structure and a portion of the surface of the second region of the epitaxial layer remote from the substrate; then, carrying out first ion implantation on the epitaxial layers at two sides of the first grid structure to form a second source region and a second drain region, so as to obtain a preparation structure; and finally, carrying out annealing treatment on the preparation structure to obtain a target structure, and removing the stress layer. Compared with the problems of higher cost and poorer device performance caused by complicated doping process in the prior art, the manufacturing method of the semiconductor device of the application comprises the steps of firstly providing the substrate, wherein the epitaxial layers in the substrate comprise the first region and the second region with different doping types, then performing the first ion implantation on the epitaxial layers at two sides of the second grid structure to obtain the first source region and the first drain region, forming the stress layer on the second grid structure and part of the epitaxial layers far away from the substrate, finally performing the first ion implantation on the epitaxial layers at two sides of the first grid structure to obtain the second source region and the second drain region, on the one hand, the stress layer can play a role in shielding the epitaxial layers at two sides of the second grid structure in the process of forming the second source region and the second drain region, thereby avoiding the first source region and the first source region, generating ions, ensuring the stress layer to be better than the first source region and the second source region, on the other hand, forming the semiconductor device in advance, and forming the stress layer at the second source region and the second drain region, on the other hand, the cost is reduced compared with the prior art, and ensures that the performance of the semiconductor device is better.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 shows a flow diagram of a method of fabricating a semiconductor device according to an embodiment of the present application;
fig. 2 shows a schematic structural diagram of a substrate and an epitaxial layer according to an embodiment of the present application;
fig. 3 shows a schematic structural diagram obtained after forming a first trench according to an embodiment of the present application;
FIG. 4 illustrates a schematic structure obtained after forming an isolation layer and an oxide layer according to an embodiment of the present application;
FIG. 5 shows a schematic structural view of a substrate according to an embodiment of the present application;
FIG. 6 illustrates a schematic structure obtained after forming a first mask structure according to an embodiment of the present application;
fig. 7 shows a schematic structural diagram obtained after forming a first source region and a first drain region according to an embodiment of the present application;
FIG. 8 shows a schematic structure diagram obtained after removing the first mask structure according to an embodiment of the present application;
FIG. 9 shows a schematic structural diagram obtained after formation of a pre-stress layer according to an embodiment of the present application;
FIG. 10 illustrates a schematic structure obtained after forming a second mask structure according to an embodiment of the present application;
FIG. 11 shows a schematic structural diagram obtained after formation of a stress layer according to an embodiment of the present application;
fig. 12 shows a schematic structural diagram obtained after forming a second source region and a second drain region according to an embodiment of the present application;
FIG. 13 shows a schematic structure diagram obtained after removing the second mask structure according to an embodiment of the present application;
fig. 14 shows a schematic structural diagram obtained after removal of the stress layer according to an embodiment of the present application.
Wherein the above figures include the following reference numerals:
10. a substrate; 20. a first source region; 30. a first drain region; 40. a stress layer; 50. a second source region; 60. a second drain region; 70. a first mask structure; 80. preparing a stress layer; 90. a second mask structure; 100. a first trench; 101. a substrate; 102. an epitaxial layer; 103. a first gate structure; 104. a second gate structure; 105. preparing an epitaxial layer; 106. an isolation layer; 107. and (5) an oxide layer.
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the doping process in the prior art is complicated, which results in high cost and poor device performance, and in order to solve the above problem, in an exemplary embodiment of the present application, a method for manufacturing a semiconductor device and a semiconductor device are provided.
According to an embodiment of the application, a method for manufacturing a semiconductor device is provided.
Fig. 1 is a flowchart of a method of fabricating a semiconductor device according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
step S101, as shown in fig. 5, providing a base 10, where the base 10 includes a substrate 101, an epitaxial layer 102, a first gate structure 103, and a second gate structure 104, where the substrate 101 and the epitaxial layer 102 are sequentially stacked, the epitaxial layer 102 includes a first region (not shown) and a second region (not shown), the first region and the second region are different in doping type, the first gate structure 103 and the second gate structure 104 are disposed on a portion of a surface of the epitaxial layer 102 away from the substrate 101 at intervals, and a projection of the first gate structure 103 in the epitaxial layer 102 is located in the first region, and a projection of the second gate structure 104 in the epitaxial layer 102 is located in the second region;
step S102, as shown in fig. 7, performing a first ion implantation on the epitaxial layer 102 at both sides of the second gate structure 104 to form a first source region 20 and a first drain region 30;
step S103, as shown in fig. 11, of forming a stress layer 40 on the second gate structure 104 and a portion of the surface of the epitaxial layer 102 away from the substrate 101, wherein the projection of the stress layer 40 in the epitaxial layer 102 covers the second region;
step S104, as shown in fig. 12, performing the first ion implantation on the epitaxial layer 102 at both sides of the first gate structure 103 to form a second source region 50 and a second drain region 60, thereby obtaining a preliminary structure;
step S105, annealing the preliminary structure to obtain a target structure, and removing the stress layer to obtain a structure as shown in fig. 14.
In the method for manufacturing a semiconductor device, a substrate including a substrate, an epitaxial layer, a first gate structure and a second gate structure is provided, wherein the substrate and the epitaxial layer are stacked, the epitaxial layer includes a first region and a second region which are arranged left and right and have different doping types, the first gate structure and the second gate structure are arranged on a part of a surface of the epitaxial layer, which is far away from the substrate, and a projection of the first gate structure in the epitaxial layer is positioned in the first region, and a projection of the second gate structure in the epitaxial layer is positioned in the second region; then, carrying out first ion implantation on the epitaxial layers at two sides of the second grid structure to form a first source region and a first drain region; then, forming a stress layer on the second gate structure and a part of the surface of the second region of the epitaxial layer, which is far away from the substrate; then, carrying out the first ion implantation on the epitaxial layers at two sides of the first grid electrode structure to form a second source region and a second drain region, so as to obtain a preparation structure; and finally, annealing the prepared structure to obtain a target structure, and removing the stress layer. Compared with the problems of high cost and poor device performance caused by complicated doping process in the prior art, the manufacturing method of the semiconductor device of the application comprises the steps of firstly providing the substrate, wherein the epitaxial layers in the substrate comprise the first region and the second region with different doping types, then performing the first ion implantation on the epitaxial layers on two sides of the second grid structure to obtain the first source region and the first drain region, forming the stress layer on the second grid structure and part surfaces of the epitaxial layers far away from the substrate, finally performing the first ion implantation on the epitaxial layers on two sides of the first grid structure to obtain the second source region and the second drain region, on one hand, the stress layer can play a role in shielding the epitaxial layers on two sides of the second grid structure in the process of forming the second source region and the second drain region, thereby avoiding the first source region and the first drain region, forming the stress layer on the second grid structure, and ensuring the second source region and the second drain region, and the stress layer can be formed in advance, on the other hand, compared with the prior art, the prior art is easier to manufacture the semiconductor device of the prior art, and the prior art has the advantages of reducing the cost of forming the second source region and the second drain region, and ensures that the performance of the semiconductor device is better.
In the prior art, since the doping types of the first region and the second region are different, in the process of forming the source and drain for the first region and the second region respectively, the surface of the epitaxial layer corresponding to the first region needs to be shielded, so that the ion implantation of the source and drain for the second region is performed, the surface of the epitaxial layer corresponding to the second region is shielded by the shielding, so that the ion implantation of the source and drain for the first region is performed, and the thickness requirement for shielding the mask structure used is higher, namely, a thicker mask structure is required to ensure the performance of the device, and in the process of forming the semiconductor device, the first source region and the second drain region corresponding to the second region are formed first, the stress layer is formed by the second source region and the second drain region, and the stress layer is positioned on the partial surface of the second gate structure and the epitaxial layer, and then the second source region and the second drain region are formed, so that the first source region and the second drain region can be formed, and the first source region can be prevented from being implanted by the same, and the thickness requirement for the semiconductor device can be further met.
According to a specific embodiment of the present application, a first ion implantation is performed on the epitaxial layer at two sides of the second gate structure to form a first source region and a first drain region, including: as shown in fig. 6, a first mask structure 70 is formed on the first gate structure 103 and a portion of the surface of the epitaxial layer 102 away from the substrate 101, wherein a projection of the first mask structure 70 into the epitaxial layer 102 covers the first region; as shown in fig. 7, the first source region 20 and the first drain region 30 are obtained by performing the first ion implantation on the epitaxial layer 102 on both sides of the second gate structure 104 using the first mask structure 70 as a mask; as shown in fig. 7 to 8, the first mask structure 70 is removed. By forming the first mask structure on the first gate structure and a portion of the surface of the epitaxial layer away from the substrate, ion impurities are not formed in the epitaxial layer on both sides of the first gate structure during the first ion implantation of the epitaxial layer on both sides of the second gate structure, which is beneficial to improving the performance of the semiconductor device.
Specifically, the first gate structure and the second gate structure respectively include a gate oxide layer, a gate electrode, and a sidewall structure, where the gate oxide layer and the gate electrode are stacked, the sidewall structure covers side surfaces of the gate oxide layer and the gate electrode, and the gate oxide layer is used to realize transistor current control.
In order to further ensure that the performance of the semiconductor device is better, according to another embodiment of the present application, forming a stress layer on the second gate structure and a portion of the surface of the epitaxial layer away from the substrate includes: as shown in fig. 9, a preliminary stress layer 80 is formed on the first gate structure 103, the second gate structure 104, and the surface of the epitaxial layer 102 away from the substrate 101; as shown in fig. 10, a second mask structure 90 is formed on a portion of the surface of the pre-stress layer 80 away from the substrate, and a projection of the second mask structure 90 into the epitaxial layer 102 covers the second region; as shown in fig. 10 to 11, a part of the preliminary stress layer 80 is removed using the second mask structure 90 as a mask, and the remaining preliminary stress layer 80 forms the stress layer 40. The preparation stress layer covering the exposed surfaces of the first grid electrode structure, the second grid electrode structure and the epitaxial layer is formed, the second mask structure covers the second area of the epitaxial layer, and part of the preparation stress layer is removed by taking the second mask structure as a mask, so that the rest of the stress layer only covers the second grid electrode structure corresponding to the second area, and the subsequent annealing treatment is carried out on the stress layer corresponding to the second area only, so that the stress memory technology is realized, the performance of a device corresponding to the second area is better, the performance of the device corresponding to the first area is not influenced, and the performance of the semiconductor device is better.
Specifically, the stress memorization technique is mainly used to increase the speed of the NMOS device, but the PMOS device will not be affected advantageously or even have poor performance, so that in the process of applying the stress memorization technique, it is required to ensure that the PMOS (i.e. the device corresponding to the first region) does not have the stress layer.
In order to further ensure that the manufacturing process of the semiconductor device is simpler and the cost is lower, according to another embodiment of the present application, the first ion implantation is performed on the epitaxial layer at two sides of the first gate structure, to form a second source region and a second drain region, including: as shown in fig. 12, the second source region 50 and the second drain region 60 are obtained by performing the first ion implantation on the epitaxial layer 102 on both sides of the first gate structure 103 using the second mask structure 90 as a mask; as shown in fig. 12 to 13, the second mask structure 90 is removed. The second mask structure is used as a mask, and the second source region and the second drain region are formed on the epitaxial layers on two sides of the first gate structure, so that on one hand, the performance of the transistor can be realized by the device corresponding to the first gate structure, and on the other hand, the mask structure used in the process of forming the stress layer is also the second mask structure, namely, the second mask structure is shared in the process of forming the stress layer, the second source region and the second drain region, so that the situation that the stress layer, the second source region and the second drain region are formed after the formation of the second source region and the second drain region in the prior art is required, the complex process and the high cost of the process in the prior art are ensured, and the process of forming the semiconductor device in advance uses the second mask structure, so that the simple process and the low cost of the process of the semiconductor device are further ensured.
According to a specific embodiment of the present application, there is provided a substrate comprising: as shown in fig. 2, the above-mentioned substrate 101 and the preliminary epitaxial layer 105 are provided as a stack; as shown in fig. 2 to 3, a portion of the preliminary epitaxial layer 105 is removed to form a plurality of first trenches 100 disposed at intervals, each of the first trenches 100 exposes a portion of the substrate 101, and the remaining preliminary epitaxial layer 105 forms the epitaxial layer 102; as shown in fig. 4, an isolation material is formed in the first trench, a plurality of isolation layers 106 are provided at intervals, and an oxide layer 107 is formed on a surface of the epitaxial layer 102 remote from the substrate 101; performing second ion implantation of different doping types on the epitaxial layers among the isolation layers to obtain the first region and the second region; as shown in fig. 5, the first gate structure 103 and the second gate structure 104 are formed on a portion of the surface of the oxide layer 107 remote from the substrate 101. Through forming the isolation layer, the two devices corresponding to the first grid structure and the second grid structure can be isolated through the isolation layer, oxidation of the epitaxial layer can be avoided through the oxidation layer, ion implantation of different doping types is conducted on the epitaxial layer, doping types of the first region and the second region are different, the first grid structure and the second grid structure are formed, and further different types of transistors can be formed in the first region and the second region, and further good performance of the semiconductor device is guaranteed.
Wherein the first gate structure and the second gate structure are both positioned on the surface of the oxide layer, which is far away from the substrate.
In order to further ensure that the performance of the semiconductor device is better, according to another embodiment of the present application, annealing the preliminary structure to obtain a target structure, and removing the stress layer includes: and carrying out the annealing treatment on the preparation structure by using a stress memorization technology to obtain the target structure, and removing the stress layer. And annealing the preparation structure by using a stress memorization technology, so that the electron mobility of the device corresponding to the second gate structure can be accelerated by the stress action, thereby improving the driving current of the device corresponding to the second gate structure and further ensuring the better performance of the semiconductor device.
Specifically, after the annealing treatment is performed on the preliminary structure, as shown in fig. 13 to 14, the stress layer 40 is removed.
According to another embodiment of the present application, the doping type of the first region in the epitaxial layer is N-type, and the doping type of the second region in the epitaxial layer is P-type.
Specifically, the doping type of the first region is N type, the doping type of the second region is P type, the device finally formed in the first region is PMOS device, and the NMOS device of the device finally formed in the second region has positive performance influence only on the NMOS, and the stress memorization technology is implemented by annealing the stress layer, so that the stress layer is only on the surface of the gate structure and the epitaxial layer corresponding to the NMOS.
According to a specific embodiment of the present application, the material of the stress layer includes SiN.
The stress layer corresponding to SiN is used as a shielding layer and a tensile stress film of the first ion implantation.
According to another embodiment of the present application, the stress layer has a thickness in the range of 100 angstroms to 1000 angstroms.
In addition, in the manufacturing process of the semiconductor device of the present application, since the stress layer corresponding to SiN has a better effect of shielding the ion implantation, the thickness of the second mask structure formed before the second source region and the second drain region are formed by the ion implantation is required to be smaller, that is, the second source region and the second drain region may be formed by using the thinner second mask structure as a mask, and of course, the second mask structure may be a thinner BARC (Bottom Anti-Reflective Coatings) or PR (Photoresist), or only BARC or PR may be deposited.
According to an embodiment of the present application, there is further provided a semiconductor device manufactured by any one of the above manufacturing methods of the semiconductor device.
The semiconductor device is manufactured by adopting any one of the manufacturing methods of the semiconductor device. Compared with the problems of higher cost and poorer device performance caused by the complicated doping process in the prior art, the semiconductor device of the application comprises the substrate, the first region and the second region which are different in doping type are firstly provided in the epitaxial layer in the substrate, then the first ion implantation is carried out on the epitaxial layers at two sides of the second grid structure to obtain the first source region and the first drain region, the stress layer is formed on the surfaces of the second grid structure and the part of the epitaxial layer which is far away from the substrate, finally the first ion implantation is carried out on the epitaxial layers at two sides of the first grid structure to obtain the second source region and the second drain region, on one hand, the stress layer can play a role in shielding the epitaxial layers at two sides of the second grid structure in the process of forming the second source region and the second drain region, the stress layer is prevented from being formed in the first source region and the first source region, the first drain region is ensured to be generated, the semiconductor device is manufactured in advance, the prior art is reduced in the process of forming the second source region and the second drain region is easier to manufacture the prior art, and the prior art is reduced in the process of forming the second drain region is easier to manufacture the semiconductor device, and ensures that the performance of the semiconductor device is better.
In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) In the method for manufacturing the semiconductor device, first, a substrate including a substrate, an epitaxial layer, a first gate structure and a second gate structure is provided, wherein the substrate and the epitaxial layer are stacked, the epitaxial layer includes a first region and a second region which are arranged left and right and have different doping types, the first gate structure and the second gate structure are arranged on a part of the surface of the epitaxial layer, which is far away from the substrate, at intervals, and a projection of the first gate structure in the epitaxial layer is located in the first region, and a projection of the second gate structure in the epitaxial layer is located in the second region; then, carrying out first ion implantation on the epitaxial layers at two sides of the second grid structure to form a first source region and a first drain region; then, forming a stress layer on the second gate structure and a part of the surface of the second region of the epitaxial layer, which is far away from the substrate; then, carrying out the first ion implantation on the epitaxial layers at two sides of the first grid electrode structure to form a second source region and a second drain region, so as to obtain a preparation structure; and finally, annealing the prepared structure to obtain a target structure, and removing the stress layer. Compared with the problems of high cost and poor device performance caused by complicated doping process in the prior art, the manufacturing method of the semiconductor device of the application comprises the steps of firstly providing the substrate, wherein the epitaxial layers in the substrate comprise the first region and the second region with different doping types, then performing the first ion implantation on the epitaxial layers on two sides of the second grid structure to obtain the first source region and the first drain region, forming the stress layer on the second grid structure and part surfaces of the epitaxial layers far away from the substrate, finally performing the first ion implantation on the epitaxial layers on two sides of the first grid structure to obtain the second source region and the second drain region, on one hand, the stress layer can play a role in shielding the epitaxial layers on two sides of the second grid structure in the process of forming the second source region and the second drain region, thereby avoiding the first source region and the first drain region, forming the stress layer on the second grid structure, and ensuring the second source region and the second drain region, and the stress layer can be formed in advance, on the other hand, compared with the prior art, the prior art is easier to manufacture the semiconductor device of the prior art, and the prior art has the advantages of reducing the cost of forming the second source region and the second drain region, and ensures that the performance of the semiconductor device is better.
2) The semiconductor device is manufactured by adopting any one of the manufacturing methods of the semiconductor device. Compared with the problems of higher cost and poorer device performance caused by the complicated doping process in the prior art, the semiconductor device of the application comprises the substrate, the first region and the second region which are different in doping type are firstly provided in the epitaxial layer in the substrate, then the first ion implantation is carried out on the epitaxial layers at two sides of the second grid structure to obtain the first source region and the first drain region, the stress layer is formed on the surfaces of the second grid structure and the part of the epitaxial layer which is far away from the substrate, finally the first ion implantation is carried out on the epitaxial layers at two sides of the first grid structure to obtain the second source region and the second drain region, on one hand, the stress layer can play a role in shielding the epitaxial layers at two sides of the second grid structure in the process of forming the second source region and the second drain region, the stress layer is prevented from being formed in the first source region and the first source region, the first drain region is ensured to be generated, the semiconductor device is manufactured in advance, the prior art is reduced in the process of forming the second source region and the second drain region is easier to manufacture the prior art, and the prior art is reduced in the process of forming the second drain region is easier to manufacture the semiconductor device, and ensures that the performance of the semiconductor device is better.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method of fabricating a semiconductor device, the method comprising:
providing a substrate, wherein the substrate comprises a substrate, an epitaxial layer, a first grid structure and a second grid structure, the substrate and the epitaxial layer are sequentially laminated, the epitaxial layer comprises a first area and a second area, the doping types of the first area and the second area are different, the first grid structure and the second grid structure are arranged on the surface of a part of the epitaxial layer, which is far away from the substrate, at intervals, the projection of the first grid structure in the epitaxial layer is positioned in the first area, and the projection of the second grid structure in the epitaxial layer is positioned in the second area;
performing first ion implantation on the epitaxial layers at two sides of the second grid structure to form a first source region and a first drain region;
forming a stress layer on the second gate structure and a part of the surface of the epitaxial layer, which is far away from the substrate, and enabling the projection of the stress layer in the epitaxial layer to cover the second area;
performing the first ion implantation on the epitaxial layers at two sides of the first grid structure to form a second source region and a second drain region, so as to obtain a preparation structure;
and annealing the preparation structure to obtain a target structure, and removing the stress layer.
2. The method of claim 1, wherein performing a first ion implantation on the epitaxial layer on both sides of the second gate structure to form a first source region and a first drain region comprises:
forming a first mask structure on the first gate structure and a part of the surface of the epitaxial layer, which is far away from the substrate, wherein the projection of the first mask structure in the epitaxial layer covers the first area;
taking the first mask structure as a mask, and performing first ion implantation on the epitaxial layers at two sides of the second gate structure to obtain the first source region and the first drain region;
and removing the first mask structure.
3. The method of claim 1, wherein forming a stress layer on the second gate structure and a portion of a surface of the epitaxial layer remote from the substrate comprises:
forming a preliminary stress layer on the first gate structure, the second gate structure, and a surface of the epitaxial layer remote from the substrate;
forming a second mask structure on a part of the surface of the pre-stress layer, which is far away from the substrate, wherein the projection of the second mask structure in the epitaxial layer covers the second area;
and taking the second mask structure as a mask, removing part of the preliminary stress layer, and forming the stress layer by the rest of the preliminary stress layer.
4. The method of claim 3, wherein performing the first ion implantation on the epitaxial layer on both sides of the first gate structure to form a second source region and a second drain region comprises:
taking the second mask structure as a mask, and performing first ion implantation on the epitaxial layers at two sides of the first gate structure to obtain the second source region and the second drain region;
and removing the second mask structure.
5. The method of claim 1, wherein providing a substrate comprises:
providing the laminated substrate and preparing an epitaxial layer;
removing part of the preparation epitaxial layer to form a plurality of first grooves which are arranged at intervals, wherein each first groove exposes part of the substrate, and the rest of the preparation epitaxial layer forms the epitaxial layer;
forming an isolation material in the first groove to obtain a plurality of isolation layers which are arranged at intervals, and forming an oxide layer on the surface of the epitaxial layer, which is far away from the substrate;
performing second ion implantation of different doping types on the epitaxial layers among the isolation layers to obtain the first region and the second region;
the first gate structure and the second gate structure are formed on a portion of a surface of the oxide layer remote from the substrate.
6. The method of claim 1, wherein annealing the preliminary structure to obtain a target structure and removing the stress layer comprises:
and carrying out annealing treatment on the preparation structure by using a stress memorization technology to obtain the target structure, and removing the stress layer.
7. The method of any one of claims 1 to 6, wherein the doping type of the first region in the epitaxial layer is N-type and the doping type of the second region in the epitaxial layer is P-type.
8. The method of any one of claims 1 to 6, wherein the material of the stress layer comprises SiN.
9. The method of any one of claims 1 to 6, wherein the stress layer has a thickness in the range of 100 angstroms-1000 angstroms.
10. A semiconductor device manufactured by the manufacturing method of the semiconductor device according to any one of claims 1 to 9.
CN202310478314.1A 2023-04-28 2023-04-28 Method for manufacturing semiconductor device and semiconductor device Pending CN116206980A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101517731A (en) * 2006-07-31 2009-08-26 先进微装置公司 Method for forming a strained transistor by stress memorization based on a stressed implantation mask
CN102201369A (en) * 2010-03-22 2011-09-28 中芯国际集成电路制造(上海)有限公司 Method for manufacturing complementary metal oxide semiconductor (CMOS) device with stress layer
CN107871710A (en) * 2016-09-23 2018-04-03 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method
CN114899149A (en) * 2022-04-21 2022-08-12 晶芯成(北京)科技有限公司 Manufacturing method of semiconductor device and semiconductor structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101517731A (en) * 2006-07-31 2009-08-26 先进微装置公司 Method for forming a strained transistor by stress memorization based on a stressed implantation mask
CN102201369A (en) * 2010-03-22 2011-09-28 中芯国际集成电路制造(上海)有限公司 Method for manufacturing complementary metal oxide semiconductor (CMOS) device with stress layer
CN107871710A (en) * 2016-09-23 2018-04-03 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method
CN114899149A (en) * 2022-04-21 2022-08-12 晶芯成(北京)科技有限公司 Manufacturing method of semiconductor device and semiconductor structure

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Application publication date: 20230602