CN116193044B - Method, device, equipment and medium for synchronously displaying multiple image frames - Google Patents
Method, device, equipment and medium for synchronously displaying multiple image frames Download PDFInfo
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- CN116193044B CN116193044B CN202310473195.0A CN202310473195A CN116193044B CN 116193044 B CN116193044 B CN 116193044B CN 202310473195 A CN202310473195 A CN 202310473195A CN 116193044 B CN116193044 B CN 116193044B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0075—Arrangements for synchronising receiver with transmitter with photonic or optical means
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2624—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects for obtaining an image which is composed of whole input images, e.g. splitscreen
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention relates to the technical field of image transmission and discloses a method, a device, equipment and a medium for synchronously displaying multiple paths of image frames.
Description
Technical Field
The present invention relates to the field of image transmission technologies, and in particular, to a method, an apparatus, a device, and a medium for synchronously displaying multiple image frames.
Background
The image splicing processor is also called as large screen splicing control, large screen splicer, multi-screen splicing processor, image splicing controller, liquid crystal splicer, display wall processor and the like, and is a professional video processing and control device. The main function of the display device is to divide a complete image signal into a plurality of display units, output the divided display unit signals to a plurality of display terminals (such as a liquid crystal splicing unit, a plasma unit, a rear projection unit, a DLP large screen, a PDP large screen, an LED display screen, a projector, a monitor, a liquid crystal television and the like), and complete the splicing of the display terminals to form a complete super-large screen dynamic image display screen.
The current method for synchronously displaying the multi-path image frames of the image splicing processor mainly realizes the synchronous display of the multi-path images by adding a synchronous clock to a display unit.
The method has the main advantages that clocks required by image processing and image output of the multi-path video can be kept consistent, so that synchronous display is realized at the terminal; the defects are mainly that:
1) A clock chip with very high precision is required to ensure the stability of the synchronous clock, so that the product cost is increased;
2) In the long-distance transmission process of the clock signal, attenuation and jitter phenomena can occur, so that the images of the display units are not synchronous, and manual synchronization is needed at the moment, so that automatic synchronization cannot be realized;
3) Although the synchronous mode can realize clock synchronization of all display units, the synchronous mode cannot ensure that all display units can keep synchronous every frame every moment.
Disclosure of Invention
The invention mainly aims to solve the problem that the existing multipath images cannot realize automatic synchronization of each frame of picture.
The first aspect of the present invention provides a method for synchronously displaying multiple image frames, comprising:
acquiring a source clock signal and a source video;
processing the source clock signal based on an integrated clock algorithm to obtain a new clock signal, a local frame signal and a frame synchronization signal;
transmitting the new clock signal and the frame synchronization signal to a preset display terminal;
acquiring a first image frame of a video image and a second image frame of the source video, wherein the first image frame is generated by the display terminal receiving the new clock signal and the frame synchronization signal;
and comparing the first image frame with the second image frame to obtain a difference signal larger than a preset threshold value, transmitting the difference signal to the display terminal, and processing a preset synchronous compensation signal according to the display terminal to generate a new video image with the same frame as the source video.
Further, in a second implementation manner of the first aspect of the present invention, the processing the source clock signal based on the integrated clock algorithm to obtain a new clock signal, a local frame signal and a frame synchronization signal includes:
and processing the source clock signal through a PLL to obtain clock signals with the same frequency and the same phase.
Further, in a third implementation manner of the first aspect of the present invention, the acquiring the first image frame of the video image and the second image frame of the source video, where the first image frame is generated by the display terminal receiving the new clock signal and the frame synchronization signal, includes:
acquiring an image display control time sequence signal, a video frame signal and image pixel data generated by the display terminal receiving the new clock signal and the frame synchronization signal;
and obtaining a video image based on a preset image signal fusion algorithm according to the display control time sequence signal and the image pixel data.
Further, in a fourth implementation manner of the first aspect of the present invention, the acquiring the first image frame of the video image and the second image frame of the source video, where the first image frame is generated by the display terminal receiving the new clock signal and the frame synchronization signal, includes:
and respectively counting the video frame signal and the local frame signal in preset time to obtain a first image frame and a second image frame.
Further, in a fifth implementation manner of the first aspect of the present invention, the comparing the first image frame with the second image frame to obtain a difference signal greater than a preset threshold value, transmitting the difference signal to the display terminal, and processing a preset synchronization compensation signal according to the display terminal, where generating a new video image of the same frame as the source video includes:
judging whether a difference value obtained by comparing the first image frame with the second image frame is larger than a preset threshold value or not;
if yes, regenerating a new frame synchronizing signal, and transmitting the new frame synchronizing signal to the display terminal;
if not, the operation is not performed.
Further, in a sixth implementation manner of the first aspect of the present invention, the threshold is 1 frame.
A second aspect of the present invention provides an apparatus for synchronizing display of multiple image frames, the apparatus comprising:
the acquisition module is used for acquiring a source clock signal and a source video;
the signal processing module is used for processing the source clock signal based on an integrated clock algorithm to obtain a new clock signal, a local frame signal and a frame synchronization signal;
the transmission module is used for transmitting the new clock signal and the frame synchronization signal to a preset display terminal;
an image frame acquisition module, configured to acquire a first image frame of a video image and a second image frame of the source video, where the first image frame is generated by the display terminal receiving the new clock signal and the frame synchronization signal;
and the synchronization module is used for comparing the first image frame with the second image frame to obtain a difference signal larger than a preset threshold value, transmitting the difference signal to the display terminal, processing a preset synchronization compensation signal according to the display terminal, and generating a new video image with the same frame as the source video.
A third aspect of the present invention provides an apparatus for multi-path image frame synchronization display, the apparatus comprising: a memory and at least one processor, the memory having instructions stored therein, the memory and the at least one processor being interconnected by a line;
the at least one processor invokes the instructions in the memory to cause the device to perform the above method of multi-path image frame synchronization display.
A fourth aspect of the present invention provides a computer readable storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the above method of multi-path image frame synchronous display.
The invention has the beneficial effects that: the method comprises the steps of converting a source video and a corresponding source clock signal to obtain a corresponding new clock signal, a local frame signal and a frame synchronization signal, transmitting the new clock signal and the frame synchronization signal to a corresponding display terminal, processing the new clock signal and the frame synchronization signal by the display terminal to generate a video image, respectively counting image frames of the video image and image frames of the source video to obtain a first image frame and a second image frame, comparing the first image frame and the second image frame to judge whether the difference value is larger than a preset threshold value, and if yes, regenerating a new frame synchronization signal to transmit the new frame synchronization signal to the display terminal to generate a new video image, otherwise, synchronizing the video images of the source video and other display terminals, effectively reducing the cost of synchronous display of images in an image splicing processor, simultaneously obtaining a good synchronization effect and preventing tearing feeling caused by asynchronous pictures.
Drawings
FIG. 1 is a schematic diagram of a first embodiment of a method for synchronously displaying multiple image frames according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a method for synchronizing multiple image frames according to a second embodiment of the present invention;
FIG. 3 is a diagram illustrating a third embodiment of a method for synchronizing multiple image frames according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a first embodiment of an apparatus for synchronously displaying multiple image frames according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an embodiment of an apparatus for synchronizing multiple image frames according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a method, a system, a device, equipment and a medium for synchronously displaying multiple paths of image frames.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.
For ease of understanding, referring to fig. 1-3, an embodiment of a method for synchronously displaying multiple image frames in an embodiment of the present invention is described below, where the method for synchronously displaying multiple image frames includes:
101. acquiring a source clock signal and a source video;
the clock signal is the basis of sequential logic to determine when the state in the logic cells is updated, and is a fixed period, operation independent semaphore. The clock signal has a fixed clock frequency, which is the inverse of the clock period. In an electronic, in particular signal, synchronous digital circuit, the clock signal is the high and low states between oscillations of a particular signal of the signal, the utilization of the signal acts in coordination like a metronome, the digital clock signal being essentially a square wave voltage;
in this embodiment, the output device of one path receives the source video, and transmits the source clock signal of the source video through a preset clock chip, where the clock chip can adjust parameters such as frequency, phase, jitter, and the like of the source clock signal.
102. Processing the source clock signal based on an integrated clock algorithm to obtain a new clock signal, a local frame signal and a frame synchronization signal;
further, step 102 may specifically further be performed:
1021. and processing the source clock signal through a PLL to obtain clock signals with the same frequency and the same phase.
The application body executed in step 1021 is an FPGA chip, where the FPGA chip is a programmable logic array, so that the problem of the original device with fewer gates can be effectively solved. The basic structure of the FPGA comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, wiring resources, an embedded special hard core and a bottom layer embedded functional unit. Because the FPGA has the characteristics of rich wiring resources, high repeated programming and integration level and low investment, the FPGA is widely applied in the field of digital circuit design, in the embodiment, after a PLL circuit is connected with an FPGA chip and one path of source video and source clock signals are acquired through the FPGA chip, the PLL circuit controls the frequency and the phase of an oscillation signal in a loop by utilizing the reference signal of the source clock signals, and the phase-locked loop can realize the automatic tracking of the output signal frequency to the input signal frequency, so the phase-locked loop is generally used for a closed-loop tracking circuit. In the process of the phase-locked loop, when the frequency of the output signal is equal to the frequency of the input signal, the output voltage and the input voltage keep a fixed phase difference value, i.e. the phases of the output voltage and the input voltage are locked, so that the output clock signal can keep the same frequency and the same phase as the input source clock signal.
103. Transmitting the new clock signal and the frame synchronization signal to a preset display terminal;
104. acquiring a first image frame of a video image and a second image frame of the source video, wherein the first image frame is generated by the display terminal receiving the new clock signal and the frame synchronization signal;
in steps 103-104, according to the number of corresponding display terminals, the PLL circuit processes the original signal and generates a corresponding number of clock signals with the same frequency and the same phase, and correspondingly, the local frame signal and the frame synchronization signal are respectively matched to the display terminals, so that the corresponding clock signals with the same frequency and the frame synchronization signal with the same phase are received at each display terminal, wherein the local frame signal is a frame number calibration value used as an image frame of the generated video image on the corresponding display terminal, and the frame synchronization signal is used for realizing calibration of the generated video image on the display terminal.
Further, step 104 may specifically further be performed:
1041. acquiring an image display control time sequence signal, a video frame signal and image pixel data generated by the display terminal receiving the new clock signal and the frame synchronization signal;
1042. obtaining a video image based on a preset image signal fusion algorithm according to the display control time sequence signal and the image pixel data;
1043. respectively counting the video frame signal and the local frame signal in preset time to obtain a first image frame and a second image frame;
in steps 1041-1043, the resolution of the video image to be generated later, such as 1080P60 frame, 1080P50 frame, 720P60 frame, etc., is set in advance, where the image display control timing signal includes a line synchronization signal and a data enable signal, which are processed and fused with the video frame signal and the image pixel data to obtain a complete video image, where the image signal fusion algorithm is not described in detail herein, and after the video image is obtained, in order to confirm whether the video image is synchronized with the source video, the video frame signal of the video image and the local frame signal of the source video are respectively counted in the same time.
1044. Judging whether a difference value obtained by comparing the first image frame with the second image frame is larger than a preset threshold value or not;
1045. if yes, regenerating a new frame synchronizing signal, and transmitting the new frame synchronizing signal to the display terminal;
1046. if not, do not operate
In steps 1044-1046, since each frame is actually a still image, 1080P60 frames refer to that 60 still images are refreshed at 1080P resolution, so the threshold is 1 frame and the threshold is a positive integer, if the difference value is 2 frames, although no difference is seen in the video in a short time, the time axis is lengthened to several minutes or even several hours, 3600 still images are refreshed in one minute, 3480 still images are refreshed in 58 frames, and in two side-by-side image-time axes, the corresponding video out-of-sync condition can be clearly seen, if the video out-of-sync condition is obtained by judging and comparing, the source video and the source clock signal need to be processed again to obtain a new frame synchronizing signal, the corresponding display terminal receives the new frame synchronizing signal to correspondingly generate the video frame signal and the image pixel data, if the video in-sync condition is obtained, no operation is performed.
105. And comparing the first image frame with the second image frame to obtain a difference signal larger than a preset threshold value, transmitting the difference signal to the display terminal, and processing a preset synchronous compensation signal according to the display terminal to generate a new video image with the same frame as the source video.
In this embodiment, the source video and the corresponding source clock signal are converted to obtain the corresponding new clock signal, the local frame signal and the frame synchronization signal, the new clock signal and the frame synchronization signal are transmitted to the corresponding display terminal, the display terminal processes the new clock signal and the frame synchronization signal and generates a video image, the first image frame and the second image frame are obtained by respectively counting the image frames of the video image and the image frames of the source video, the difference value of the first image frame and the second image frame is compared and judged to be greater than a preset threshold value, if yes, the new frame synchronization signal is required to be regenerated and transmitted to the display terminal to generate a new video image, if not, the source video and the video images of other display terminals are synchronous, the cost of synchronous display of the images in the image splicing processor is effectively reduced, and meanwhile, a good synchronization effect is obtained and tearing sense caused by asynchronous images is prevented.
The method for synchronously displaying multiple image frames in the embodiment of the present invention is described above, and the device for synchronously displaying multiple image frames in the embodiment of the present invention is described below, referring to fig. 4, an embodiment of the device for synchronously displaying multiple image frames in the embodiment of the present invention includes:
an acquisition module 201, configured to acquire a source clock signal and a source video;
the signal processing module 202 is configured to process the source clock signal based on an integrated clock algorithm to obtain a new clock signal, a local frame signal and a frame synchronization signal;
a transfer module 203, configured to transfer the new clock signal and the frame synchronization signal to a preset display terminal;
an image frame acquisition module 204, configured to acquire a first image frame of a video image and a second image frame of the source video, where the first image frame is generated by the display terminal receiving the new clock signal and the frame synchronization signal;
and the synchronization module 205 is configured to compare the first image frame with the second image frame to obtain a difference signal greater than a preset threshold, transmit the difference signal to the display terminal, and process a preset synchronization compensation signal according to the display terminal, so as to generate a new video image with the same frame as the source video.
The device for synchronously displaying the multiple image frames in the embodiment of the invention comprises:
an acquisition module 201, configured to acquire a source clock signal and a source video;
the signal processing module 202 is configured to process the source clock signal based on an integrated clock algorithm to obtain a new clock signal, a local frame signal and a frame synchronization signal;
a transfer module 203, configured to transfer the new clock signal and the frame synchronization signal to a preset display terminal;
an image frame acquisition module 204, configured to acquire a first image frame of a video image and a second image frame of the source video, where the first image frame is generated by the display terminal receiving the new clock signal and the frame synchronization signal;
and the synchronization module 205 is configured to compare the first image frame with the second image frame to obtain a difference signal greater than a preset threshold, transmit the difference signal to the display terminal, and process a preset synchronization compensation signal according to the display terminal, so as to generate a new video image with the same frame as the source video.
The signal processing module 202 shown may specifically further perform:
and processing the source clock signal through a PLL to obtain clock signals with the same frequency and the same phase.
The image frame acquisition module 204 may specifically further perform:
acquiring an image display control time sequence signal, a video frame signal and image pixel data generated by the display terminal receiving the new clock signal and the frame synchronization signal;
and obtaining a video image based on a preset image signal fusion algorithm according to the display control time sequence signal and the image pixel data.
The image frame acquisition module 204 may specifically further perform:
and respectively counting the video frame signal and the local frame signal in preset time to obtain a first image frame and a second image frame.
The image frame acquisition module 204 may specifically further perform:
judging whether a difference value obtained by comparing the first image frame with the second image frame is larger than a preset threshold value, wherein the threshold value is 1 frame;
if yes, regenerating a new frame synchronizing signal, and transmitting the new frame synchronizing signal to the display terminal;
if not, the operation is not performed.
In this embodiment, the source video and the corresponding source clock signal are converted to obtain the corresponding new clock signal, the local frame signal and the frame synchronization signal, the new clock signal and the frame synchronization signal are transmitted to the corresponding display terminal, the display terminal processes the new clock signal and the frame synchronization signal and generates a video image, the first image frame and the second image frame are obtained by respectively counting the image frames of the video image and the image frames of the source video, the difference value of the first image frame and the second image frame is compared and judged to be greater than a preset threshold value, if yes, the new frame synchronization signal is required to be regenerated and transmitted to the display terminal to generate a new video image, if not, the source video and the video images of other display terminals are synchronous, the cost of synchronous display of the images in the image splicing processor is effectively reduced, and meanwhile, a good synchronization effect is obtained and tearing sense caused by asynchronous images is prevented.
Fig. 4 above describes the apparatus for synchronously displaying multiple image frames in the embodiment of the present invention in detail from the point of view of modularized functional entities, and the following describes the device for synchronously displaying multiple image frames in the embodiment of the present invention in detail from the point of view of hardware processing.
Fig. 5 is a schematic structural diagram of a device for multi-path image frame synchronization display, where the multi-path image frame synchronization display device 300 may have a relatively large difference due to different configurations or performances, and may include one or more processors (CPU) 310 (e.g., one or more processors) and a memory 320, and one or more storage media 330 (e.g., one or more mass storage devices) storing applications 333 or data 332. Wherein memory 320 and storage medium 330 may be transitory or persistent storage. The program stored in the storage medium 330 may include one or more modules (not shown), each of which may include a series of instruction operations in the apparatus 300 for synchronously displaying multiple image frames. Still further, the processor 310 may be configured to communicate with the storage medium 330 to execute a series of instruction operations in the storage medium 330 on the apparatus 300 for multiple image frame simultaneous display.
The apparatus 300 for multiplexed image frame synchronization display may also include one or more power supplies 340, one or more wired or wireless network interfaces 350, one or more input/output interfaces 360, and/or one or more operating systems 331, such as WindowsServe, macOSX, unix, linux, freeBSD, and the like. It will be appreciated by those skilled in the art that the configuration of the apparatus for multiple image frame synchronization display shown in fig. 5 does not constitute a limitation of the apparatus for multiple image frame synchronization display, and may include more or fewer components than shown, or may combine certain components, or may be a different arrangement of components.
The present invention also provides a computer readable storage medium, which may be a non-volatile computer readable storage medium, or may be a volatile computer readable storage medium, where instructions are stored in the computer readable storage medium, where the instructions, when executed on a computer, cause the computer to perform the steps of the method and system for synchronously displaying multiple image frames.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the system or apparatus and unit described above may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, or other various media capable of storing program codes.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A method for synchronizing display of multiple image frames, comprising:
acquiring a source clock signal and a source video;
processing the source clock signal based on an integrated clock algorithm to obtain a new clock signal, a local frame signal and a frame synchronization signal;
transmitting the new clock signal and the frame synchronization signal to a preset display terminal;
acquiring a first image frame of a video image and a second image frame of the source video, wherein the first image frame is generated by the display terminal receiving the new clock signal and the frame synchronization signal;
comparing the first image frame with the second image frame to obtain a difference signal larger than a preset threshold value, transmitting the difference signal to the display terminal, and processing a preset synchronous compensation signal according to the display terminal to generate a new video image of the same frame as the source video;
the step of processing the source clock signal based on the integrated clock algorithm to obtain a new clock signal, a local frame signal and a frame synchronization signal includes:
and processing the source clock signal through a PLL to obtain clock signals with the same frequency and the same phase.
2. The method of claim 1, wherein the acquiring the first image frame of the video image and the second image frame of the source video by the display terminal receiving the new clock signal and the frame synchronization signal comprises:
acquiring an image display control time sequence signal, a video frame signal and image pixel data generated by the display terminal receiving the new clock signal and the frame synchronization signal;
and obtaining a video image based on a preset image signal fusion algorithm according to the display control time sequence signal and the image pixel data.
3. The method of multi-path image frame synchronization display of claim 2, wherein the acquiring the first image frame of the video image and the second image frame of the source video by the display terminal receiving the new clock signal and the frame synchronization signal comprises:
and respectively counting the video frame signal and the local frame signal in preset time to obtain a first image frame and a second image frame.
4. The method for synchronously displaying multiple image frames according to claim 3, wherein said comparing the first image frame with the second image frame to obtain a difference signal greater than a preset threshold value is transmitted to the display terminal, and processing a preset synchronous compensation signal according to the display terminal, and generating a new video image of the same frame as the source video comprises:
judging whether a difference value obtained by comparing the first image frame with the second image frame is larger than a preset threshold value or not;
if yes, regenerating a new frame synchronizing signal, and transmitting the new frame synchronizing signal to the display terminal;
if not, the operation is not performed.
5. The method of claim 4, wherein the threshold is 1 frame.
6. An apparatus for synchronously displaying multiple image frames, comprising:
the acquisition module is used for acquiring a source clock signal and a source video;
the signal processing module is used for processing the source clock signal based on an integrated clock algorithm to obtain a new clock signal, a local frame signal and a frame synchronization signal;
the transmission module is used for transmitting the new clock signal and the frame synchronization signal to a preset display terminal;
an image frame acquisition module, configured to acquire a first image frame of a video image and a second image frame of the source video, where the first image frame is generated by the display terminal receiving the new clock signal and the frame synchronization signal;
and the synchronization module is used for comparing the first image frame with the second image frame to obtain a difference signal larger than a preset threshold value, transmitting the difference signal to the display terminal, processing a preset synchronization compensation signal according to the display terminal, and generating a new video image with the same frame as the source video.
7. An apparatus for multiple image frame synchronization display, the apparatus comprising: a memory and at least one processor, the memory having instructions stored therein, the memory and the at least one processor being interconnected by a line;
the at least one processor invoking the instructions in the memory to cause the apparatus for multi-path image frame synchronization display to perform the method of multi-path image frame synchronization display of any of claims 1-5.
8. A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements a method of simultaneous display of multiple image frames according to any of claims 1-5.
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