CN116167322A - Circuit simulation method and device, server and storage medium - Google Patents

Abstract

The invention discloses a circuit simulation method and device, a server and a storage medium. The circuit simulation method comprises the steps of obtaining a circuit netlist, wherein the circuit netlist comprises at least two wire mesh layers; acquiring port information in the circuit netlist and space constraint values corresponding to different wire mesh layers, wherein the port information comprises port graphics; obtaining a first forbidden region according to a port graph on an original layout and a space constraint value corresponding to a wire network layer to which the port graph belongs; and carrying out wiring design according to the port information and the first forbidden area, wherein the first forbidden area forbids wiring. According to the circuit simulation method and device, the server and the storage medium, violation of design rules can be avoided, and wiring quality is improved.

Description

Circuit simulation method and device, server and storage medium

Technical Field

The present invention relates to the field of integrated circuit simulation technologies, and in particular, to a circuit simulation method and apparatus, a server, and a storage medium.

Background

With the rapid development of very large scale integrated circuits and their wide application, the design and process requirements of chips are becoming more and more complex, and electronic design automation (Electronic design automation, EDA) tools are becoming an indispensable auxiliary design tool in the chip design field.

In the chip wiring stage, corresponding design rules are read according to the process requirements, and under the premise that the design rules are met, the EDA tool connects all modules or pins according to the given connection relation in the netlist. In the whole chip design process, the design rules directly influence the final chip manufacture, and in order to ensure the normal manufacture of the chip, certain design rules need to be considered in the wiring process.

In the prior art, the spacing between the same-layer metals is required, and the same-layer metals cannot be too close together, so that a minimum spacing is required, otherwise, the manufacturing of the chip is affected. However, the conventional router cannot ensure the spacing between the same-layer metals.

Accordingly, a new circuit simulation method and apparatus, server, and storage medium are desired to solve the above-described problems.

Disclosure of Invention

In view of the foregoing, an object of the present invention is to provide a circuit simulation method and apparatus, a server, and a storage medium, so as to avoid violating design rules and improve wiring quality.

According to one aspect of the invention, a circuit simulation method is provided, which comprises the steps of obtaining a circuit netlist, wherein the circuit netlist comprises at least two wire mesh layers; acquiring port information in the circuit netlist and space constraint values corresponding to different wire mesh layers, wherein the port information comprises port graphics; obtaining a first forbidden region according to a port graph on an original layout and a space constraint value corresponding to a wire network layer to which the port graph belongs; and carrying out wiring design according to the port information and the first forbidden area, wherein the first forbidden area forbids wiring.

Optionally, the port information further includes at least one of a network layer to which the port belongs and a port type.

Optionally, the obtaining the first forbidden area according to the port graph on the original layout and the pitch constraint value corresponding to the wire mesh layer to which the port graph belongs includes setting an area, which does not satisfy the pitch constraint value with the pitch of the port graph, as the first forbidden area, and recording the position of the first forbidden area on a map.

Optionally, the circuit simulation method further comprises the steps of obtaining existing wiring and a wire network layer to which the existing wiring belongs; and setting an area, which does not meet the pitch constraint value corresponding to the wire mesh layer to which the existing wire belongs, as a second forbidden area, wherein the second forbidden area forbids newly added wires.

Optionally, the circuit simulation method further includes using a port to be connected in the circuit netlist as a source point, expanding to at least one direction according to a dijkstra algorithm, and recording an expanded direction of the source point.

Optionally, in the expansion process, when the current expansion direction is different from the expanded direction, backtracking to a last turning point in the expansion process, and obtaining a third forbidden area according to the current expansion direction, the last turning point and the spacing constraint value, wherein the third forbidden area is used for wire arrangement forbidden.

Optionally, the circuit simulation method further comprises searching according to the dijkstra algorithm until points extending from the source point are connected; backtracking along the source point after the Di Jie Style algorithm search is finished, and obtaining a wiring point chain; and wiring is carried out along the wiring point chain.

Optionally, the circuit simulation method further includes traversing the wiring point chain, and judging whether the situation of violating the space constraint value exists; and when judging that the space constraint value is violated, carrying out post-processing on the wiring, wherein the post-processing on the wiring comprises wiring widening and/or wiring moving so as to obtain the corrected wiring.

Optionally, the post-processing the wiring includes performing the wiring widening according to a value with a smaller width in the patterns at both ends of the wiring; when pins are at both ends of the wiring, the post-processing the wiring includes moving the wiring.

Optionally, when the minimum distance between the corresponding patterns of two ports in the same wire mesh layer is less than or equal to zero, the two ports together form one port pattern.

According to another aspect of the present invention, there is provided a circuit simulation device, including an obtaining unit, configured to obtain a circuit netlist, where the circuit netlist includes at least two net layers, and the obtaining unit is further configured to obtain port information in the circuit netlist and pitch constraint values corresponding to different net layers, where the port information includes a port pattern; the constraint unit is used for obtaining a first forbidden area according to the port graph on the original layout and the space constraint value corresponding to the wire mesh layer to which the port graph belongs; and a wiring unit configured to perform wiring design according to the port information and the first prohibited area, wherein the first prohibited area prohibits wiring.

According to yet another aspect of the present invention, there is provided a server including a processor; a memory for storing one or more programs; wherein the one or more programs, when executed by the processor, cause the processor to implement the circuit emulation method as described above.

According to still another aspect of the present invention, there is provided a computer-readable storage medium having stored thereon a computer program, wherein the program, when executed by a processor, implements the circuit emulation method as described above.

According to the circuit simulation method and device, the server and the storage medium, the first forbidden area is determined according to the spacing constraint values of different wire layers to realize wiring design, the minimum spacing requirement of the same wire layer is supported, the violation of design rules can be avoided, and the wiring quality is improved.

Further, wiring is performed by using methods such as marking and backtracking, so that different situations can be handled, the application range is wide, the coverage scenes are more, and the success rate is high.

Further, after the initial wiring is obtained, post-processing is performed to cover more scenes, so that the success rate is high.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a method flowchart of a circuit simulation method according to a first embodiment of the present invention.

Fig. 2 shows a method flowchart of a circuit simulation method according to a second embodiment of the present invention.

Fig. 3 shows a schematic diagram of minimum pitches according to a second embodiment of the present invention.

Fig. 4 shows a schematic marking diagram according to a second embodiment of the present invention.

Fig. 5 shows an illegal wiring schematic according to a second embodiment of the present invention.

Fig. 6 shows a schematic diagram of legal layout according to a second embodiment of the invention.

Fig. 7 shows a backtracking schematic according to a second embodiment of the present invention.

Fig. 8 shows a wiring schematic according to a second embodiment of the present invention.

Fig. 9 shows a wiring widening schematic diagram according to a second embodiment of the present invention.

Fig. 10 shows a wiring movement diagram according to a second embodiment of the present invention.

Fig. 11 shows a wiring widening schematic diagram according to a second embodiment of the present invention.

Fig. 12 shows a method flowchart of a circuit simulation method according to a third embodiment of the present invention.

Fig. 13 shows a schematic diagram of an operation interface according to a third embodiment of the present invention.

Fig. 14 shows a schematic diagram of a wiring result according to the third embodiment of the present invention.

Fig. 15 shows a schematic structural diagram of a circuit simulation device according to an embodiment of the present invention.

Fig. 16 shows a schematic structural diagram of a server according to an embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.

The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. Numerous specific details of the invention, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

It will be understood that when a layer, an area, or a structure is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or another layer or area can be included between the layer and the other layer, another area. And if the component is turned over, that layer, one region, will be "under" or "beneath" the other layer, another region.

A through hole generation method meeting minimum spacing/spacing constraint value (Min Notch) constraint in integrated circuit layout wiring is a method for selecting an optimal routing path based on Min Notch constraint in the wiring process of an EDA tool, wherein the constraint is the same net (net layer) minimum spacing constraint (same net spacing), and the same net refers to pins, metals and through holes on the same wire net, and the pins, the metals and the through holes are required to be connected together to meet a circuit connection relation. The application relates to the technical field of EDA design, in particular to a wiring method for meeting Min Notch of an integrated circuit layout. The total path length of the wiring is minimized on the premise that the design rule check (Design rules checking, DRC) is satisfied.

Fig. 1 shows a method flowchart of a circuit simulation method according to a first embodiment of the present invention. As shown in fig. 1, the circuit simulation method according to the first embodiment of the present invention includes the following steps:

in step S101, a circuit netlist is obtained;

a circuit netlist is obtained, wherein the circuit netlist comprises at least two net layers. Each net layer includes at least one of pins, metal, vias, and the like, which are connected together to satisfy a circuit connection relationship.

In step S102, obtaining port information in the netlist and pitch constraint values corresponding to different wire layers;

and acquiring port information in the circuit netlist and space constraint values corresponding to different wire layers, wherein the port information comprises port graphics. Optionally, the port information further includes at least one of a network layer to which the port belongs, a port type, and the like. Optionally, the circuit netlist comprises a first net layer and a second net layer. The first net layer corresponds to a first pitch constraint value and the second net layer corresponds to a second pitch constraint value. The first pitch constraint value and the second pitch constraint value may be the same or different.

In step S103, a first forbidden area is obtained according to the port graph on the original layout and the constraint value corresponding to the wire network layer to which the port graph belongs;

and obtaining a first forbidden area (corresponding to the wire mesh layer) according to the port graph on the original layout and the constraint value corresponding to the wire mesh layer to which the port graph belongs.

In step S104, wiring design is performed based on the port information and the first prohibition area.

And performing (circuit simulation) wiring design according to the port information and the first forbidden area, wherein the wiring is forbidden in the first forbidden area.

In an alternative embodiment of the present invention, the circuit emulation method further comprises: acquiring an existing wiring and a wire network layer to which the existing wiring belongs; and setting an area, which does not meet the pitch constraint value corresponding to the wire mesh layer to which the existing wire belongs, as a second forbidden area, wherein the second forbidden area forbids the newly added wire. Optionally, in the wiring process, a region which does not satisfy the pitch constraint value with the existing wiring pitch is set as the second forbidden region, and after the newly added wiring is completed, the newly added wiring is taken as the existing wiring.

Fig. 2 shows a method flowchart of a circuit simulation method according to a second embodiment of the present invention. As shown in fig. 2, a second circuit simulation method according to an embodiment of the present invention includes the following steps:

in step S201, obtaining circuit netlist information;

obtaining circuit netlist information, reading port graphics of all nets in a wiring input file, wherein the port graphics comprise the size and the hierarchy of the port graphics, the interval rule of each (net) layer and minimum spacing constraint information (comprising a net layer where constraint is located and a corresponding spacing constraint value). As shown in connection with fig. 3, the distance between port patterns needs to satisfy a constraint value (min notch spacing) greater than the pitch.

In step S202, a first forbidden area is established;

a first prohibition region is established, wherein wiring is prohibited in the first prohibition region. Alternatively, an area whose pitch from the port pattern does not satisfy the pitch constraint value is set as a first prohibited area, and the position of the first prohibited area is recorded on the map. Optionally, the graph on the original layout is marked (to establish a first forbidden area), and the position of the graph after the graph is expanded (the graph is expanded, namely, the area where the marking of the graph and net routing can occur same net spacing violation, namely, the first forbidden area) is recorded on the map. Referring to fig. 4, the marked area is a hollowed rectangle, specifically, the marked pattern is expanded. Optionally, the mark is used for solving the problem of notch caused by multiple searches of the same net, and the mark is the annular area of the metal pattern subtracted after the metal pattern is externally expanded by MinNotch spacing.

In an alternative embodiment of the present invention, when the minimum distance between the corresponding patterns of two ports in the same net layer is less than or equal to zero, the two ports together form one port pattern. Specifically, if the distance between the metal patterns of the two same net layers is smaller than Min Notch Spacing, the design rule is violated, but if the distance between the metal patterns of the two same net layers is smaller than or equal to 0, that is, the metal patterns are contacted, the metal patterns are regarded as one pattern, and the design rule is not violated.

In step S203, an initial wiring is planned;

planning to obtain initial wiring. Optionally, the ports in the circuit netlist that need to be connected are used as source points, expanded in at least one direction according to the dijkstra algorithm, and the expanded direction (of the source points) is recorded. Further, in the expansion process, when the current expansion direction is different from the expanded direction, backtracking to the last turning point in the expansion process, and obtaining a third forbidden area according to the current expansion direction, the last turning point and the spacing constraint value, wherein the third forbidden area is used for wire arrangement inhibition. Optionally searching according to the dijkstra algorithm until points extending from the source point are connected; backtracking along a source point after the Di Jie Style algorithm search is finished, and obtaining a wiring point chain; and wiring is carried out along the wiring point chain, so that initial wiring is obtained.

In one embodiment, points on pins (ports) that need to be connected are used as source points, and the Di Jie St-Law algorithm is used to expand to various directions, and the direction in which each point (source point/expansion point) is expanded is recorded.

When expanding, searching for a mark map, if the distance between the mark map and a metal pattern of a same wire mesh layer (net) is smaller than a distance constraint value (Min Notch), increasing the cost (obtaining a third forbidden area), and thus avoiding wiring. In other words, during the expansion process, if the current node is marked in same net spacing map, it is indicated that same net spacing violation would occur if the current node is routed to, requiring a larger routing cost, avoiding forbidden areas. As shown in connection with fig. 5, if the current point is within the marked area, the constraint may be violated, and a cost may need to be added; if not, legal and no cost is added. In connection with fig. 6, there are two possibilities for the legitimacy, one in which the current point is far from the marked pattern and the other in which the current point is in contact with the marked pattern.

When expanding, if the current expanding direction is different from the direction of expanding the point, describing to turn, at the moment, backtracking to the last turning point, calculating the distance between the two turning points, and if the distance is smaller than the distance constraint value, increasing the cost (the increased cost is the length required to be increased after the wiring is changed). In the backtracking process, as shown in connection with fig. 7, backtracking is reversed along the extended direction of each point until the last curve point is found. In the application, marking and backtracking are used for solving different situations, and backtracking solves Notch caused by the same search; the Notch caused by the multiple searches needs to be resolved by labeling as shown in fig. 8.

Optionally, during the expansion process, the costly node may be pressed at the end of the queue, and the maze algorithm itself pops up the less costly node to expand, that is, preferentially selects the routing path without same net violation.

The search continues until points that extend from the source point are connected. And after the Di Jie Style algorithm search is finished, backtracking along the source point to obtain a point chain. The initial wiring (i.e., the first-obtained metal line) is obtained along the chain of points.

In step S204, it is checked whether the initial wiring violates the constraint, resulting in a final wiring.

And checking whether the initial wiring violates the constraint of the spacing constraint value to obtain the final wiring. For example, traversing a chain of points, if a violation of a pitch constraint occurs, post-processing is required, which may be by widening the metal line. Optionally traversing the wired point chain to judge whether the condition of violating the space constraint value exists; when it is determined that there is a violation of the pitch constraint value, post-processing is performed on the (initial) wiring. Wherein post-processing the initial wire includes wire widening and/or wire shifting to obtain a corrected wire. Optionally, performing wire widening according to a smaller width value in the patterns at two ends of the wire; where the two ends of the wire are pins, post-processing the wire includes moving (initial) the wire.

In one particular embodiment of the invention, the end (port) of the wiring (wire) includes at least three cases: turns, pins, and vias. Post-processing is used to handle the case where there is no corner at both ends, but rather a pin. The processing method is to widen the metal line, wherein the widened width is a smaller value of the width of the patterns at the two ends. The situation that one end turns is solved by backtracking in searching, and the situation that post-processing is needed comprises the following three types: pins are arranged at both ends; one end is a pin, and the other end is a through hole; both ends are through holes.

When widening the metal line, selecting the smaller value of the pattern width at the two ends. Where the two ends are pins, DRC may still be violated even if widened, as shown in fig. 9, since the metal wire does not have to be routed out in the center of the pins. At this time, it is necessary to move the wire as shown in fig. 10.

When the projection of the large-width pins cannot cover the projection of the small-width pins, the width of the metal line widened at this time is not the width of the pins, but the distance between the closer edges of the two pins, as shown in fig. 11.

Fig. 12 shows a method flowchart of a circuit simulation method according to a third embodiment of the present invention. As shown in fig. 12, a specific wiring method of the circuit simulation method according to the third embodiment of the present invention includes the steps of:

in step S301, initializing layout data and process constraints;

initializing layout data and process constraints. Alternatively, as shown in fig. 13, the router is opened and clicks are made to route. And reading the graph on the layout and Min Notch constraint.

In step S302, marking a layout graph;

the layout pattern is marked, for example, with reference to fig. 4. When punching or routing within the marked area, the cost is increased (i.e., the marked area is avoided).

In step S303, a search is performed from the source point;

starting from the source point, searching, performing path searching by using Di Jie St-Law algorithm, searching for the map of the mark, and adding cost if the map violates Min Notch DRC.

In step S304, a dot chain is obtained, and post-processing is performed.

After the dot chain is obtained, wiring (metal wire) is generated, and the metal wire is post-processed. The wiring result is referred to fig. 14.

According to another aspect of the present invention, there is provided a circuit simulation apparatus for implementing the above-described circuit simulation method. As shown in fig. 15, in one embodiment of the present invention, the circuit simulation apparatus includes an acquisition unit 310, a constraint unit 320, and a wiring unit 330.

In particular, the obtaining unit 310 is configured to obtain a circuit netlist, where the circuit netlist includes at least two net layers. The obtaining unit 310 is further configured to obtain port information in the circuit netlist and pitch constraint values corresponding to different net layers, where the port information includes a port graph.

The constraint unit 320 is configured to obtain a first forbidden area according to the port pattern on the original layout and the pitch constraint value corresponding to the net layer to which the port pattern belongs.

The wiring unit 330 is used for performing wiring design according to the port information and the first prohibited area, wherein the first prohibited area prohibits wiring.

Fig. 16 shows a schematic structural diagram of a server according to an embodiment of the present invention. Referring to fig. 16, the present disclosure also presents a block diagram of an exemplary server suitable for use in implementing embodiments of the present disclosure. It should be understood that the server shown in fig. 16 is only an example, and should not be construed as limiting the functionality and scope of use of the disclosed embodiments.

As shown in fig. 16, the server 200 is in the form of a general purpose computing device. The components of server 200 may include, but are not limited to: one or more processors or processing units 210, a memory 220, a bus 201 that connects the various system components, including the memory 220 and the processing units 210.

Bus 201 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, micro channel architecture (MAC) bus, enhanced ISA bus, video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

Server 200 typically includes a variety of computer system readable media. Such media can be any available media that is accessible by server 200 and includes both volatile and nonvolatile media, removable and non-removable media.

The system memory 220 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 221 and/or cache memory 222. Server 200 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 223 may be used to read from or write to non-removable, nonvolatile magnetic media (not shown in FIG. 16, commonly referred to as a "hard disk drive"). Although not shown in fig. 16, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be coupled to bus 201 through one or more data medium interfaces. Memory 220 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of embodiments of the present disclosure.

Programs/utilities 224 having a set (at least one) of program modules 2241 may be stored in, for example, memory 220, such program modules 2241 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 2241 generally perform the functions and/or methods in the embodiments described in the embodiments of the disclosure.

Further, the server 200 may also be communicatively coupled to a display 300 for displaying the results of the screening ranking, and the display 300 may include, but is not limited to, a Liquid Crystal Display (LCD), a Light Emitting Diode (LED) display, and a plasma display. In some embodiments, the display 300 may also be a touch screen.

Further, the server 200 may also communicate with one or more devices that enable a user to interact with the server 200, and/or with any device (e.g., network card, modem, etc.) that enables the server 200 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 230. Also, the server 200 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through a network adapter 240. As shown, network adapter 240 communicates with other modules of server 200 over bus 201. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with server 200, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

The processing unit 210 executes various functional applications and data processing by running programs stored in the system memory 220, for example, implementing a circuit simulation method for a device modeling tool provided by an embodiment of the present disclosure.

Embodiments of the present invention also provide a computer-readable storage medium having stored thereon a computer program (or referred to as computer-executable instructions) which, when executed by a processor, is configured to perform a circuit simulation method provided by an embodiment of the present disclosure, the method comprising: obtaining a circuit netlist, wherein the circuit netlist comprises at least two wire mesh layers; acquiring port information in the circuit netlist and space constraint values corresponding to different wire mesh layers, wherein the port information comprises port graphics; obtaining a first forbidden region according to the port graph on the original layout and the space constraint value corresponding to the wire mesh layer to which the port graph belongs; and carrying out wiring design according to the port information and the first forbidden area, wherein the first forbidden area forbids wiring.

The computer storage media of the embodiments of the present disclosure may take the form of any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for embodiments of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (13)

1. A circuit emulation method, comprising:

obtaining a circuit netlist, wherein the circuit netlist comprises at least two wire mesh layers;

acquiring port information in the circuit netlist and space constraint values corresponding to different wire mesh layers, wherein the port information comprises port graphics;

obtaining a first forbidden region according to a port graph on an original layout and a space constraint value corresponding to a wire network layer to which the port graph belongs;

and carrying out wiring design according to the port information and the first forbidden area, wherein the first forbidden area forbids wiring.

2. The circuit emulation method of claim 1, wherein the port information further comprises at least one of a net layer to which the port belongs and a port type.

3. The circuit simulation method according to claim 1, wherein the obtaining the first forbidden area according to the port pattern on the original layout and the pitch constraint value corresponding to the wire mesh layer to which the port pattern belongs includes:

and setting an area, of which the distance from the port graph does not meet the distance constraint value, as the first forbidden area, and recording the position of the first forbidden area on a map.

4. The circuit emulation method of claim 1, wherein the circuit emulation method further comprises:

acquiring an existing wiring and a wire network layer to which the existing wiring belongs;

setting a region where the pitch of the existing wiring does not satisfy a pitch constraint value corresponding to a net layer to which the existing wiring belongs as a second inhibition region,

wherein the second prohibition area prohibits the newly added wiring.

5. The circuit emulation method of claim 1, wherein the circuit emulation method further comprises:

and taking a port to be connected in the circuit netlist as a source point, expanding to at least one direction according to a Di-Jie-Tesla algorithm, and recording the expanded direction of the source point.

6. The circuit simulation method of claim 5 wherein, in the expansion process, when a current expansion direction is different from the expanded direction, backtracking to a last corner point of the expansion process, and obtaining a third forbidden region according to the current expansion direction, the last corner point and the spacing constraint value,

wherein the third prohibition region prohibits wiring.

7. The circuit emulation method of claim 5, wherein the circuit emulation method further comprises:

searching according to the Di-Jie-St algorithm until points extending from the source point are connected;

backtracking along the source point after the Di Jie Style algorithm search is finished, and obtaining a wiring point chain;

and wiring is carried out along the wiring point chain.

8. The circuit emulation method of claim 7, wherein the circuit emulation method further comprises:

traversing the wiring point chain, and judging whether the situation of violating the space constraint value exists or not;

when it is judged that the space constraint value is violated, post-processing is performed on the wiring,

wherein the post-processing of the wiring includes wiring widening and/or wiring shifting to obtain a corrected wiring.

9. The circuit emulation method of claim 8, wherein the post-processing the wiring comprises:

the wiring widening is carried out according to the smaller width value in the patterns at the two ends of the wiring;

when pins are at both ends of the wiring, the post-processing the wiring includes moving the wiring.

10. The circuit emulation method of claim 1, wherein two ports in the same net layer collectively form a port pattern when a minimum spacing of corresponding patterns of the two ports is less than or equal to zero.

11. A circuit emulation device, comprising:

the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring a circuit netlist, the circuit netlist comprises at least two wire mesh layers, and the acquisition unit is also used for acquiring port information in the circuit netlist and space constraint values corresponding to different wire mesh layers, wherein the port information comprises port graphics;

the constraint unit is used for obtaining a first forbidden area according to the port graph on the original layout and the space constraint value corresponding to the wire mesh layer to which the port graph belongs;

and a wiring unit configured to perform wiring design according to the port information and the first prohibited area, wherein the first prohibited area prohibits wiring.

12. A server, comprising:

a processor;

a memory for storing one or more programs;

wherein the one or more programs, when executed by the processor, cause the processor to implement the circuit emulation method of any one of claims 1 to 10.

13. A computer readable storage medium having stored thereon a computer program, wherein the program when executed by a processor implements the circuit emulation method according to any one of claims 1 to 10.

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