CN116166572A

CN116166572A - System configuration and memory synchronization method and device, system, equipment and medium

Info

Publication number: CN116166572A
Application number: CN202310226874.8A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Biren Intelligent Technology Co Ltd
Current assignee: Shanghai Biren Intelligent Technology Co Ltd
Priority date: 2023-03-08
Filing date: 2023-03-08
Publication date: 2023-05-26

Abstract

A system configuration method, a memory synchronization method, a system configuration device, a memory synchronization device, a processing system, an electronic device, and a computer readable storage medium. The system configuration method comprises the following steps: acquiring a first memory space of first equipment, wherein the first memory space corresponds to a second memory space of second equipment; the method includes configuring a first function configured to be invoked when a first memory space is accessed by a first access request to trigger an access error event, the first function including performing an access operation corresponding to the first access request, and including performing a memory synchronization operation associated with the first access request for a second memory space relative to the first memory space. The method has wide applicability and can ensure the consistency of memories at the front end and the rear end.

Description

System configuration and memory synchronization method and device, system, equipment and medium

Technical Field

Embodiments of the present disclosure relate to a system configuration method, a memory synchronization method, a system configuration apparatus, a memory synchronization apparatus, a processing system, an electronic device, and a computer-readable storage medium.

Background

The computer utilizes processors to implement data operations, different processors can meet different computing requirements, for example, GPUs (Graphics Processing Unit, graphics processors) can be used for image processing, AI accelerators such as GPGPUs (general purpose graphics processors), TPUs (tensor processors), NPUs (Neural network Processing, neural network processors) can be used for neural network computation, etc., and clusters can be formed for passing through cloud services, etc. If some computation is required, a device may be configured with a corresponding type of processor to perform the computation using a local processor, or the local device may be caused to communicate with another device or devices that are remote via a local area network or a wide area network to perform the computation using a remote processor.

Disclosure of Invention

At least one embodiment of the present disclosure provides a system configuration method for a first device, where the first device communicates with a second device, the system configuration method including: acquiring a first memory space of the first device, wherein the first memory space corresponds to a second memory space of the second device; a first function is configured, wherein the first function is configured to be invoked when the first memory space is accessed by a first access request to trigger an access error event, the first function comprising performing an access operation corresponding to the first access request, and comprising performing a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space.

For example, the system configuration method provided in an embodiment of the present disclosure further includes: the first memory space is configured to be in an inaccessible state to trigger the access error event when the first memory space is accessed by the first access request.

For example, in a system configuration method provided by an embodiment of the present disclosure, the access error event includes a segment error event; the first function is a callback function registered corresponding to the segment error event.

For example, in a system configuration method provided in an embodiment of the present disclosure, the first function further includes: before executing the memory synchronization operation and the access operation, changing the first memory space from the inaccessible state to an accessible state; and after performing the memory synchronization operation and the access operation, altering the first memory space from the accessible state back to the inaccessible state.

For example, in a system configuration method provided in an embodiment of the present disclosure, obtaining a first memory space of the first device includes: and recording a first memory address space allocated by the first device as the first memory space according to a program interface related to memory allocation provided by the first device.

For example, the system configuration method provided in an embodiment of the present disclosure further includes: and allocating a second memory address space corresponding to the first memory address space by the second device through negotiation of the first device and the second device, and taking the second memory address space as the second memory space.

At least one embodiment of the present disclosure provides a memory synchronization method for a first device, where the first device includes a first memory space, the first device communicates with a second device, the second device includes a second memory space corresponding to the first memory space, and the memory synchronization method includes: triggering an access error event corresponding to the first memory space in response to a first access request for the first memory space; in response to the access error event, a first function is invoked to perform an access operation corresponding to the first access request, and to perform a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space.

For example, in the memory synchronization method provided in an embodiment of the present disclosure, the first memory space is configured to be in an inaccessible state to trigger the access error event when the first memory space is accessed by the first access request.

For example, in the memory synchronization method provided in an embodiment of the present disclosure, the access error event includes a segment error event; the first function is a callback function registered corresponding to the segment error event.

For example, the memory synchronization method provided in an embodiment of the present disclosure further includes: before executing the memory synchronization operation and the access operation, changing the first memory space from the inaccessible state to an accessible state; and after performing the memory synchronization operation and the access operation, altering the first memory space from the accessible state back to the inaccessible state.

For example, in the memory synchronization method provided in an embodiment of the present disclosure, the first access request is a read request, and the first access request includes a first access address; performing an access operation corresponding to the first access request, and performing a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space, comprising: receiving first data to be synchronized in the second memory space sent by the second device, wherein the first data to be synchronized comprises data stored in a position corresponding to the first access address in the second memory space; writing the first data to be synchronized into the corresponding position of the first memory space; and reading the data stored by the first access address from the first memory space.

For example, in the memory synchronization method provided in an embodiment of the present disclosure, the first access request is a write request, where the first access request includes data to be written and a first access address; performing an access operation corresponding to the first access request, and performing a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space, comprising: writing the data to be written into a position corresponding to the first access address in the first memory space; and transmitting second data to be synchronized of the first memory space to the second device, so that the second device writes the second data to be synchronized into the second memory space, wherein the second data to be synchronized comprises data stored in a position corresponding to the first access address in the first memory space.

For example, in the memory synchronization method provided in an embodiment of the present disclosure, a first memory address space allocated by the first device for the first memory space corresponds to a second memory address space allocated by the second device for the second memory space; the first access request includes a first access address; the address range of the memory synchronization operation is a first address segment in the first memory space where the first access address is located and a second address segment in the second memory space corresponding to the first address segment.

For example, in the memory synchronization method provided in an embodiment of the present disclosure, the first device further communicates with N devices other than the second device, where the N devices include N predetermined memory spaces corresponding to the first memory space, respectively, and the memory synchronization method further includes: and executing memory synchronization operation for the N preset memory spaces relative to the first memory space, which is associated with the first access request, by using the first function. Wherein N is an integer greater than or equal to 1.

For example, in the memory synchronization method provided in an embodiment of the present disclosure, the first device performs a computing task by using a processor of the second device, and the second memory space is used to store data to be processed and processing result data of the processor, where the processor includes a graphics processor or a general-purpose graphics processor.

For example, in a memory synchronization method provided in an embodiment of the present disclosure, performing an access operation corresponding to the first access request, and performing a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space, includes: generating a first synchronous task based on the first access request, and adding the first synchronous task into a task queue; and executing tasks in the task queue in sequence, wherein when the first synchronous task is executed, an access operation corresponding to the first access request is executed, and a memory synchronous operation relative to the first memory space, which is associated with the first access request, is executed for the second memory space.

The present disclosure also provides a memory synchronization method for a system including a first device and a second device, where the first device includes a first memory space, and the second device includes a second memory space corresponding to the first memory space, and the memory synchronization method includes: triggering an access error event corresponding to the first memory space in response to a first access request for the first memory space; in response to the access error event corresponding to the first memory space, a first function is called to perform an access operation corresponding to the first access request, and a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space is performed.

For example, the memory synchronization method provided in an embodiment of the present disclosure further includes: triggering an access error event corresponding to the second memory space in response to a second access request for the second memory space; in response to the access error event corresponding to the second memory space, a second function is called to perform an access operation corresponding to the second access request, and a memory synchronization operation associated with the second access request for the first memory space relative to the second memory space is performed.

The present disclosure also provides a memory synchronization apparatus, configured to be used in a first device, where the first device includes a first memory space, the first device communicates with a second device, the second device includes a second memory space corresponding to the first memory space, and the memory synchronization apparatus includes a first response unit and a second response unit, where the first response unit is configured to trigger an access error event corresponding to the first memory space in response to a first access request for the first memory space; the second response unit is configured to invoke a first function in response to the access error event, to perform an access operation corresponding to the first access request, and to perform a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space.

The present disclosure also provides, in at least one embodiment, a processing system including a first device and a second device, the first device including a first memory space; the second device communicates with the first device and comprises a second memory space corresponding to the first memory space; wherein the first device is configured to: triggering an access error event corresponding to the first memory space in response to a first access request for the first memory space; in response to the access error event, a first function is invoked to perform an access operation corresponding to the first access request, and to perform a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space.

At least one embodiment of the present disclosure provides an electronic device comprising a processor; a memory storing one or more computer program modules; wherein the one or more computer program modules are configured to be executed by the processor for implementing the system configuration method and the memory synchronization method provided by any of the embodiments of the present disclosure.

At least one embodiment of the present disclosure provides a computer-readable storage medium storing non-transitory computer-readable instructions that, when executed by a computer, implement the system configuration method and the memory synchronization method provided by any of the embodiments of the present disclosure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1 is a schematic diagram of a memory synchronization;

FIG. 2 illustrates a flow chart of a system configuration method provided by at least one embodiment of the present disclosure;

FIG. 3 is a flow chart illustrating a method for memory synchronization according to at least one embodiment of the present disclosure;

FIG. 4 illustrates a process flow diagram provided by at least one embodiment of the present disclosure;

FIG. 5 illustrates a schematic block diagram of a memory synchronization device provided in at least one embodiment of the present disclosure;

FIG. 6 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure;

FIG. 7 illustrates a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure; and

fig. 8 illustrates a schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

Fig. 1 shows a schematic diagram of a memory synchronization.

The first device A1 at the front end may be connected to the second device A2 at the back end through a network to perform calculations using the processor of the second device A2, and a GPU (which is also used herein to include a GPGPU) is described as an example. For example, the first device A1 at the front end contains a CPU (Central Processing Unit, central processor) without a GPU, while the second device A2 at the remote end contains a CPU and a GPU. The first device A1 may locally set (provide) a virtual GPU, and synchronize, by using the remote system, the user's operation on the local virtual GPU into the remote second device A2, so as to complete the user's calculation request by using the real GPU of the second device A2. The remote system may be understood as a system capable of intercepting operations of the front and rear ends related to a processor (such as a GPU) and of achieving interaction and synchronization of the front and rear ends.

In order to achieve the above-mentioned purpose of remotely using the GPU, it is necessary to keep the data consistency of the front and rear ends, that is, to synchronize the related memory spaces of the first device A1 and the second device A2, for example, the first device A1 stores the data to be processed in a local memory space, and by performing the memory synchronization operation on the two ends, the data to be processed can be synchronized to the corresponding memory space of the second device A2, so that the second device A2 performs the operation processing based on the data to be synchronized. Similarly, after the processing result data is obtained, the second device A2 stores the processing result data in the memory space of the second device A2, and the processing result data can be synchronized into the corresponding memory space of the first device A1 by performing the memory synchronization operation on both ends. Based on the memory synchronization operation, the remote use of the front-end to the back-end GPU and other devices is realized.

For example, a GPU vendor may provide a user with relevant APIs (Application Programming Interface, application program interfaces) for memory allocation, access, release, etc. to enable GPU-related operations. The remote system can realize the memory synchronization of the front end and the rear end based on an Application Program Interface (API) interception and forwarding mechanism of the GPU heterogeneous model, and ensures the data consistency of the memories of the front end and the rear end by intercepting and forwarding the related application program interfaces such as memory allocation, access, release and the like disclosed by GPU manufacturers, wherein the data consistency is a prerequisite condition for normal and stable operation of the remote system.

The remote system can intercept and forward the public application program interface provided for the user by the GPU manufacturer, and is limited in the scope of the public application program interface, but cannot intercept the application program interface which is not disclosed by the GPU manufacturer, so that the consistency of the front end memory and the rear end memory in the scene cannot be ensured.

In addition, the completeness of the remote system to the known application program interfaces such as memory read-write operation and the like needs to be guaranteed, namely the application program interfaces for intercepting all the read-write operations disclosed are required to be guaranteed, and if omission occurs, or a GPU manufacturer adds a new application program interface and the GPU remote system is not adapted, the problem that memories on the two sides of the front end and the rear end are not synchronous is caused.

In addition, there are significant limitations in the current scenario of handling Unified Memory (Unified Memory). Unified memory is a memory that can support CPU and GPU access. In order to ensure the consistency of the memories at the front end and the rear end, under the unified memory scene, the application program interface call of the CPU for accessing the memories is required to be intercepted, and some unexpected memory accesses are inevitably intercepted while the application program interface call is intercepted, so that a list is required to be maintained by the remote system to filter out the unexpected accesses, and extra performance loss is brought to the remote system. And meanwhile, the CPU accesses a plurality of application program interfaces of the memory, so that the integrity of the intercepted application program interfaces is ensured, and the CPU is an obvious pain point.

Therefore, the above method for implementing memory synchronization by intercepting the application program interface provided by the GPU manufacturer has some limitations, and in some scenarios, the memory consistency of the front end and the back end cannot be ensured.

At least one embodiment of the present disclosure provides a system configuration method, a memory synchronization method, a system configuration apparatus, a memory synchronization apparatus, a processing system, an electronic device, and a computer-readable storage medium.

The system configuration method comprises the following steps: acquiring a first memory space of first equipment, wherein the first memory space corresponds to a second memory space of second equipment; the method includes configuring a first function configured to be invoked when a first memory space is accessed by a first access request to trigger an access error event, the first function including performing an access operation corresponding to the first access request, and including performing a memory synchronization operation associated with the first access request for a second memory space relative to the first memory space.

The memory synchronization method comprises the following steps: triggering an access error event corresponding to the first memory space in response to a first access request for the first memory space; in response to an access error event, a first function is invoked to perform an access operation corresponding to the first access request, and to perform a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space.

According to the system configuration method and the memory synchronization method, the first function and the first memory space are configured, so that an access error event is triggered when the first memory space is accessed, and the first function is further called. Based on the mode, the access request can be intercepted by utilizing the mechanism (access error mechanism) of the device operating system, and the first function is further called to execute the synchronous operation of the front end and the rear end, so that the application program interfaces of the memory access provided by the manufacturer are not required to be intercepted, the implementation mode and the openness of the application program interfaces provided by the manufacturer are not required to be considered, and the limitation of the mode of realizing the synchronous operation of the front end and the rear end by intercepting the application program interfaces provided by the manufacturer is overcome. The embodiment of the disclosure is realized by using a general mechanism of an operating system, has wide applicability, can realize memory synchronous operation aiming at various scenes, ensures the memory consistency at the front end and the rear end, and reduces the loss. In addition, the access operation can be executed while the memory synchronization operation is executed, so that the access to the first memory space can be smoothly executed.

Fig. 2 illustrates a flow chart of a system configuration method provided by at least one embodiment of the present disclosure, for example, for a first device of fig. 1, which communicates with a second device as described above. The first device comprises at least one processor (such as a CPU, a GPU/GPGPU, etc.), at least one memory, a communication device (such as a network card, etc.), and the first operating system is operated and controls and manages the hardware and software of the system in the first device, and allocates scheduling resources, such as file management, memory management, process management, input and output, etc.; likewise, the second device includes at least one processor (e.g., CPU, GPU/GPGPU, etc.), at least one memory, a communication device (e.g., network card), etc., in which a second operating system is running that controls, manages the hardware of the system in the second device, allocates scheduling resources, including, for example, file management, memory management, process management, input and output (I/O), etc. Embodiments of the present disclosure are not limited to the hardware configuration of the first device and the second device, the type of operating system, etc., for example, the CPU used may be based on an X86 architecture, an ARM architecture, a RISC-V architecture, etc., the GPU/GPGPU may be any commercially available product, and the operating system may use a system such as Linux, unix, android, etc.

For example, a first device may communicate with a second device, e.g., the first device may be communicatively coupled to the second device via a wireless or wired network, e.g., may cooperate with a variety of communication mechanisms (e.g., ethernet, RDMA (Remote Direct Memory Access, remote direct data access)), to improve access speed and data throughput. Embodiments of the present disclosure do not limit the manner in which communications between the first device and the second device are made.

For example, the first device and the second device each include a central processing unit CPU, and the first device and the second device have the same architecture of the CPU.

For example, the first device and the second device may be the same type of device or different types of devices, e.g., the first device and the second device may be desktops, cellphones, tablets, notebooks, workstations, servers, cloud services, etc.

As shown in fig. 2, the method may include steps S110 to S120.

Step S110: and acquiring a first memory space of the first device.

The first memory space of the first device corresponds to the second memory space of the second device.

Step S120: the first function is configured.

In a first operating system running in a first device, the first function is configured (e.g., registered) to be invoked when an access error event is triggered by a first memory space being accessed by a first access request, the first function comprising performing an access operation corresponding to the first access request, and comprising performing a memory synchronization operation associated with the first access request for a second memory space relative to the first memory space.

For example, in step S110, for example, the first memory space and the second memory space are allocated by the first operating system and the second operating system for the same computing task. For example, the first memory space of the first device is a segment of address space in the memory of the first device, the second memory space of the second device is a segment of address space in the memory of the second device, the addresses of the first memory space and the addresses of the second memory space have a corresponding relationship, and for any address of the first memory space, the addresses in the second memory space correspond to each other.

For example, the first memory space and the second memory space may have the same size in the first device and the second device, and in some examples, the first memory space may have the same size (i.e., capacity) as the second memory space, for example, the first memory space may have an address range of 0 to 99, the second memory space may have an address range of 300 to 399, a segment of the address in the first memory space may correspond to a segment of the address having the same size in the second memory space, and a fixed address offset may be provided between the corresponding addresses, for example, the address offset may be greater than or equal to 0, for example, the address offset may be 300 between the corresponding addresses of the first memory space (address range of 0 to 99) and the second memory space (address range of 300 to 399) in the above examples. In other examples, the first memory space and the second memory space may be different in size (i.e., capacity), for example, the first memory space may have an address of 0 to 99, the second memory space may have an address of 300 to 499, and a segment of the first memory space may correspond to a segment of the second memory space having a size twice that of the first memory space, where, for example, a lookup table may be maintained for the corresponding address space between the first memory space and the second memory space to achieve the memory space synchronization.

For example, the first device may perform a computing task with a processor of the second device, and the second memory space of the second device is used to store data to be processed and processing result data of the processor. For example, the processor may include a graphics processor GPU or a general purpose graphics processor GPGPU. Because the first memory space is synchronous with the second memory space, the first memory space is also related to the processor and is used for storing the data to be processed and the processing result data of the processor.

For example, in step S120, the first access request is an access request for a first memory space, i.e. the access address of the first access request is located in the first memory space.

For example, the first memory space may be access protected such that the first memory space cannot be normally accessed to trigger an access error event when the first memory space is accessed. For example, the first memory space may be configured to be in an inaccessible state, i.e., unreadable and unwritable, to trigger an access error event when the first memory space is accessed by the first access request. Thus, when the first memory space is accessed, the access to the first memory space is intercepted by the access error mechanism, and further the subsequent memory synchronization operation and access operation can be triggered based on the intercepted access request.

For example, the access error event may comprise a segment error event, for example, which may be triggered if the accessed memory exceeds the memory space allocated for the current program (e.g., process) by the operating system of the device. In other embodiments, the access error event may be other error events except for a segment error event, and any error triggered when the first memory space is accessed by performing access protection on the first memory space may be used as the access error event in the embodiments of the present disclosure.

For example, the first function may be a callback function corresponding to an access error event, e.g., the first function may be a callback function corresponding to a segment error event registration, i.e., invoking the first function upon occurrence of a segment error event, which passes required parameters to the callback function, e.g., the type of access operation currently to the first memory space (e.g., read or write), the memory address or memory address range for which the access operation is directed, etc.

For example, the first function may include code for performing an access operation and a memory synchronization operation such that the access operation and the memory synchronization operation may be triggered when the first function is invoked.

For example, the access operation may be a read operation or a write operation, and when the type of the first access request is a read request, data in the first memory space is read according to an access address of the first access request, for example, the read data is a result of an operation or an intermediate result; when the type of the first access request is a write request, data is written into the first memory space according to the access address of the first access request, for example, the written data is to be used for operation.

For example, a memory synchronization operation is associated with a first access request, and it is understood that data synchronized by the memory synchronization operation is associated with the first access request. The memory synchronization operation is a synchronization operation between the first memory space and the second memory space, i.e., an operation for implementing data synchronization of the first memory space and the second memory space. The memory synchronization operation may include the first device updating the data of the local first memory space with the received data, thereby requiring the synchronized updating of the data of the remote second memory space, or may include the removal of a portion of the data of the local first memory space, thereby requiring the updating of the data of the remote second memory space.

For example, the first function may further include: before performing the memory synchronization operation and the access operation, changing the first memory space from an inaccessible state to an accessible state; and after performing the memory synchronization operation and the access operation, changing the first memory space from the accessible state back to the inaccessible state.

For example, if the first memory space is configured in advance to be in the inaccessible state, the first memory space may be changed from the inaccessible state to the accessible state before each execution of the access operation and the memory synchronization operation, so as to execute the access operation and the memory synchronization operation. After each execution of the memory synchronization operation and the access operation, the first memory space may be changed from the accessible state back to the inaccessible state. In this way, when the next time an access request about the first memory space is received, an access error event may be triggered again, and the first function may be invoked to perform a corresponding access operation and a memory synchronization operation.

According to the system configuration method disclosed by the embodiment of the disclosure, the first function and the first memory space are configured, so that the access error event is triggered when the first memory space is accessed, and the first function is further called. Based on this way, the mechanism (access error mechanism) of the first operating system of the first device can be utilized to intercept the access request, and further the first function is called to execute the synchronous operation of the front end and the back end, so that an Application Program Interface (API) intercepting the memory access provided by the manufacturer is not needed, the implementation mode and the openness of the application program interface provided by the manufacturer are not needed to be considered, and the limitation of the mode of intercepting the application program interface provided by the manufacturer to realize the synchronous operation of the front end and the back end is overcome.

At least the embodiment of the disclosure is realized by using a general mechanism of an operating system, has wide applicability, can realize memory synchronous operation aiming at various scenes, ensures the memory consistency at the front end and the rear end, and reduces the loss. In addition, the access operation can be executed while the memory synchronization operation is executed, so that the access to the first memory space can be smoothly executed.

For example, in step S110, acquiring the first memory space of the first device may include: and recording the first memory address space allocated by the first device as the first memory space according to the program interface related to memory allocation provided by the first device. For example, the memory space may be allocated through an application program interface for memory allocation provided by the GPU manufacturer, for example, in some examples, the application program interface for memory allocation provided by the GPU manufacturer may be used to determine the size (capacity) of the address space to be allocated, and the size of the address space to be allocated may be obtained by intercepting the application program interface for memory allocation, so that the first operating system of the first device allocates a block of address space with a corresponding size from the locally available memory as the first memory space for use in the running computing task (e.g. process).

For example, the configuration method may further include: and through negotiation between the first device and the second device, a second operating system running on the second device allocates a second memory address space corresponding to the first memory address space as a second memory space. For example, after the first device allocates the first memory space, the first device may negotiate with the second device to enable the second device to allocate a corresponding second memory space. For example, the first device may send an allocation command to the second device, where the allocation command may include a size of an address space to be allocated and/or address information of the first memory space, and after the second device receives the allocation command, the second device allocates a corresponding block of address space from the memory of the second device as the second memory space. In the second device, the first memory space and the second memory space may be associated to obtain a corresponding relationship between the first memory space and the second memory space. The second device may also return (synchronize) address information of the second memory space to the first device, so that the first device may also maintain a correspondence between the first memory space and the second memory space.

Fig. 3 is a flowchart illustrating a memory synchronization method according to at least one embodiment of the present disclosure, for example, the memory synchronization method may be used for a first device, where the first device includes a first memory space, and the first device communicates with a second device, and the second device includes a second memory space corresponding to the first memory space. The first device comprises at least one processor (such as a CPU, a GPU/GPGPU, etc.), at least one memory, a communication device (such as a network card, etc.), and the first operating system is operated and controls and manages the hardware and software of the system in the first device, and allocates scheduling resources, such as file management, memory management, process management, input and output, etc.; likewise, the second device includes at least one processor (e.g., CPU, GPU/GPGPU, etc.), at least one memory, a communication device (e.g., network card), etc., in which a second operating system is running that controls, manages the hardware of the system in the second device, allocates scheduling resources, including, for example, file management, memory management, process management, input and output (I/O), etc.

As shown in fig. 3, the method may include steps S210 to S220.

Step S210: an access error event corresponding to the first memory space is triggered in response to a first access request for the first memory space.

Step S220: in response to an access error event, a first function is invoked to perform an access operation corresponding to the first access request, and to perform a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space.

For example, after the first function is configured in steps S110 and S120, when the first device receives a first access request for the first memory space and triggers an access error event corresponding to the first memory space in response to the first access request, the first function may be called, and the memory synchronization operation and the access operation may be performed by using the first function, which may be described in the embodiments of the system configuration method as to related content.

According to the memory synchronization method of at least one embodiment of the present disclosure, an access request may be intercepted by using a mechanism (access error mechanism) of an operating system of a device, and further, a first function is invoked to perform a synchronization operation of both front and rear ends, which does not need to intercept an application program interface of a memory access provided by a manufacturer, and does not need to consider an implementation manner and a disclosure of the application program interface provided by the manufacturer, so that a limitation of a manner of implementing a front and rear end synchronization operation by intercepting the application program interface provided by the manufacturer is overcome. The method and the device are realized by using a general mechanism of an operating system, have wide applicability, can realize memory synchronous operation aiming at various scenes, ensure the memory consistency at the front end and the rear end and reduce the loss. In addition, the access operation can be executed while the memory synchronization operation is executed, so that the access to the first memory space can be smoothly executed.

For example, since other memory spaces in the first device may trigger an access error event, in order to ensure that the memory synchronization operation is performed only for the access of the first memory space, it may be determined whether the memory address of the access request triggering the access error event is an address within the first memory space after the access error event is detected, if the memory address of the access request triggering the access error event is an address within the first memory space, the memory synchronization operation and the access operation may be performed based on the access request, and if the memory address of the access request triggering the access error event is not an address within the first memory space, the memory synchronization operation and the access operation may not be performed without responding to the access request.

For example, the first device invokes a processor of the second device to perform a computing task, and the second memory space is used to store data to be processed and processing result data of the processor, where the processor includes a graphics processor, an AI accelerator, and the like. The description of the related content in the embodiments of the system configuration method described above is omitted here.

For example, the first memory space may be configured to be in an inaccessible state to trigger an access error event when the first memory space is accessed by the first access request. The description of the related content in the embodiments of the system configuration method described above is omitted here.

For example, the access error event includes a segment error event; the first function is a callback function registered corresponding to the segment error event. The description of the related content in the embodiments of the system configuration method described above is omitted here.

For example, the memory synchronization method of the embodiment of the present disclosure may further include: before performing the memory synchronization operation and the access operation, changing the first memory space from an inaccessible state to an accessible state; and after performing the memory synchronization operation and the access operation, changing the first memory space from the accessible state back to the inaccessible state. The description of the related content in the embodiments of the system configuration method described above is omitted here.

For example, the first access request may be a read request, and the first access request may include a first access address, which is an address that the user wants to read. In this case, performing the access operation corresponding to the first access request, and performing the memory synchronization operation associated with the first access request for the second memory space with respect to the first memory space may include: receiving first data to be synchronized in a second memory space sent by a second device, wherein the first data to be synchronized comprises data stored in a position corresponding to a first access address in the second memory space; writing the first data to be synchronized into the corresponding position of the first memory space; and reading the data stored by the first access address from the first memory space.

For example, a first function is used to send a synchronization request to a second device, the second device reads data to be synchronized from a second memory space based on the synchronization request, and sends the data to be synchronized back to the first device as first data to be synchronized, and the first device updates the data in the first memory space by using the first data to be synchronized. The first data to be synchronized at least includes data corresponding to an access address of the first access request, for example, an address range of the first memory space is 0-99, an address range of the second memory space is 300-399, and if the access address of the first access request is an address 50 of the first memory space, the address 50 corresponds to an address 350 of the second memory space, the first data to be synchronized at least includes data stored in the address 350 of the second memory space.

For example, the first access request may be a write request, and the first access request may include data to be written and a first access address, which is an address where the user wants to write the data. In this case, performing the access operation corresponding to the first access request, and performing the memory synchronization operation associated with the first access request for the second memory space with respect to the first memory space may include: writing the data to be written into a position corresponding to the first access address in the first memory space; and transmitting second data to be synchronized of the first memory space to the second device so that the second device writes the second data to be synchronized into the second memory space, wherein the second data to be synchronized comprises data stored in a position corresponding to the first access address in the first memory space.

For example, by using the first function, data to be synchronized is read from the first memory space and used as second data to be synchronized, and the second data to be synchronized is sent to the second device, and after the second device receives the second data to be synchronized, the second device can update the data in the second memory space by using the second data to be synchronized. The second data to be synchronized at least includes data corresponding to the access address of the first access request, for example, the address range of the first memory space is 0-99, the address range of the second memory space is 300-399, and if the access address of the first access request is the address 50 of the first memory space, the second data to be synchronized at least includes data stored in the address 50 of the first memory space.

Fig. 4 is a flowchart illustrating an exemplary process of a memory synchronization method according to at least one embodiment of the present disclosure.

As shown in fig. 4, after the first device responds to a certain access request and triggers an access error event (S301), it may be first determined whether the access request triggering the access error event is located in the first memory space range (S302), if not, the first device may not correspond to a memory synchronization operation, for example, may exit the program, for example, notify the user that a system error occurs or jump to other system operations (e.g., functions) configured in the system for processing the access error event; if so, the first memory space may be changed to a readable and writable state (S303) and an access type of the access request is determined (S304), and if the access type is a read request, first data to be synchronized in the second memory space sent by the second device may be received (S305), the first data to be synchronized may be written into a corresponding location in the first memory space (S306), and the data stored in the first access address may be read from the first memory space (S307). If the access type is a write request, the data to be written may be written into a location in the first memory space corresponding to the first access address (S308); and transmitting the second data to be synchronized of the first memory space to the second device, so that the second device writes the second data to be synchronized into the second memory space (S309).

For example, a first memory address space allocated by a first device for a first memory space corresponds to a second memory address space allocated by a second device for a second memory space. The address range of the memory synchronization operation is a first address segment in the first memory space where the first access address is located and a second address segment in the second memory space corresponding to the first address segment. The size of the address field is, for example, a basic memory size, and may be, for example, a memory line (e.g., 32 bytes, 64 bytes, … …, 4KB, etc.). When the memory synchronization operation is performed, only the data of the first address segment where the first access address is located and the data stored in the second address segment corresponding to the first address segment in the second memory space can be synchronized without synchronizing the data of other addresses.

For example, the first device may further communicate with N devices other than the second device, where the N devices each include N predetermined memory spaces corresponding to the first memory space, and in some embodiments, the memory synchronization method further includes: memory synchronization operations associated with the first access request are performed for the N predetermined memory spaces relative to the first memory space using the first function. Wherein N is an integer greater than or equal to 1.

For example, the memory synchronization operation can be generalized to a distributed system, that is, one front end corresponds to a plurality of back ends, so as to implement the memory synchronization operation of the first device and a plurality of devices. The operation of synchronizing with the memory of the plurality of devices may refer to the operation of synchronizing with the memory of the second device, which is not described herein.

For example, in step S220, a first synchronization task may be generated based on the first access request, and the first synchronization task may be added to the task queue; the tasks in the task queue are sequentially executed, wherein when the first synchronized task is executed, an access operation corresponding to the first access request is executed, and a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space is executed.

For example, one sync task may be generated for each access request, the respective sync tasks may be arranged in a task queue according to a time sequence of generation of the sync tasks, and the sync tasks in the queue may be processed one by one according to the sequence, and a data sync operation and an access operation may be performed for each sync task.

The present disclosure also provides another memory synchronization method, for a system including a first device and a second device, for example, as shown in fig. 1, where the first device includes a first memory space, and the second device includes a second memory space corresponding to the first memory space, and the memory synchronization method includes: triggering an access error event corresponding to the first memory space in response to a first access request for the first memory space; in response to an access error event corresponding to the first memory space, a first function is invoked to perform an access operation corresponding to the first access request, and to perform a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space.

For example, the memory synchronization method for a system may further include: responding to a second access request aiming at a second memory space, and triggering an access error event corresponding to the second memory space; in response to an access error event corresponding to the second memory space, a second function is invoked to perform an access operation corresponding to the second access request, and to perform a memory synchronization operation associated with the second access request for the first memory space relative to the second memory space.

For example, the access and synchronization of the first device and the second device may be designed in a bidirectional symmetric manner, when the first memory space of the first device is accessed, the memory synchronization operations at two ends may be triggered, when the second memory space of the second device is accessed, the memory synchronization operations at two ends may be triggered, that is, a second function corresponding to the first function is also configured at one end of the second device, and when the second memory space is accessed, the memory synchronization operations and the access operations are triggered by the second function, so as to ensure that the memory read-write operation of the second device at the back end is pushed back to the first device at the front end, thereby realizing bidirectional operation, and further ensuring the data consistency at the front end and the back end.

In the system configuration method and the memory synchronization method of the embodiments of the present disclosure, by configuring the first function and the first memory space, an access error event may be triggered when the first memory space is accessed, and the first function may be further invoked. Based on the mode, the access request can be intercepted by utilizing the mechanism (access error mechanism) of the device operating system, and the first function is further called to execute the synchronous operation of the front end and the rear end, so that the application program interfaces of the memory access provided by the manufacturer are not required to be intercepted, the implementation mode and the openness of the application program interfaces provided by the manufacturer are not required to be considered, and the limitation of the mode of realizing the synchronous operation of the front end and the rear end by intercepting the application program interfaces provided by the manufacturer is overcome. The access error event such as segment error is a general mechanism of an operating system (such as a Linux system), so the method of the embodiment of the disclosure has wide applicability. And the memory synchronization operation can be realized aiming at various scenes, the memory consistency at the front end and the rear end is ensured, and the loss is reduced. In addition, the access operation can be executed while the memory synchronization operation is executed, so that the access to the first memory space can be smoothly executed.

In the system configuration method and the memory synchronization method of the embodiment of the disclosure, dynamic allocation of the system memory in the application program can be supported, instead of pre-allocating the large memory, and no additional resource consumption is generated for the application program.

In the system configuration method and the memory synchronization method of the embodiment of the disclosure, the user operating system is not invasive, the kernel, the driver and the like of the user operating system are not required to be modified, and additional permission requirements are not required.

In the system configuration method and the memory synchronization method of the embodiment of the disclosure, the consistency of the memory allocated by the application programs at the front end and the back end is ensured, the application mode of the API of the GPU heterogeneous model at the user side is not changed, and the program at the user side is not required by permission.

The present disclosure also provides, in at least one embodiment, a processing system including a first device including a first memory space and a second device in communication with the first device including a second memory space corresponding to the first memory space; wherein the first device is configured to: triggering an access error event corresponding to the first memory space in response to a first access request for the first memory space; in response to an access error event, a first function is invoked to perform an access operation corresponding to the first access request, and to perform a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space.

With respect to the system, reference may be made to the related description in the above embodiments, and the description is omitted here.

Fig. 5 illustrates a schematic block diagram of a memory synchronization apparatus 400 provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 5, the memory synchronization device 400 includes a first response unit 410 and a second response unit 420. These components are interconnected by a bus system and/or other forms of connection mechanisms (not shown). For example, these modules may be implemented by hardware (e.g., circuit) modules, software modules, or any combination of the two, and the like, and the following embodiments are the same and will not be repeated. For example, these elements may be implemented by a Central Processing Unit (CPU), an image processor (GPU), a Tensor Processor (TPU), a Field Programmable Gate Array (FPGA), or other form of processing unit having data processing and/or instruction execution capabilities, and corresponding computer instructions. It should be noted that the components and structures of memory synchronization device 400 shown in fig. 5 are exemplary only and not limiting, and memory synchronization device 400 may have other components and structures as desired.

The first response unit 410 is configured to trigger an access error event corresponding to the first memory space in response to a first access request for the first memory space. The first response unit 410 may perform, for example, step S210 described in fig. 3.

The second response unit 420 is configured to invoke a first function to perform an access operation corresponding to the first access request and to perform a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space in response to the access error event. The second response unit 420 may perform, for example, step S220 described in fig. 3.

For example, the first response unit 410 and the second response unit 420 may be hardware, software, firmware, and any feasible combination thereof. For example, the first response unit 410 and the second response unit 420 may be dedicated or general-purpose circuits, chips, devices, or the like, or may be a combination of a processor and a memory. With respect to the specific implementation forms of the respective units described above, the embodiments of the present disclosure are not limited thereto.

For example, the first response unit 410 and the second response unit 420 may include codes and programs stored in a memory; the processor may execute the code and the program to implement some or all of the functions of the first response unit 410 and the second response unit 420 as described above. For example, the first and

second response units

410 and 420 may be dedicated hardware devices for implementing some or all of the functions of the first and

second response units

410 and 420 as described above. For example, the first and

second response units

410 and 420 may be one circuit board or a combination of circuit boards for implementing the functions as described above. In an embodiment of the present disclosure, the circuit board or the combination of circuit boards may include: (1) one or more processors; (2) One or more non-transitory memories coupled to the processor; and (3) firmware stored in the memory that is executable by the processor.

It should be noted that, in the embodiment of the present disclosure, each unit of the memory synchronization device 400 corresponds to each step of the foregoing memory synchronization method, and the specific function of the memory synchronization device 400 may refer to the related description of the memory synchronization method, which is not repeated herein. The components and structures of memory synchronization device 400 shown in fig. 5 are exemplary only and not limiting, and memory synchronization device 400 may include other components and structures as desired. The memory synchronization device 400 may include more or fewer circuits or units, and the connection relationship between the circuits or units is not limited, and may be determined according to actual requirements. The specific configuration of each circuit or unit is not limited, and may be constituted by an analog device according to the circuit principle, a digital chip, or other applicable means.

At least one embodiment of the present disclosure also provides an electronic device comprising a processor and a memory storing one or more computer program modules. One or more computer program modules are configured to be executed by the processor to implement the memory synchronization method described above.

Fig. 6 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure. As shown in fig. 6, the electronic device 500 includes a processor 510 and a memory 520. Memory 520 stores non-transitory computer-readable instructions (e.g., one or more computer program modules). Processor 510 is configured to execute non-transitory computer readable instructions that, when executed by processor 510, perform one or more of the steps of the memory synchronization method described above. The memory 520 and the processor 510 may be interconnected by a bus system and/or other form of connection mechanism (not shown). The specific implementation and the related explanation of each step of the memory synchronization method can be referred to the above embodiments of the memory synchronization method, and the repetition is omitted herein.

It should be noted that the components of the electronic device 500 shown in fig. 6 are exemplary only and not limiting, and that the electronic device 500 may have other components as desired for practical applications.

For example, processor 510 and memory 520 may communicate with each other directly or indirectly.

For example, the processor 510 and the memory 520 may communicate over a network. The network may include a wireless network, a wired network, and/or any combination of wireless and wired networks. Intercommunication among processor 510 and memory 520 can also be implemented via a system bus as no limitation of the present disclosure.

For example, the processor 510 and the memory 520 may be provided at a server side (or cloud).

For example, the processor 510 may control other components in the electronic device 500 to perform desired functions. For example, processor 510 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the Central Processing Unit (CPU) may be an X86 or ARM architecture, or the like. The processor 510 may be a general purpose processor or a special purpose processor that may control other components in the electronic device 500 to perform the desired functions.

For example, memory 520 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The nonvolatile memory may include, for example, read Only Memory (ROM), hard disk, erasable Programmable Read Only Memory (EPROM), compact disc read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer readable storage medium and executed by the processor 510 to implement the various functions of the electronic device 500. Various applications and various data, as well as various data used and/or generated by the applications, etc., may also be stored in the computer readable storage medium.

For example, in some embodiments, the electronic device 500 may be a cell phone, tablet, electronic paper, television, display, notebook, digital photo frame, navigator, wearable electronic device, smart home device, or the like.

It should be noted that, in the embodiments of the present disclosure, specific functions and technical effects of the electronic device 500 may refer to the above description about the memory synchronization method, which is not repeated herein.

Fig. 7 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic device 600 is suitable for implementing, for example, the memory synchronization method and the system configuration method provided in the embodiments of the present disclosure. The electronic device 600 may be a terminal device or the like. It should be noted that the electronic device 600 shown in fig. 7 is merely an example, and does not impose any limitation on the functionality and scope of use of the embodiments of the present disclosure.

As shown in fig. 7, the electronic device 600 may include a processing means (e.g., a central processing unit, a graphics processor, etc.) 610, which may perform various suitable actions and processes according to a program stored in a Read Only Memory (ROM) 620 or a program loaded from a storage means 680 into a Random Access Memory (RAM) 630. In the RAM630, various programs and data required for the operation of the electronic device 600 are also stored. The processing device 610, ROM 620, and RAM630 are connected to each other by a bus 640. An input/output (I/O) interface 650 is also connected to bus 640.

In general, the following devices may be connected to the I/O interface 650: input devices 660 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; an output device 670 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, etc.; storage 680 including, for example, magnetic tape, hard disk, etc.; and a communication device 690. The communication device 690 may allow the electronic apparatus 600 to communicate wirelessly or by wire with other electronic apparatuses to exchange data. While fig. 7 shows the electronic device 600 with various means, it is to be understood that not all of the illustrated means are required to be implemented or provided, and that the electronic device 600 may alternatively be implemented or provided with more or fewer means.

For example, according to embodiments of the present disclosure, the memory synchronization method and the system configuration method described above may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a non-transitory computer readable medium, the computer program comprising program code for performing the memory synchronization method and the system configuration method described above. In such embodiments, the computer program may be downloaded and installed from a network via communications device 690, or from storage device 680, or from ROM 620. The functions defined in the memory synchronization method and the system configuration method provided in the embodiments of the present disclosure may be implemented when the computer program is executed by the processing device 610.

At least one embodiment of the present disclosure also provides a computer-readable storage medium storing non-transitory computer-readable instructions that, when executed by a computer, implement the memory synchronization method and the system configuration method described above.

Fig. 8 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. As shown in fig. 8, the storage medium 700 stores non-transitory computer readable instructions 710. For example, non-transitory computer readable instructions 710, when executed by a computer, perform one or more steps in accordance with the memory synchronization method and system configuration method described above.

For example, the storage medium 700 may be applied to the electronic device 500 described above. For example, the storage medium 700 may be the memory 520 in the electronic device 500 shown in fig. 6. For example, the relevant description of the storage medium 700 may refer to the corresponding description of the memory 520 in the electronic device 500 shown in fig. 6, and will not be repeated here.

The foregoing description is only of the preferred embodiments of the present disclosure and description of the principles of the technology being employed. It will be appreciated by persons skilled in the art that the scope of the disclosure referred to in this disclosure is not limited to the specific combinations of features described above, but also covers other embodiments which may be formed by any combination of features described above or equivalents thereof without departing from the spirit of the disclosure. Such as those described above, are mutually substituted with the technical features having similar functions disclosed in the present disclosure (but not limited thereto).

Moreover, although operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

For the purposes of this disclosure, the following points are also noted:

(1) The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A system configuration method for a first device, wherein the first device communicates with a second device, the system configuration method comprising:

acquiring a first memory space of the first device, wherein the first memory space corresponds to a second memory space of the second device;

a first function is configured, wherein the first function is configured to be invoked when the first memory space is accessed by a first access request to trigger an access error event, the first function comprising performing an access operation corresponding to the first access request, and comprising performing a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space.

2. The system configuration method of claim 1, further comprising:

the first memory space is configured to be in an inaccessible state to trigger the access error event when the first memory space is accessed by the first access request.

3. The system configuration method according to claim 1 or 2, wherein,

the access error event comprises a segment error event;

the first function is a callback function registered corresponding to the segment error event.

4. The system configuration method of claim 2, wherein the first function further comprises:

before executing the memory synchronization operation and the access operation, changing the first memory space from the inaccessible state to an accessible state; and

after performing the memory synchronization operation and the access operation, the first memory space is changed from the accessible state back to the inaccessible state.

5. The system configuration method of claim 1, wherein obtaining the first memory space of the first device comprises:

and recording a first memory address space allocated by the first device as the first memory space according to a program interface related to memory allocation provided by the first device.

6. The system configuration method of claim 5, further comprising:

and allocating a second memory address space corresponding to the first memory address space by the second device through negotiation of the first device and the second device, and taking the second memory address space as the second memory space.

7. A memory synchronization method for a first device, wherein the first device includes a first memory space, the first device communicates with a second device, the second device includes a second memory space corresponding to the first memory space, the memory synchronization method comprising:

triggering an access error event corresponding to the first memory space in response to a first access request for the first memory space;

in response to the access error event, a first function is invoked to perform an access operation corresponding to the first access request, and to perform a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space.

8. The memory synchronization method of claim 7, wherein,

9. The memory synchronization method according to claim 7 or 8, wherein,

the access error event comprises a segment error event;

10. The memory synchronization method of claim 8, further comprising:

11. The memory synchronization method according to claim 7 or 8, wherein the first access request is a read request, the first access request including a first access address;

performing an access operation corresponding to the first access request, and performing a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space, comprising:

receiving first data to be synchronized in the second memory space sent by the second device, wherein the first data to be synchronized comprises data stored in a position corresponding to the first access address in the second memory space;

writing the first data to be synchronized into the corresponding position of the first memory space;

and reading the data stored by the first access address from the first memory space.

12. The memory synchronization method according to claim 7 or 8, wherein the first access request is a write request, the first access request including data to be written and a first access address;

writing the data to be written into a position corresponding to the first access address in the first memory space;

and transmitting second data to be synchronized of the first memory space to the second device, so that the second device writes the second data to be synchronized into the second memory space, wherein the second data to be synchronized comprises data stored in a position corresponding to the first access address in the first memory space.

13. The memory synchronization method according to claim 7 or 8, wherein a first memory address space allocated by the first device for the first memory space corresponds to a second memory address space allocated by the second device for the second memory space;

the first access request includes a first access address;

The address range of the memory synchronization operation is a first address segment in the first memory space where the first access address is located and a second address segment in the second memory space corresponding to the first address segment.

14. The memory synchronization method according to claim 7 or 8, wherein the first device further communicates with N devices other than the second device, each of the N devices including N predetermined memory spaces corresponding to the first memory space, the memory synchronization method further comprising:

performing a memory synchronization operation associated with the first access request with respect to the N predetermined memory spaces with respect to the first memory space using the first function;

wherein N is an integer greater than or equal to 1.

15. The memory synchronization method according to claim 7 or 8, wherein,

the first device performs a computing task by using a processor of the second device, the second memory space is used for storing data to be processed and processing result data of the processor,

wherein the processor comprises a graphics processor or a general purpose graphics processor.

16. The memory synchronization method according to claim 7 or 8, wherein performing an access operation corresponding to the first access request, and performing a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space, comprises:

Generating a first synchronous task based on the first access request, and adding the first synchronous task into a task queue;

and executing tasks in the task queue in sequence, wherein when the first synchronous task is executed, an access operation corresponding to the first access request is executed, and a memory synchronous operation relative to the first memory space, which is associated with the first access request, is executed for the second memory space.

17. A memory synchronization method for a system including a first device and a second device, wherein the first device includes a first memory space, and the second device includes a second memory space corresponding to the first memory space, the memory synchronization method comprising:

in response to the access error event corresponding to the first memory space, a first function is called to perform an access operation corresponding to the first access request, and a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space is performed.

18. The memory synchronization method of claim 17, further comprising:

triggering an access error event corresponding to the second memory space in response to a second access request for the second memory space;

in response to the access error event corresponding to the second memory space, a second function is called to perform an access operation corresponding to the second access request, and a memory synchronization operation associated with the second access request for the first memory space relative to the second memory space is performed.

19. A memory synchronization apparatus for a first device, wherein the first device includes a first memory space, the first device communicates with a second device, the second device includes a second memory space corresponding to the first memory space, the memory synchronization apparatus comprising:

a first response unit configured to trigger an access error event corresponding to the first memory space in response to a first access request for the first memory space;

and a second response unit configured to respond to the access error event, call a first function to execute an access operation corresponding to the first access request, and execute a memory synchronization operation associated with the first access request for the second memory space relative to the first memory space.

20. A processing system, comprising:

the first device comprises a first memory space;

a second device, in communication with the first device, comprising a second memory space corresponding to the first memory space;

wherein the first device is configured to:

21. An electronic device, comprising:

a processor;

a memory including one or more computer program modules;

wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for implementing the system configuration method of any of claims 1-6 and/or the memory synchronization method of any of claims 7-18.

22. A computer readable storage medium storing non-transitory computer readable instructions which, when executed by a computer, implement the system configuration method of any one of claims 1-6 and/or the memory synchronization method of any one of claims 7-18.