CN116165753B - Optical chip, chip packaging structure and packaging performance detection method - Google Patents
Optical chip, chip packaging structure and packaging performance detection method Download PDFInfo
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- CN116165753B CN116165753B CN202310418377.8A CN202310418377A CN116165753B CN 116165753 B CN116165753 B CN 116165753B CN 202310418377 A CN202310418377 A CN 202310418377A CN 116165753 B CN116165753 B CN 116165753B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4256—Details of housings
- G02B6/4257—Details of housings having a supporting carrier or a mounting substrate or a mounting plate
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4274—Electrical aspects
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Abstract
The invention relates to an optical chip, a chip packaging structure and a packaging performance detection method, which comprise a conductive column, a substrate and an optical port arranged on the front surface of the substrate, wherein a through hole is formed in the substrate, the conductive column is filled in the through hole, two end parts of the conductive column are respectively positioned on the front surface and the back surface of the substrate, the end part of the conductive column on the front surface of the substrate is a detection port, and the port of the conductive column on the back surface of the substrate is a communication port. For the optical chip with larger size, the communication port can be directly bonded with the fan-out plate, so that the optical chip and the fan-out plate are electrically connected, and the optical port and the detection port are positioned on one side of the substrate, which is away from the fan-out plate, so that the optical port can be directly coupled with the optical fiber array above the substrate, the optical port cannot be blocked by the substrate, and meanwhile, the packaging of the optical port and the communication port is realized, and therefore, windowing on the fan-out plate or changing the shape of the fan-out plate is avoided.
Description
Technical Field
The present invention relates to the field of optical chip packaging, and in particular, to an optical chip, a chip packaging structure, and a packaging performance detection method.
Background
The silicon-based optical chip has the characteristics of high integration level, compatibility of the process and CMOS, and the like, and has wide application in the field of optical communication. With the development of the semiconductor chip industry and related technologies, the design and manufacture of optical chips and electrical chips are gradually advanced toward high density and large capacity, and in particular, optical switching chips, optical computing chips, system integration chips, and the like, among optical chips are expected to have a larger scale.
The optical chip has an optical port and an electrical port on its surface, and during packaging, the optical port needs to establish coupling optical communication with the optical fiber array, and the electrical port needs to establish electrical connection with a fan-out plate under the optical chip. For small-scale optical chips, the optical ports and the electrical ports are fewer in number and can be separated on the surface of the optical chip, the electrical ports are bonded with the fan-out plate by using leads, and the optical ports can be coupled with the optical fiber array by using a switching block. However, as the size of the optical chip increases, the number of optical and electrical ports increases, the optical chip can only be mounted on the fan-out plate in a flip-chip bonding manner to make electrical connection between the electrical ports and the fan-out plate, and no leads can be used, or only the leads are relied on to make electrical connection between the optical chip and the fan-out plate. However, flip-chip bonding of optical chips to electrical chips creates a problem that is different from electrical chips in that the large number of optical ports are separated from the fiber array by flip-chip bonding, making coupling of the optical ports to the fiber array difficult. It is current practice to window the fan-out plate or to change the shape of the fan-out plate so that the optical ports can be aligned with the fiber array, but this can result in limited direction of fanout traces inside the fan-out plate.
Disclosure of Invention
Based on this, it is necessary to provide an optical chip, a chip packaging structure and a packaging performance detection method for the problem that a large-sized optical chip cannot be well compatible with an optical port and an electrical port package.
The optical chip comprises a conductive column, a substrate and an optical port arranged on the front side of the substrate, wherein a through hole is formed in the substrate, the conductive column is filled in the through hole, two end parts of the conductive column are respectively positioned on the front side and the back side of the substrate, the end part of the conductive column on the front side of the substrate is a detection port, and the port of the conductive column on the back side of the substrate is a communication port.
According to the invention, the inner wall of the through hole is provided with the insulating layer, the inner wall of the insulating layer is provided with the metal adhesion layer, the inner wall of the metal adhesion layer is provided with the blocking layer, the inner wall of the blocking layer is provided with the seed layer, and the seed layer is coated on the outer wall of the conductive column.
The axis of the conductive post is perpendicular to the substrate.
The back of the substrate is provided with a rewiring layer.
The utility model provides a chip packaging structure, includes optical chip, fiber array, fan-out board and automatically controlled board, the back of base plate with the front of fan-out board is relative, so that communication port with the fan-out board electricity is connected, the back of fan-out board with the front of automatically controlled board is relative and electric connection, fiber array is located the front of base plate and with the optical port coupling.
The communication port is provided with a first conductive bump, and the first conductive bump is welded to the front surface of the fan-out plate.
The back surface of the fan-out plate is provided with a second conductive convex point, the second conductive convex point is welded to the front surface of the electric control plate, and the melting point of the second conductive convex point is lower than that of the first conductive convex point.
According to the invention, a first gap is reserved between the substrate and the fan-out plate, the first conductive protruding point is positioned in the first gap, a second gap is reserved between the fan-out plate and the electric control plate, the second conductive protruding point is positioned in the second gap, and insulating sealant is filled in both the first gap and the second gap.
A packaging performance detection method is to contact the end of a detection probe with a detection port of a chip packaging structure.
The end face of the optical fiber array is an inclined plane so as to avoid the detection probe.
Compared with the prior art, the invention adopts the mode of matching the through holes and the conductive posts, so that the front and the back of the substrate are provided with the electric ports (the detection port and the communication port), that is, the optical port can be at least positioned on the same surface of the substrate as one electric port, the electric port on the same surface with the optical port is used as the detection port, and the electric port on the different surface with the optical port is used as the communication port. For the optical chip with larger size, the communication port can be directly bonded with the fan-out plate, so that the optical chip and the fan-out plate are electrically connected, and the optical port and the detection port are positioned on one side of the substrate, which is away from the fan-out plate, so that the optical port can be directly coupled with the optical fiber array above the substrate, the optical port cannot be blocked by the substrate, and meanwhile, the packaging of the optical port and the communication port is realized, and therefore, windowing on the fan-out plate or changing the shape of the fan-out plate is avoided. Meanwhile, after the encapsulation of the two ports is finished, the detection port positioned on the front surface of the substrate provides a port for performing electrical test after the encapsulation of the optical chip is finished, and the defect that the electrical test cannot be performed after the encapsulation of the optical chip in the prior art is overcome. In addition, if the optical chip size is small, the detection port can be electrically connected with the fan-out plate in a lead mode, and meanwhile, the optical port is still located on the side away from the fan-out plate. Therefore, the optical chip provided by the invention has various packaging modes, and can especially meet the packaging requirements of the electrical port and the optical port.
Drawings
FIG. 1 is a side sectional view of a photo chip according to embodiment 1 of the present invention;
FIG. 2 is a side view of a chip package structure according to embodiment 1 of the present invention;
fig. 3 is a top view of a chip package structure according to embodiment 1 of the present invention;
FIG. 4 is a top view of a fan-out plate of embodiment 1 of the present invention;
fig. 5 is a flowchart of a method for manufacturing a chip package structure according to embodiment 1 of the present invention.
Reference numerals:
1. a substrate; 11. a through hole; 2. a conductive post; 21. a detection port; 22. a communication port; 3. an optical port; 4. an optical fiber array; 5. a fan-out plate; 51. a first welding area; 6. an electric control board; 7. a first conductive bump; 8. a second conductive bump; 9. and (5) insulating sealant.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the invention, whereby the invention is not limited to the specific embodiments disclosed below.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
It will be understood that when an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
Example 1:
referring to fig. 1, the present embodiment provides a chip package structure including an optical chip, an optical fiber array 4, a fan-out plate 5, and an electronic control plate 6. The optical chip needs to be coupled with the optical fiber array 4 to form an optical signal transmission relationship with the optical fiber array 4, meanwhile, the optical chip also needs to be electrically connected with the fan-out plate 5, and meanwhile, the fan-out plate 5 and the electric control plate 6 are electrically connected to realize electric signal transmission between the optical chip and the electric control plate 6.
Specifically, the optical chip includes a conductive post 2, a substrate 1, and an optical port 3 disposed on the front surface of the substrate 1. The substrate 1 is provided with a through hole 11, the conductive column 2 is filled in the through hole 11, and two end parts of the conductive column 2 are respectively positioned on the front surface and the back surface of the substrate 1.
It will be appreciated that the substrate 1 in this embodiment is formed by dicing a wafer prepared by conventional techniques, and the front and back sides are not symmetrical, and the front side has a silicon dioxide layer and a thinner silicon layer, while the back side is a thicker substrate layer.
In the prior art, since a silicon layer is required when the optical chip connects the electrical device and a part of the optical device, both the electrical port and the optical port 3 on the substrate 1 are disposed on the front surface of the substrate 1, so that the electrical conductivity of the electrical port is ensured by the substrate 1, and the electrical port and the optical port 3 are not disposed on the back surface of the substrate 1. Meanwhile, the optical port 3 and the electrical port in the conventional optical chip manufacturing process are arranged on the front surface of the substrate 1 conveniently. For the above reasons, there are technical prejudices and inherent knowledge to the skilled person that electrical ports cannot be nor need to be prepared on the back side of the substrate 1. Based on this situation, in the prior art, for a large-sized optical chip, the front side of the substrate 1 needs to face the fan-out plate 5, so that the electrical port on the front side of the substrate 1 can be directly electrically connected with the fan-out plate 5, at this time, the front side of the optical port 3 of the substrate 1 faces the fan-out plate 5, and at the same time, the back side of the substrate 1 faces upwards, at this time, the optical communication between the optical port 3 and the optical fiber array 4 is hindered by the substrate 1 and the fan-out plate 5, which results in that if the optical communication between the optical port 3 and the optical fiber array 4 is to be realized, the shape of the fan-out plate 5 can only be changed, or the fan-out plate 5 is windowed, so that the dodging effect between the end of the optical fiber array 4 and the optical port 3 on the fan-out plate 5 is performed, and the process of the method is complex, and the light emitted to the optical fiber array 4 by the optical port 3 may be blocked due to the fact that the dodging effect of the fan-out plate 5 is not complete. Of course, if the shape of the substrate 1 is changed or the substrate 1 is windowed to allow optical communication between the optical ports 3 and the optical fiber array 4, the structure of the substrate 1 is destroyed, and the normal operation of the optical ports 3 and the fan-out wiring inside the substrate 1 are also affected.
In the present embodiment, the through holes 11 are formed on the substrate 1 and the conductive pillars 2 are filled in the through holes 11, so that the front and back surfaces of the substrate 1 have electrical ports, that is, the two ends of the conductive pillars 2, which breaks the prejudice that the person skilled in the art cannot prepare the electrical ports on the back surface of the substrate 1. Meanwhile, the through holes 11 avoid the part of the substrate 1 at the optical port 3, so that the structure of the front surface of the substrate 1 at the optical port 3 is not damaged, the optical port 3 can still be completely arranged on the front surface of the substrate 1, and certain specific functions of the optical port can be realized by continuously depending on the structure of the front surface of the substrate 1. The conductivity of the two electrical ports at the two ends of the conductive post 2 is realized by the conductivity of the conductive post 2 itself instead of relying on the structure of the substrate 1, so the arrangement of the through holes 11 does not destroy the conductivity of the two electrical ports.
For convenience of distinction, in this embodiment, the end of the conductive post 2 on the front side of the substrate 1 is a detection port 21, and the port of the conductive post 2 on the back side of the substrate 1 is a communication port 22.
Referring to fig. 1 to 3, since the implementation manner of the electrical port in the present embodiment is completely different from that of the prior art, there is also a great difference between the packaging manner of the optical chip and that of the prior art. Specifically, the substrate 1 faces upward and the back faces downward, so that the communication port 22 is opposite to the front face of the fan-out board 5, and thus the communication port 22 can be directly electrically connected to the fan-out board 5. However, it should be noted that the optical port 3 is still located above the substrate 1, so that the optical port 3 can be directly coupled to the end of the optical fiber array 4 located above the substrate 1 to implement optical communication without being obstructed by the substrate 1, so that the optical port 3 can implement the effect of coupling with the end of the optical fiber array 4 without damaging the structural function. This breaks the technical prejudice that the backside of the substrate 1 does not need to be provided with electrical ports in the prior art.
And when base plate 1 and fan-out board 5 electricity are connected, and fan-out board 5 and automatically controlled board 6 are also connected the back, and the optical chip has just also accomplished the encapsulation, can contact detection port 21 through the probe this moment, and detection port 21 can rely on conductive column 2 self conductivity to be connected with communication port 22 electricity, and then with automatically controlled board 6 realization electric signal interaction to realize the electric signal detection to the optical chip under the encapsulation state. It can be understood that in the prior art, since the electrical port and the optical port 3 are both located on the front surface of the substrate 1 and face the fan-out board 5, once the optical chip is packaged, no redundant electrical port exists for detection, and the optical chip can perform electrical signal detection only when the optical chip is not packaged, so that whether the electrical signal transmission of the optical chip is abnormal after the packaging cannot be effectively known, and whether the packaging process is accurate and smooth cannot be judged. It can be seen that the conductive pillars 2 in this embodiment also provide a possibility of judging the effect of the optical chip package.
Based on this, the embodiment also provides a method for detecting the packaging performance, the end of the detection probe is contacted with the detection port 21 in the chip packaging structure, and the detection probe can acquire the electric signal of the electric control board 6 through the detection port 21, so that the electric signal transmission performance in the chip packaging structure can be judged. Because the part of the optical fiber array 4 above the substrate 1 is opposite to the optical port 3, the through hole 11 can avoid the optical port 3 in the process of designing and manufacturing, so that the optical fiber array 4 naturally avoids the detection port 21, which provides a moving space for the detection probe, and the detection probe can smoothly contact with the detection port 21.
Preferably, the end face of the optical fiber array 4 is an inclined plane, and the detection probe is not limited to being in contact with the detection port 21 in a manner perpendicular to the substrate 1, and the detection probe can be in contact with the detection port 21 in a manner of forming a certain included angle with the substrate 1, so that the convenience of detecting the packaging performance of the detection probe is improved. For example, if the end face of the optical fiber array 4 and the detection port 21 are relatively close, the detection probe may contact the detection port 21 as long as the detection probe does not contact the end face of the optical fiber array 4, that is, the movable range in which the detection probe can perform detection is determined by the angle between the end face of the optical fiber array 4 and the front face of the substrate 1.
The light beam emitted from the optical port 3 is perpendicular to the substrate 1, and because the end face of the optical fiber array 4 and the substrate 1 form a certain specific included angle, the light beam emitted from the optical port 3 can enter the optical fiber array 4 in a direction parallel to the substrate 1 after reaching the end face of the optical fiber array 4 by virtue of the reflection effect of the end face of the optical fiber array 4, so that the optical signal output from the optical port 3 to the optical fiber array 4 is realized. By means of reversible light path, the light rays parallel to the substrate 1 inside the optical fiber array 4 can enter the optical port 3 along the direction perpendicular to the substrate 1 under the reflection action of the end face of the optical fiber array 4, so that the optical signal output from the optical fiber array 4 to the optical port 3 is realized. Whereby optical signal transmission and coupling between the optical port 3 and the fiber array 4 is achieved. The value of the angle between the end face of the optical fiber array 4 and the substrate 1 meeting the above requirements can be calculated by a person skilled in the art according to specific material parameters.
Since the surfaces of the base plate 1, the fan-out plate 5 and the electric control plate 6 are not perfectly flat, if the base plate 1, the fan-out plate 5 and the electric control plate 6 are directly laminated in sequence, a good electrical contact relationship between the communication port 22 and the fan-out plate 5 and between the fan-out plate 5 and the electric control plate 6 cannot be ensured. Based on this, the communication ports 22 of this embodiment are provided with the first conductive bumps 7, the first conductive bumps 7 are welded to the front surface of the fan-out board 5, the first gaps are reserved between the substrate 1 and the fan-out board 5 through the first conductive bumps 7, the corresponding first conductive bumps 7 are located in the first gaps, and each communication port 22 can be electrically connected with the fan-out board 5 through the first conductive bumps 7. Similarly, the back of the fan-out plate 5 is provided with a second conductive bump 8, the second conductive bump 8 is welded to the front of the electric control plate 6, a second gap is reserved between the fan-out plate 5 and the electric control plate 6 through the second conductive bump 8, the corresponding second conductive bump 8 is located in the second gap, and each fan-out point of the fan-out plate 5 can be electrically connected with the electric control plate 6 through the second conductive bump 8.
The temperature of the first conductive bump 7 and the second conductive bump 8 in the welding process needs to be controlled, so that the situation that all the first conductive bump 7 and the second conductive bump 8 are melted and conductive surfaces are formed in the first gap and the second gap respectively due to overhigh welding temperature is avoided, and short circuit is avoided between the fan-out plate 5 and the base plate 1 and between the fan-out plate 5 and the electric control plate 6. Of course, insulating sealant 9 is filled in the first gap and the second gap, short circuits between the fan-out plate 5 and the base plate 1 and between the fan-out plate 5 and the electric control plate 6 are avoided through the insulating sealant 9, and the insulating sealant 9 is used for reinforcing connection between the fan-out plate 5 and the electric control plate 6. The insulating sealant 9 can be made of epoxy resin.
It can be thought that in the prior art, since both the electrical port and the optical port 3 are located on the front surface of the substrate 1, if the front surface of the substrate 1 faces the fan-out board 5, the electrical port and the optical port 3 are located between the substrate 1 and the fan-out board 5, that is, in the first gap, in order to expose the optical port 3, it is required to perform windowing on the fan-out board 5, and the light emitted by the optical port 3 reaches the optical fiber array 4 located on the side surface of the fan-out board 5 through the windowing position, so that the windowing position of the first gap on the fan-out board 5 is not in a sealing state, and the insulating sealant 9 cannot be filled in the first gap, that is, the connection strength between the fan-out board 5 and the substrate 1 cannot be improved by means of the insulating sealant 9. In other words, the optical chip structure of the present embodiment provides the possibility of enhancing the connection strength with the fan-out plate 5 through the insulating sealant 9.
In this embodiment, the substrate 1 is first packaged on the fan-out board 5, and then the fan-out board 5 is packaged on the electric control board 6, so that the first conductive bump 7 is welded and melted first, and the second conductive bump 8 is welded and melted second, so that in order to prevent the first conductive bump 7 from being melted in the melting process of the second conductive bump 8, the electrical connection state between the fan-out board 5 and the substrate 1 is affected, the materials of the second conductive bump 8 and the first conductive bump 7 need to be differentiated, so that the melting point of the second conductive bump 8 is lower than that of the first conductive bump 7, and the first conductive bump 7 cannot be caused to melt when the second conductive bump 8 is melted.
The substrate of the fan-out plate 5 in this embodiment is a low-temperature co-fired ceramic, and in other embodiments, the substrate may be an organic material, other ceramic materials, glass or silicon, which may be determined according to practical requirements. If the base material is ceramic material or organic material, 20-40 layers of wiring can be manufactured in a lamination mode, and the line width is hundred micrometers; if the substrate is glass or silicon, the line width of the process is smaller, the wiring density is large, and only 2-3 layers of rewiring layers are usually manufactured, if the number of the rewiring layers is increased, only the process difficulty is increased, and the yield is drastically reduced. The thermal expansion coefficient of the fan-out plate 5 is between the substrate 1 and the electric control plate 6, so that the occurrence of package failure of the chip package structure caused by mismatch of the thermal expansion coefficients of the substrate 1, the fan-out plate 5 and the electric control plate 6 is reduced.
Referring to fig. 4, the area of the fan-out plate 5 is larger than that of the substrate 1, the center of the front surface of the fan-out plate 5 is provided with a first welding area 51, the shape and size of the first welding area 51 are consistent with those of the substrate 1, the corresponding first conductive protruding points 7 are located in the first welding area 51, the substrate 1 is opposite to the first welding area 51, and the welding position of the front surface of the fan-out plate 5 is limited in the first welding area 51. The area of the electric control board 6 is larger than that of the fan-out board 5, so that the whole back surface of the fan-out board 5 is a second welding area, the second conductive protruding points 8 are distributed over the whole second welding area, and the second welding area is welded with the electric control board 6.
The fan-out plate 5 in this embodiment may be internally routed in four directions indicated by arrows in fig. 4. In contrast, if the front surface of the substrate 1 is opposite to the fan-out board 5 in the prior art, the optical port 3 is opposite to the fan-out board 5, and the window needs to be opened on the fan-out board 5 at this time, so that the fan-out direction of the internal wiring of the fan-out board 5 is limited, and the fan-out effect of the fan-out board 5 is affected, and therefore, the fan-out board 5 in the prior art can only perform fan-out wiring along the direction indicated by a partial arrow.
Referring to fig. 5, the complete preparation method of the chip package structure of this embodiment is as follows:
step a: preparing through holes 11 and conductive columns 2 on the surface of a wafer where the substrate 1 is positioned, and then dividing the wafer to form a plurality of substrates 1 with the through holes 11 and the conductive columns 2;
step b: preparing a first conductive bump 7 on the back surface of the substrate 1, welding the first conductive bump 7 to the front surface of the fan-out plate 5, and then encapsulating an insulating sealant 9;
step c: preparing a second conductive bump 8 on the back surface of the fan-out plate 5, welding the second conductive bump 8 to the electric control plate 6, and then encapsulating insulating sealant 9;
step d: the fiber array 4 is coupled to the optical port 3 and spot-glued.
The first conductive bump 7 is formed on the back surface of the substrate 1 and the second conductive bump 8 is formed on the back surface of the fan-out plate 5 by laser ball-plating, steel screen printing or electroplating.
Example 2:
the present embodiment provides an optical chip, which is different from the optical chip in embodiment 1 in the specification and size, that is, the substrate is different in size, and in embodiment 1, the optical chip is a large-size chip, and in this embodiment, the optical chip is a small-size chip, that is, the number of through holes on the substrate is smaller and is closer to the edge of the substrate, so that all the detection ports on the front surface of the substrate are closer to the edge of the substrate. In this case, the optical chip can be packaged not only by using the chip package structure of embodiment 1, but also by using a conventional chip package structure for a small-sized optical chip.
Specifically, the process of implementing the chip packaging structure by matching the optical chip of the embodiment with the prior art is as follows: the substrate is right side up, and the fan-out board is located the substrate below, and the positive detection port of substrate can pass through lead wire and fan-out board electricity and be connected this moment, and the optical port then can continue to couple at the substrate openly with the fiber array is direct. That is, the detection port can also function as the communication port at this time, so that the communication port can be used as the fan-out plate at this time.
Therefore, the packaging mode of the small-size optical chip of the embodiment is more diversified and flexible compared with the existing small-size optical chip. Meanwhile, the optical chip structure provided by combining embodiment 1 and this embodiment can be selected according to a suitable packaging mode, regardless of the size of the optical chip itself.
Example 3:
the embodiment provides a specific preparation method of a conductive post and a through hole, which specifically comprises the following steps:
step S1: etching a deep hole in the front surface of the substrate;
step S2: sequentially growing an insulating layer, a metal adhesion layer, a barrier layer and a seed layer on the inner wall of the deep hole;
step S3, electroplating copper in the middle of the seed layer so as to fill copper in the middle of the seed layer, and forming a conductive column by the copper;
step S4: and thinning the back surface of the substrate so as to convert the deep hole into a through hole.
Therefore, the structure finally formed is that the inner wall of the through hole is provided with an insulating layer, the inner wall of the insulating layer is provided with a metal adhesion layer, the inner wall of the metal adhesion layer is provided with a blocking layer, the inner wall of the blocking layer is provided with a seed layer, and the seed layer is coated on the outer wall of the conductive column.
It can be understood that, since the optical chip in embodiment 1 is mainly a large-sized chip, the number of through holes is also large, the distance between the through holes is small, the material of the insulating layer is mainly silicon nitride or silicon dioxide, and of course, other insulating materials can be used, and the insulating layer prevents the electric leakage and short circuit between the conductive posts in the adjacent through holes. The metal adhesion layer is generally made of titanium or chromium so as to prevent the conductive post and the insulating layer from being directly contacted and separated. The barrier layer prevents copper in the conductive pillars from diffusing toward the substrate and the insulating layer. The seed layer ensures that the conductive posts can be formed by electroplating later.
The axis of the conductive post of this embodiment is perpendicular to the substrate.
If the position of the conductive post meets the requirement of the relative position of the fan-out plate, the first conductive bump can be directly welded at the communication port after the step S4 is finished, and if the position of the conductive post cannot be matched with the fan-out plate, a re-wiring layer can be arranged on the back surface of the substrate after the step S4 is finished, and then the first conductive bump is welded on the back surface of the re-wiring layer.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (9)
1. The utility model provides a chip packaging structure, its characterized in that includes optical chip, fiber array, fan-out board and automatically controlled board, optical chip include conductive post, base plate and set up in the positive optical port of base plate, the through-hole has been seted up on the base plate, conductive post is filled in the through-hole, just two tip of conductive post are located respectively the front and the back of base plate, conductive post is in the positive tip of base plate is the detection port, conductive post is in the port at the base plate back is the communication port, the back of base plate with the front of fan-out board is relative, so that the communication port with fan-out board electricity is connected, the back of fan-out board with the front of automatically controlled board is relative and electric connection, fiber array is located the front of base plate and with optical port coupling.
2. The chip package structure of claim 1, wherein a first conductive bump is disposed at the communication port, the first conductive bump being soldered to a front side of the fan-out plate.
3. The chip package structure of claim 2, wherein a second conductive bump is disposed on a back surface of the fan-out board, the second conductive bump being soldered to a front surface of the electronic board, and a melting point of the second conductive bump being lower than a melting point of the first conductive bump.
4. The chip package structure of claim 3, wherein a first gap is left between the substrate and the fan-out board, the first conductive bump is located in the first gap, a second gap is left between the fan-out board and the electric control board, the second conductive bump is located in the second gap, and insulating sealant is filled in both the first gap and the second gap.
5. The chip packaging structure according to claim 1, wherein an insulating layer is provided on an inner wall of the through hole, a metal adhesion layer is provided on an inner wall of the insulating layer, a barrier layer is provided on an inner wall of the metal adhesion layer, a seed layer is provided on an inner wall of the barrier layer, and the seed layer is coated on an outer wall of the conductive column.
6. The chip package structure of claim 1, wherein the axis of the conductive post is perpendicular to the substrate.
7. The chip package structure according to claim 6, wherein a redistribution layer is provided on a back surface of the substrate.
8. A packaging performance detecting method, characterized in that an end of a detecting probe is brought into contact with the detecting port of the chip packaging structure according to claim 1.
9. The method of claim 8, wherein the end face of the optical fiber array is an inclined plane to avoid the detection probe.
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| US9941230B2 (en) * | 2015-12-30 | 2018-04-10 | International Business Machines Corporation | Electrical connecting structure between a substrate and a semiconductor chip |
| CN105575913B (en) * | 2016-02-23 | 2019-02-01 | 华天科技（昆山）电子有限公司 | It is embedded to silicon substrate fan-out-type 3D encapsulating structure |
| CN110890349A (en) * | 2019-12-20 | 2020-03-17 | 华进半导体封装先导技术研发中心有限公司 | Photoelectric chip three-dimensional packaging structure with optical interconnection interface and manufacturing method thereof |
| US11842826B2 (en) * | 2020-06-23 | 2023-12-12 | Intel Corporation | Additive manufacturing for integrated circuit assembly connector support structures |
| CN112034567B (en) * | 2020-09-04 | 2022-07-05 | 华进半导体封装先导技术研发中心有限公司 | Photoelectric chip packaging structure and packaging method thereof |
| US20220206221A1 (en) * | 2020-12-28 | 2022-06-30 | Advanced Micro Devices, Inc. | Optical die-last wafer-level fanout package with fiber attach capability |
| CN114325965B (en) * | 2021-12-28 | 2024-05-28 | 华进半导体封装先导技术研发中心有限公司 | Packaging structure of optical chip and electric chip and preparation method thereof |
| CN115657224B (en) * | 2022-10-26 | 2023-06-23 | 之江实验室 | Optical packaging method of silicon photonic chip |
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| JPS6256908A (en) * | 1985-09-03 | 1987-03-12 | アメリカン テレフオン アンド テレグラフ カムパニ− | Optical element package |
| CN101451860A (en) * | 2007-12-04 | 2009-06-10 | 松下电器产业株式会社 | Electronic part and method of producing the same |
| WO2023010574A1 (en) * | 2021-08-06 | 2023-02-09 | 华为技术有限公司 | Chip packaging structure, and packaging method therefor and electronic device therewith |
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