CN116150041A - Space allocation method, apparatus, electronic device, and computer-readable storage medium - Google Patents
Space allocation method, apparatus, electronic device, and computer-readable storage medium Download PDFInfo
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- CN116150041A CN116150041A CN202111385413.2A CN202111385413A CN116150041A CN 116150041 A CN116150041 A CN 116150041A CN 202111385413 A CN202111385413 A CN 202111385413A CN 116150041 A CN116150041 A CN 116150041A
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Abstract
The embodiment of the application relates to a space allocation method, a device, electronic equipment and a computer readable storage medium, wherein the space is used for storing data generated by a plurality of calculation layers, the calculation layers are respectively in one-to-one correspondence with a plurality of storage linked lists, and the space allocation method comprises the following steps: acquiring an allocation instruction carrying first information, wherein the first information comprises a first data size and a first calculation layer mark, and the first calculation layer mark is used for marking the calculation layer of a storage space to be allocated; distributing at least one storage block address in an idle linked list to a first target linked list according to the first data size, wherein the first target linked list is the storage linked list corresponding to the first calculation layer mark; updating the storage block address pointed by the pointer of the idle linked list.
Description
Technical Field
The present invention relates to the field of data storage technologies, and in particular, to a space allocation method, apparatus, electronic device, and computer readable storage medium.
Background
Artificial intelligence network algorithms typically comprise a plurality of computing layers, with a certain size of memory space being allocated between adjacent computing layers to buffer data between the layers. However, with the increasing amount of data to be processed by the electronic device, the existing storage space cannot fully meet the buffer requirements between different layers, and the use efficiency of the storage space is seriously insufficient, so that the operation speed of the algorithm is greatly affected.
Disclosure of Invention
The embodiment of the application provides a space allocation method, a space allocation device, electronic equipment and a computer readable storage medium, which can improve the use efficiency of a storage space.
A space allocation method, wherein the space is used for storing data generated by a plurality of computing layers, and the computing layers are respectively in one-to-one correspondence with a plurality of storage linked lists, the allocation method comprising:
acquiring an allocation instruction carrying first information, wherein the first information comprises a first data size and a first calculation layer mark, and the first calculation layer mark is used for marking the calculation layer of a storage space to be allocated;
distributing at least one storage block address in an idle linked list to a first target linked list according to the first data size, wherein the first target linked list is the storage linked list corresponding to the first calculation layer mark;
updating the storage block address pointed by the pointer of the idle linked list.
A data storage method, comprising:
acquiring calculation layer information of a target algorithm, and generating an idle linked list and a plurality of storage linked lists according to the calculation layer information, wherein the idle linked list comprises a plurality of storage blocks, and the granularity of the storage blocks corresponds to the calculation layer information;
generating an allocation instruction carrying first information in response to the data storage signal;
the storage space is distributed by adopting the space distribution method;
and storing data to be stored into the allocated storage space, wherein the data to be stored is data generated in the operation process of the target algorithm.
A space allocation apparatus for storing data generated by a plurality of computation layers, the plurality of computation layers being in one-to-one correspondence with a plurality of storage linked lists, respectively, the allocation apparatus comprising:
the instruction receiving module is used for acquiring an allocation instruction carrying first information, wherein the first information comprises a first data size and a first calculation layer mark, and the first calculation layer mark is used for marking the calculation layer of a storage space to be allocated;
the address allocation module is used for allocating at least one storage block address in the idle linked list to a first target linked list according to the first data size, wherein the first target linked list is the storage linked list corresponding to the first calculation layer mark;
and the pointer updating module is used for updating the storage block address pointed by the pointer of the idle linked list.
An electronic device, comprising:
the memory is used for storing data generated by a plurality of calculation layers, and the plurality of calculation layers are respectively in one-to-one correspondence with the plurality of storage linked lists;
the controller is used for responding to the data storage signal and generating an allocation instruction carrying first information, wherein the first information comprises a first data size and a first calculation layer mark, and the first calculation layer mark is used for marking the calculation layer needing to occupy the storage space;
the space allocation circuit is respectively connected with the controller and the memory and is used for acquiring an allocation instruction carrying first information, wherein the first information comprises a first data size and a first calculation layer mark, and the first calculation layer mark is used for marking the calculation layer of the storage space to be allocated; distributing at least one storage block address in an idle linked list to a first target linked list according to the first data size, wherein the first target linked list is the storage linked list corresponding to the first calculation layer mark; updating the storage block address pointed by the pointer of the idle linked list.
An electronic device comprising a memory and a processor, the memory having stored therein a computer program which, when executed by the processor, causes the processor to perform the steps of the space allocation method as described above.
A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of a space allocation method as described above.
According to the space allocation method, based on the first data size in the first information, the storage space can be dynamically allocated according to the data size generated by each operation, so that the utilization rate of the storage space is improved. Meanwhile, based on the first calculation layer mark in the first information, the data generated by different calculation layers can be stored respectively, so that the data of each calculation layer can be managed in batches, and the convenience of storage space management is improved. Namely, a storage space allocation method with high efficiency is provided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an internal architecture of an artificial intelligence accelerator according to an embodiment;
FIG. 2 is one of the flowcharts of the space allocation method according to one embodiment;
FIG. 3 is a schematic diagram of a linked list of a first time according to an embodiment;
FIG. 4 is a schematic diagram of a linked list of a second time according to an embodiment;
FIG. 5 is a second flowchart of a space allocation method according to an embodiment;
FIG. 6 is a third flowchart of a space allocation method according to an embodiment;
FIG. 7 is a flowchart of a method for allocating space in accordance with one embodiment;
FIG. 8 is a schematic diagram of a linked list at a third time according to an embodiment;
FIG. 9 is a schematic diagram of a linked list at a fourth time according to an embodiment;
FIG. 10 is a flow chart of a data storage method according to an embodiment;
FIG. 11 is a block diagram of an electronic device according to an embodiment;
fig. 12 is a schematic diagram of an internal structure of an electronic device according to an embodiment.
Description of element numbers:
a memory: 102, a step of; and (3) a controller: 104; space allocation circuitry: 106. An array of processing units: 108, a step of; vector operation array: 110; an accumulator: 112.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, the first information may be referred to as second information, and similarly, the second information may be referred to as first information, without departing from the scope of the present application. Both the first information and the second information are information, but they are not the same information.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise. In the description of the present application, the meaning of "several" means at least one, such as one, two, etc., unless explicitly defined otherwise.
The embodiment of the application provides a space allocation method which is used for allocating storage space so as to store data generated in the operation process of a target algorithm. Wherein the allocated memory space may be, but is not limited to, space in a static random access memory (Dynamic Random Access Memory, SRAM). A static random access memory is a memory that can always hold stored data as long as it remains powered on. That is, when the power supply is stopped, the data stored in the sram may disappear. Therefore, the static random access memory is more suitable for temporarily storing the buffered data. In the embodiment of the present application, a static random access memory is taken as an example for explanation.
In some related art, each computing layer is typically allocated a fixed and same amount of memory, i.e., may be referred to as a static allocation. Based on a static allocation mode, a buffer area with enough size is required to be arranged between every two layers so as to ensure the smooth completion of the target algorithm. It will be appreciated that if the space of the data buffer between some two computing layers is insufficient, then this computing node may become a bottleneck in the operation. For Data that cannot be stored in the buffer, the Data needs to be stored in an external Double Data Rate (DDR) memory, so that the link length for reading the Data is greatly increased, and the overall performance of the electronic device is reduced and the power consumption is increased. There are also some related techniques that allocate storage space for each computing layer separately, but the buffer corresponding to the computing layer near the rear may not be available until late, resulting in underutilization of the storage space.
FIG. 1 is a schematic diagram of an internal architecture of an artificial intelligence accelerator, which is a hardware architecture for supporting deep learning operations in an electronic device, according to an embodiment. The artificial intelligence accelerator may be, for example, a System on Chip (SoC), and an integrated circuit structure is disposed in the SoC. Referring to FIG. 1, in this embodiment, the artificial intelligence accelerator may include a memory 102, a controller 104, and a space allocation circuit 106 to store data generated by a target algorithm during operation. Among other things, structures capable of generating Data may include, for example, a Processing Element (PE) array 108 and a Vector Engine & Data Access (Vector Engine & Data Access) array 110. The processing unit array 108 is mainly used for the computation layer of the convolution class, and the vector operation array 110 is mainly used for the computation layer of the vector class. That is, different computing layers correspond to different computing resources and also to different amounts of SRAM requirements. Further, the artificial intelligence accelerator may further include an Accumulator 112 (ACC), where the Accumulator 112 is configured to accumulate different data. During operation of the artificial intelligence accelerator, the entire process is controlled in unison by the controller 104. Specifically, the controller 104 issues instructions, each instruction includes different domain segments, and each different domain segment is used to indicate different information, so as to instruct the receiving end of the instruction to execute a corresponding operation.
Fig. 2 is one of flowcharts of a space allocation method according to an embodiment, before the space allocation method according to the embodiment is executed, an idle linked list and a plurality of storage linked lists are pre-configured in a space allocation circuit, and a plurality of calculation layers are respectively in one-to-one correspondence with the plurality of storage linked lists. The linked list consists of a series of nodes (each element in the linked list is called a node) each of which includes two parts. One part is a data field storing data elements, the data stored in the data field indicating the physical memory block addresses, each memory block being available for storing data of the size 1K, 2K, 4K, etc. The other part is a pointer field storing the address of the next node. FIG. 3 is a schematic diagram of a first time of an embodiment, where the first time may be understood as a time when no computing layer occupies memory space, for example, a time when an idle linked list and each memory linked list have just been configured. In fig. 3, a free linked list is shown, and each rectangular box in the free linked list can be understood as a node. The previous node realizes the link between nodes by the pointer field storing the address of the next node, i.e. the link between different memory block addresses can be realized by the horizontal pointers in fig. 3. In addition, the vertical pointer in fig. 3 is the head pointer of the linked list, and the head pointer is used to indicate the first node in the linked list. At a first time, the diagonal fill in the free linked list shows all free memory space, and the head pointer of the free linked list points to the first free node or is used to mark the address of the first free memory block.
When the address is allocated by the space allocation method of this embodiment, and the address of the storage block pointed by the allocated head pointer is stored in the address mapping table, the data to be stored can be stored in the corresponding address by querying the address mapping table. The space allocation method of the embodiment can be used for allocating storage space for various target algorithms such as computer vision, medical image analysis, optical character recognition, natural language processing, voice recognition, handwriting recognition and biological feature recognition. Taking computer vision as an example, the plurality of computing layers may include, but are not limited to, convolution, pooling, size scaling, upsampling, and the like. Referring to fig. 2, in the present embodiment, the space allocation method includes steps 202 to 206.
The allocation instruction may include two field segments, one field segment is used to indicate a first calculation layer flag, that is, the first calculation layer flag is used to indicate the calculation layer of the storage space to be allocated, and the other field segment is used to indicate a first data size, that is, a size of the storage space required by the calculation layer of the storage space to be allocated. The space allocation circuit receives the allocation instruction, analyzes the allocation instruction, and can acquire the first information, so that the storage space is allocated according to the first information.
And 204, distributing at least one storage block address in the idle linked list to a first target linked list according to the first data size, wherein the first target linked list is the storage linked list corresponding to the first calculation layer mark.
Wherein the first data size corresponds to the number of memory blocks, i.e. the ratio between the first data size and the number of memory blocks is equal to the size of each memory block. Specifically, fig. 4 is a schematic diagram of a linked list at a second time according to an embodiment, and referring to fig. 4, in this embodiment, the first target linked list refers to a storage linked list corresponding to the calculation layer 1. If the computing layer 1 needs to allocate a storage space of 12K for data storage, and the size of each storage block is 4K, three units of storage blocks need to be allocated from the idle linked list to the computing layer 1 for data storage. That is, three memory block addresses that are blank in the free linked list are assigned to the first target linked list. Further, if multiple memory block addresses need to be allocated to the first target linked list, the adjacent multiple memory block addresses can be allocated to the first target linked list together, so that allocation difficulty is reduced. Wherein adjacent memory block addresses are understood as being linked together memory block addresses. For example, in the embodiment of fig. 4, three adjacent memory block addresses are allocated to the first target linked list corresponding to the calculation layer 1.
And step 206, updating the storage block address pointed by the pointer of the idle linked list.
Specifically, after at least one memory block address is allocated to the first target linked list, a pointer of the free linked list needs to be pointed to a new memory block address, where the new memory block address is an address of a free memory block. It will be appreciated that when updating the memory block address pointed to by the pointer, it is necessary to determine the pointer to be updated specifically based on the location of the memory block address assigned to the first target linked list by the free linked list. For example, in the embodiment of fig. 4, a plurality of memory block addresses at the head of the free linked list are allocated to the memory linked list of the computation layer 1, and then the memory block address pointed to by the head pointer of the free linked list needs to be correspondingly updated. In some possible embodiments, a plurality of memory block addresses at the tail of the free linked list may also be allocated to the memory linked list of the computation layer 1, and then the memory block address pointed to by the tail pointer of the free linked list needs to be correspondingly updated.
In this embodiment, based on the first data size in the first information, the storage space may be dynamically allocated according to the data size generated by each operation, so as to improve the utilization rate of the storage space. Meanwhile, based on the first calculation layer mark in the first information, the data generated by different calculation layers can be stored respectively, so that the data of each calculation layer can be managed in batches, and the convenience of storage space management is improved. Namely, a storage space allocation method with high efficiency is provided. In addition, it can be understood that if the processor such as the CPU is used to execute the above operation of allocating the storage space, the task being executed by the CPU needs to be frequently interrupted, thereby affecting the operation efficiency of the CPU. That is, the CPU is only suitable for performing a low-frequency, large-granularity space allocation operation, and is not effectively suitable for performing a high-frequency, small-granularity space allocation operation. Therefore, in this embodiment, the above steps are implemented by the space allocation circuit in fig. 1, and no cooperation of a processor such as a CPU is required, so that the working efficiency of the electronic device can be greatly improved.
Fig. 5 is a second flowchart of a space allocation method according to an embodiment, referring to fig. 5, in this embodiment, the space allocation method includes steps 502 to 506. Step 204 in fig. 2 includes step 504 in the present embodiment, and step 206 in fig. 2 includes step 506 in the present embodiment. Step 502 of the present embodiment is the same as step 202 in fig. 2, and will not be described here again.
And 504, linking m storage block addresses positioned at the head of the idle linked list to the tail of the first target linked list according to the storage block address pointed by the head pointer of the idle linked list, wherein m is a positive integer.
Specifically, the step of linking the memory block address to the tail of the first target linked list may include the following steps. And acquiring a tail pointer of the first target linked list to determine the last node in the first target linked list. Updating the pointer field of the last node to point to the node pointed to by the head pointer of the free linked list to link the first memory block address of the free linked list to the last memory block address of the first target linked list. Disconnecting the link relation between the mth memory block address and the (m+1) th memory block address of the head part of the idle linked list. And updating the storage block address pointed by the tail pointer of the first target linked list according to the number m of the distributed storage block addresses. By the operation of linking and updating the tail pointer of the first target linked list, other storage block addresses can be conveniently linked to the tail of the first target linked list later, and the first target linked list does not need to be traversed to determine the last node in the first target linked list.
In this embodiment, the memory block address is always allocated to the first target linked list from the head of the idle linked list, so that errors in the idle linked list can be effectively avoided. And the distributed storage block addresses are all linked to the tail part of the first target linked list, so that the generated data can be sequentially arranged, the batch moving or releasing processing is convenient, and the running efficiency of the electronic equipment is further improved.
Fig. 6 is a third flowchart of a space allocation method according to an embodiment, referring to fig. 6, in this embodiment, the space allocation method includes steps 602 to 610. Wherein the step in fig. 5 links m memory block addresses located at the head of the free linked list to the tail of the first target linked list includes steps 604 to 606 of the present embodiment. Step 602 of the present embodiment is the same as step 502 in fig. 5, and step 608 of the present embodiment is the same as step 506 in fig. 5, and will not be described here again.
Wherein the count value corresponds to the number of memory block addresses in the free linked list. It will be appreciated that if the number of memory block addresses in the free linked list is insufficient, a sufficient number of memory block addresses cannot be allocated to the first target linked list, and may even cause errors in the data stored in the linked list. Therefore, by first obtaining the count value, the number of memory block addresses that can be allocated by the idle linked list can be initially determined, and then by comparing the relationship between the number of memory block addresses required by the first computing layer and the count value in step 606, the above problem can be effectively avoided, thereby improving the reliability and accuracy of the space allocation method.
In this embodiment, after each allocation of the memory block address, the current count value is recorded by the counting module, and before each allocation of the memory block address, the current count value is queried. By the steps, invalid allocation operation can be avoided, so that the allocation speed of the space allocation method is improved, allocation errors can be prevented, and the reliability of the space allocation method is improved.
Fig. 7 is a flowchart of a method for allocating space in a memory, and referring to fig. 7, in this embodiment, the method for allocating space further includes steps 702 to 706.
The release instruction may include two field segments, one field segment is used to indicate a second computation layer flag, that is, the second computation layer flag is used to indicate the computation layer of the storage space to be released, and the other field segment is used to indicate a second data size, that is, the size of the storage space that can be released by the computation layer of the storage space to be released. The space distribution circuit receives the release instruction, analyzes the release instruction, and can acquire the second information, so that the storage space is released according to the second information.
wherein the second data size corresponds to the number of memory blocks, i.e. the ratio between the second data size and the number of memory blocks is equal to the size of each memory block. It is understood that allocation and release of storage space may be performed independently of each other, and that both the first target linked list and the second target linked list may change over time. That is, the storage linked list corresponding to a certain computing layer may be used as the first target linked list at the second time and be used as the second target linked list at the third time.
Specifically, fig. 8 is a schematic diagram of a linked list at a third time according to an embodiment, referring to fig. 8, in this embodiment, the second target linked list of the space to be released refers to a storage linked list corresponding to the calculation layer 1, and the storage linked list corresponding to the calculation layer 2 is used as the first target linked list at the current time, which needs to occupy the storage space. At this time, three units of memory block addresses in the memory linked list of the computation layer 1 may be released and linked to the tail of the free linked list. Accordingly, the memory block address pointed to by the tail pointer of the free linked list may be moved by three units. At the same time, two units of memory block addresses at the head of the free linked list are allocated to the memory linked list of the computation layer 2. Accordingly, the memory block address pointed to by the head pointer of the free linked list may be moved by two units.
Fig. 9 is a schematic diagram of a fourth link table at a fourth time according to an embodiment, referring to fig. 8, in this embodiment, the second target link table of the space to be released refers to a storage link table corresponding to the calculation layer 2, and the storage link table corresponding to the calculation layer 3 is used as the first target link table at the current time, which needs to occupy the storage space. At this point, one unit of memory block address in the compute layer 2 memory linked list may be released and linked to the tail of the free linked list. Accordingly, the memory block address pointed to by the tail pointer of the free linked list may be moved by one unit. That is, a plurality of memory block addresses allocated simultaneously may be released independently of each other, and a memory block to be released may be specifically indicated in the release instruction. At the same time, a unit of memory block address of the free linked list head is allocated to the memory linked list of the computation layer 3. Accordingly, the memory block address pointed to by the head pointer of the free linked list may be moved by one unit.
Specifically, after the second target linked list releases the storage block address, the pointer of the second target linked list needs to be pointed to a new storage block address, where the new storage block address may be the address of the last storage block in the second target linked list.
In this embodiment, by the above space allocation method, the storage space can be dynamically allocated and released in real time. Compared with a static allocation mode, the dynamic allocation and release mode can wait for the space allocation to be performed when the computing layer really needs to use the storage space, so that the storage space can be utilized efficiently and accurately, and the system is more flexible and efficient. Moreover, the method is more suitable for the artificial intelligent network algorithm with high-frequency calculation layer address allocation requirements.
With continued reference to fig. 7, in one embodiment, the space allocation method further includes steps 708 through 710.
and 710, suspending allocation of the storage space when the count value is smaller than m, and recovering allocation of the storage space when the count value is increased to be larger than a preset space threshold value, wherein the preset space threshold value is larger than the data quantity generated by one operation of any calculation layer.
When the idle linked list and the storage linked list are configured in an initialized mode, a preset space threshold can be generated synchronously, and accordingly the corresponding preset space threshold is set according to a target algorithm, and therefore accuracy of adjustment is improved. In this embodiment, when the count value does not meet the requirement, the allocation of the storage space is suspended, so that the pressure during the storage of a large amount of data can be effectively avoided, and the reliability of the space allocation and the storage process is improved.
In one embodiment, the first information further includes an allocation flag, the second information further includes a release flag, and the allocation flag and the release flag occupy a same flag bit in the instruction. That is, the instruction receiving module only needs to configure one interface to receive the operations of the allocation instruction and the release instruction. Specifically, after receiving the instruction, the instruction receiving module analyzes the instruction, and can acquire the data on the flag bit, so as to determine whether the received instruction is an allocation instruction or a release instruction. For example, if the data on the flag bit is 0, the received instruction is an allocation instruction; if the data on the flag bit is 1, the received instruction is a release instruction. By the arrangement mode of the embodiment, the number of interfaces required to be configured by the space distribution circuit can be reduced, and the integration level of the circuit can be improved.
Fig. 10 is a flowchart of a data storage method according to an embodiment, referring to fig. 10, in this embodiment, the data storage method includes steps 1002 to 1012.
In particular, the target algorithm may be, but is not limited to, computer vision, medical image analysis, optical word recognition, natural language processing, speech recognition, handwriting recognition, and biometric recognition. The calculation layer information is used to describe a calculation layer included in the target algorithm, and taking the target algorithm as a computer vision as an example, the calculation layer information may include a convolution calculation layer, a pooling calculation layer, a size scaling calculation layer, an up-sampling calculation layer, and the like. The number of storage linked lists to be created, such as four storage linked lists, can be determined by acquiring the calculation layer information, and the granularity of the storage blocks can be determined, for example, in computer vision, if the minimum data which can be generated in the calculation process is 4K, the granularity of the storage blocks can be set to be 4K, so that accurate division of the storage blocks is realized, and the waste of storage space is avoided.
In step 1004, an allocation instruction carrying the first information is generated in response to the data storage signal. The data storage signal may be an external signal, and is used to instruct the controller 104 to generate an allocation command.
And step 1008, allocating at least one storage block address in the idle linked list to a first target linked list according to the first data size, wherein the first target linked list is the storage linked list corresponding to the first calculation layer mark.
And step 1010, updating the storage block address pointed by the pointer of the idle linked list.
In this embodiment, based on the foregoing space allocation method, high-speed and efficient storage of data may be implemented, so that operation efficiency of the electronic device may be greatly improved.
It should be understood that, although the steps in the flowcharts are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, and the order of execution of the sub-steps or stages is not necessarily sequential, but may be performed in rotation or alternately with at least a portion of the sub-steps or stages of other steps or other steps.
Fig. 11 is a block diagram of an electronic device according to an embodiment, and referring to fig. 11, the electronic device includes a memory 102, a controller 104, and a space allocation circuit 106 in this embodiment.
The memory 102 is configured to store data generated by a plurality of computing layers, where the computing layers are respectively in one-to-one correspondence with a plurality of storage linked lists. The controller 104 is configured to generate, in response to the data storage signal, an allocation instruction carrying first information, where the first information includes a first data size and a first computation layer flag, where the first computation layer flag is used to indicate the computation layer that needs to occupy a storage space. The space allocation circuit 106 is respectively connected to the controller 104 and the memory 102, and is configured to obtain an allocation instruction carrying first information, where the first information includes a first data size and a first calculation layer flag, and the first calculation layer flag is used to indicate the calculation layer of the storage space to be allocated; distributing at least one storage block address in an idle linked list to a first target linked list according to the first data size, wherein the first target linked list is the storage linked list corresponding to the first calculation layer mark; updating the storage block address pointed by the pointer of the idle linked list.
Specifically, the controller 104 issues an instruction, where the instruction format includes a calculation layer flag, whether space needs to be allocated or released, and a data size. When memory needs to be allocated, the free memory count module in the memory allocation circuit 106 may count whether there is currently free memory available for allocation and feed this information back to the controller 104.
The space allocation circuit 106 includes an instruction receiving module, an address allocation module, and a pointer updating module. The instruction receiving module is used for receiving and analyzing an allocation instruction carrying first information and a release instruction carrying second information. The address allocation module is used for allocating at least one storage block address in the idle linked list to a first target linked list according to the first data size, wherein the first target linked list is the storage linked list corresponding to the first calculation layer mark. The pointer updating module is used for updating the storage block address pointed by the pointer of the idle linked list, recording the positions of the chain table head and the chain table tail of each idle linked list and updating the storage block address pointed by the pointer of the chain table head or the pointer of the chain table tail according to the executed operation. The instruction receiving module may be implemented by a decoder, and the address allocating module and the pointer updating module may be implemented by a shift register, for example. With continued reference to FIG. 11, in one embodiment, the space allocation circuit 106 further includes a free memory count module for recording count values. The free memory count module may be implemented by an adder and a subtractor, for example. It should be understood that the foregoing implementation manner is merely illustrative, and is not intended to limit the scope of the present embodiment, and other hardware capable of implementing the foregoing operation is also included in the scope of the present application.
The space distribution circuit 106 may also be referred to as a space distribution device, where the division of the individual modules is for illustration only, and in other embodiments, the space distribution device may be divided into different modules as needed to perform all or part of the functions of the space distribution device. For specific limitations of the space allocation device, reference may be made to the above limitation of the space allocation method, and no further description is given here. The respective modules in the above-described space allocation apparatus may be all realized by hardware. The above modules may be embedded in hardware or may be independent of a processor in the computer device, so as to perform operations corresponding to the above modules.
Fig. 12 is a schematic diagram showing an internal structure of an electronic device according to an embodiment, and referring to fig. 12, the electronic device includes a processor and a memory connected through a system bus. Wherein the processor is configured to provide computing and control capabilities to support operation of the entire electronic device. The memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The computer program is executable by a processor for implementing a space allocation method provided by the following embodiments. The internal memory provides a cached operating environment for operating system computer programs in the non-volatile storage medium. The electronic device may be any terminal device such as a mobile phone, a tablet computer, a PDA (Personal Digital Assistant ), a POS (Point of Sales), a car-mounted computer, and a wearable device.
An electronic device comprising a memory and a processor, the memory having stored therein a computer program which, when executed by the processor, causes the processor to perform the steps of the space allocation method as described above.
The implementation of each module in the space allocation apparatus provided in the embodiments of the present application may be in the form of a computer program. The computer program may run on a terminal or a server. Program modules of the computer program may be stored in the memory of the electronic device. Which when executed by a processor, performs the steps of the methods described in the embodiments of the present application.
Embodiments of the present application also provide a computer-readable storage medium. One or more non-transitory computer-readable storage media containing computer-executable instructions that, when executed by one or more processors, cause the processors to perform the steps of a space allocation method.
A computer program product containing instructions that, when run on a computer, cause the computer to perform a space allocation method.
Any reference to memory, storage, database, or other medium used herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (11)
1. The space allocation method is characterized in that the space is used for storing data generated by a plurality of calculation layers, the plurality of calculation layers are respectively in one-to-one correspondence with a plurality of storage linked lists, and the allocation method comprises the following steps:
acquiring an allocation instruction carrying first information, wherein the first information comprises a first data size and a first calculation layer mark, and the first calculation layer mark is used for marking the calculation layer of a storage space to be allocated;
distributing at least one storage block address in an idle linked list to a first target linked list according to the first data size, wherein the first target linked list is the storage linked list corresponding to the first calculation layer mark;
updating the storage block address pointed by the pointer of the idle linked list.
2. The allocation method according to claim 1, wherein said allocating at least one memory block address in a free linked list to a first target linked list according to said first data size comprises:
according to the storage block address pointed by the head pointer of the idle linked list, linking m storage block addresses positioned at the head of the idle linked list to the tail of the first target linked list, wherein m is a positive integer;
the updating the storage block address pointed by the pointer of the idle linked list comprises the following steps:
and updating the memory block address pointed by the head pointer of the idle linked list according to the number m of the allocated memory block addresses.
3. The allocation method according to claim 2, further comprising:
when the storage space is distributed to the first target linked list, reducing the count value of the free storage space, wherein the count value corresponds to the number of storage block addresses in the free linked list;
the linking the m storage block addresses located at the head of the idle linked list to the tail of the first target linked list includes:
acquiring the count value;
and when the count value is greater than m, linking m storage block addresses at the head part of the idle linked list to the tail part of the first target linked list.
4. A method of dispensing as claimed in claim 3, further comprising:
acquiring a release instruction carrying second information, wherein the second information comprises a second data size and a second calculation layer mark, and the second calculation layer mark is used for marking the calculation layer of the storage space to be released;
distributing at least one storage block address in a second target linked list to the idle linked list according to the second data size, wherein the second target linked list is the storage linked list corresponding to the second calculation layer mark;
and updating the storage block address pointed by the pointer of the second target linked list.
5. The allocation method according to claim 4, further comprising:
after the memory space is released to the idle linked list, the count value is increased;
and when the count value is smaller than m, suspending to allocate the storage space, and when the count value is increased to be larger than a preset space threshold value, recovering to allocate the storage space, wherein the preset space threshold value is larger than the data quantity generated by one operation of any calculation layer.
6. The allocation method according to claim 4, wherein said first information further comprises an allocation flag, said second information further comprises a release flag, said allocation flag and said release flag occupy a same flag bit in an instruction.
7. A method of data storage, comprising:
acquiring calculation layer information of a target algorithm, and generating an idle linked list and a plurality of storage linked lists according to the calculation layer information, wherein the idle linked list comprises a plurality of storage blocks, and the granularity of the storage blocks corresponds to the calculation layer information;
generating an allocation instruction carrying first information in response to the data storage signal;
allocating storage space using the space allocation method according to any one of claims 1 to 6;
and storing data to be stored into the allocated storage space, wherein the data to be stored is data generated in the operation process of the target algorithm.
8. A space allocation apparatus, wherein the space is used for storing data generated by a plurality of computation layers, and a plurality of computation layers are respectively in one-to-one correspondence with a plurality of storage linked lists, the allocation apparatus comprising:
the instruction receiving module is used for acquiring an allocation instruction carrying first information, wherein the first information comprises a first data size and a first calculation layer mark, and the first calculation layer mark is used for marking the calculation layer of a storage space to be allocated;
the address allocation module is used for allocating at least one storage block address in the idle linked list to a first target linked list according to the first data size, wherein the first target linked list is the storage linked list corresponding to the first calculation layer mark;
and the pointer updating module is used for updating the storage block address pointed by the pointer of the idle linked list.
9. An electronic device, comprising:
the memory is used for storing data generated by a plurality of calculation layers, and the plurality of calculation layers are respectively in one-to-one correspondence with the plurality of storage linked lists;
the controller is used for responding to the data storage signal and generating an allocation instruction carrying first information, wherein the first information comprises a first data size and a first calculation layer mark, and the first calculation layer mark is used for marking the calculation layer needing to occupy the storage space;
the space allocation circuit is respectively connected with the controller and the memory and is used for acquiring an allocation instruction carrying first information, wherein the first information comprises a first data size and a first calculation layer mark, and the first calculation layer mark is used for marking the calculation layer of the storage space to be allocated; distributing at least one storage block address in an idle linked list to a first target linked list according to the first data size, wherein the first target linked list is the storage linked list corresponding to the first calculation layer mark; updating the storage block address pointed by the pointer of the idle linked list.
10. An electronic device comprising a memory and a processor, the memory having stored therein a computer program which, when executed by the processor, causes the processor to perform the steps of the space allocation method according to any one of claims 1 to 7.
11. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the space allocation method according to any one of claims 1 to 7.
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| CN116719485A (en) * | 2023-08-09 | 2023-09-08 | 苏州浪潮智能科技有限公司 | FPGA-based data reading and writing method, reading and writing unit and FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116719485A (en) * | 2023-08-09 | 2023-09-08 | 苏州浪潮智能科技有限公司 | FPGA-based data reading and writing method, reading and writing unit and FPGA |
| CN116719485B (en) * | 2023-08-09 | 2023-11-03 | 苏州浪潮智能科技有限公司 | FPGA-based data reading and writing method, reading and writing unit and FPGA |
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