CN116131858A - Current rudder digital-to-analog conversion circuit, chip and electronic equipment - Google Patents
Current rudder digital-to-analog conversion circuit, chip and electronic equipment Download PDFInfo
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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Abstract
The embodiment of the disclosure provides a current steering digital-to-analog conversion circuit, a chip and an electronic device, wherein the current steering digital-to-analog conversion circuit comprises: a DAC main circuit configured to convert an input digital signal into a control signal of a unit current source output switch group, and generate an output current according to the control signal, the output current driving a load resistor, outputting a voltage analog signal, a plurality of unit current sources being implemented by a current mirror circuit; a current mirror input control circuit configured to control a voltage of a reference current input in the current mirror circuit to be equal to an input reference voltage through a first operational amplifier; and the common-mode voltage control circuit is configured to control the common-mode voltage of the first output end voltage and the second output end voltage obtained after the output of the plurality of unit current sources is controlled by the unit current source output switch group through the second operational amplifier to be equal to the input reference voltage. The problem of low linearity between output voltage and input digital quantity of the existing current rudder digital-to-analog converter is solved.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of integrated circuits, in particular to a current steering digital-to-analog conversion circuit, a chip and electronic equipment.
Background
With the development of digital technology and digital computers, the conversion of digital signals into analog signals has become an important part of modern integrated circuit designs. Digital-to-analog converter (Digita)l to analog converter, DAC) is implemented in a variety of ways, one of which is commonly used as a current steering DAC. An exemplary circuit diagram of a conventional current steering DAC (100) is shown in fig. 1. The digital DATA input from the DAC is converted into a control signal of the current output switch 110 by the digital decoder, and the current output switch 110 is connected to an output of a unit current source, which is implemented by the current mirror circuit 120. Different DAC output currents can be obtained by different control signals, the output currents directly drive the load resistor RL, and the digital-to-analog conversion result of the DAC is output by Voutp and Voutn, wherein Voutp=VDD-DATA x I LSB *RL，Voutn＝VDD-(2 n -DATA)*I LSB * RL, wherein VDD is the supply voltage, n is the number of bits of the DAC, I LSB Is the unit current. In practical applications, the inventors have found that since the current mirror circuit 120 is implemented by a MOS transistor, the output impedance of the current mirror circuit 120 is limited, not infinite to an ideal state, which results in the output current of the unit current source varying with the voltage at the output terminal, i.e. when Voutp and Voutn vary, I LSB Will also change with it, i.e LSB Cannot be kept stable, resulting in a reduced linearity between the output voltage of the current steering DAC and the input digital quantity DATA.
Disclosure of Invention
The embodiments described herein provide a current steering digital-to-analog conversion circuit, a chip and an electronic device, which are used for solving the problem of low linearity between the output voltage and the input digital quantity of a current steering DAC in the existing current steering digital-to-analog converter.
According to a first aspect of the present disclosure, there is provided a current steering digital to analog conversion circuit comprising: the device comprises a DAC main circuit, a current mirror input end control circuit and a common mode voltage control circuit, wherein the DAC main circuit is configured to convert an input digital signal into a control signal of a unit current source output switch group, and generate output current according to the control signal, the output current drives a load resistor and outputs a voltage analog signal, the unit current source output switch group is a switch group connected with the outputs of a plurality of unit current sources, and the plurality of unit current sources are realized by the current mirror circuit; the current mirror input end control circuit is configured to control the voltage of a reference current input end in the current mirror circuit to be equal to an input reference voltage through a first operational amplifier; the common mode voltage control circuit is configured to control the common mode voltage of the first output end voltage and the second output end voltage to be equal to the input reference voltage through the second operational amplifier, wherein the first output end voltage and the second output end voltage are output end voltages of two outputs obtained after the output of the plurality of unit current sources is controlled by the unit current source output switch group.
Optionally, the current mirror input control circuit includes: the first operational amplifier is characterized in that an inverting input end of the first operational amplifier is coupled with the input reference voltage, a non-inverting input end of the first operational amplifier is coupled with an input end of a reference current in the current mirror circuit, and an output end of the first operational amplifier is coupled with a control electrode of an input stage transistor which receives the reference current in the current mirror circuit.
Optionally, the common mode voltage control circuit includes: a first common-mode detection circuit, a second common-mode detection circuit, the second operational amplifier, and a common-mode compensation circuit, wherein the first common-mode detection circuit is configured to detect a common-mode voltage of the first output terminal voltage and the second output terminal voltage, and input the common-mode voltage to a non-inverting input terminal of the second operational amplifier; the second common mode detection circuit is configured to convert the input reference voltage into a reference common mode voltage and input the reference common mode voltage to an inverting input terminal of the second operational amplifier; the common mode compensation circuit is coupled to the output terminal of the second operational amplifier and configured to adjust a common mode voltage of the first output terminal voltage and the second output terminal voltage according to an output result of the second operational amplifier.
Optionally, the first common mode detection circuit includes: the first current source, the first transistor and the second transistor, wherein one end of the first current source is coupled with the grounding end, and the other end of the first current source is respectively coupled with the first pole of the first transistor, the first pole of the second transistor and the non-inverting input end of the second operational amplifier; the second pole of the first transistor and the second pole of the second transistor are coupled with a power supply voltage, the control pole of the first transistor is coupled with the first output terminal voltage, and the control pole of the second transistor is coupled with the second output terminal voltage; the second common mode detection circuit includes: the second current source, the third transistor and the fourth transistor, wherein one end of the second current source is coupled with the ground end, and the other end of the second current source is respectively coupled with the first pole of the third transistor, the first pole of the fourth transistor and the inverting input end of the second operational amplifier; the second pole of the third transistor and the second pole of the fourth transistor are coupled to a power supply voltage, and the control pole of the third transistor and the control pole of the fourth transistor are coupled to the input reference voltage.
Optionally, the common mode compensation circuit includes: a fifth transistor, a sixth transistor, a first resistor and a second resistor, wherein the control electrode of the fifth transistor and the control electrode of the sixth transistor are coupled to the output end of the second operational amplifier, the first electrode of the fifth transistor and the first electrode of the sixth transistor are coupled to a power supply voltage, the second electrode of the fifth transistor is respectively coupled to one end of the first resistor and the first output end voltage, and the second electrode of the sixth transistor is respectively coupled to one end of the second resistor and the second output end voltage; the other end of the first resistor and the other end of the second resistor are coupled with a grounding end.
Optionally, the DAC main circuit includes: the current mirror circuit, the unit current source output switch group, the current conversion voltage circuit and the digital decoder, wherein the current mirror circuit is configured to mirror out a plurality of unit current sources according to a mirror proportion by utilizing the reference current; the first end of each switch in the unit current source output switch group is respectively coupled with the output end of one unit current source, the second end of each switch is respectively coupled with the voltage of the first output end, the third end of each switch is respectively coupled with the voltage of the second output end, the number of the switches in the unit current source output switch group is equal to the number of the unit current sources, and the unit current source output switch group receives the control signal; the digital decoder is configured to receive the input digital signal and convert the input digital signal into the control signal; the current conversion voltage circuit is coupled to the first output terminal voltage and the second output terminal voltage respectively and is configured to convert the output current into the output voltage analog signal.
Optionally, the current mirror circuit includes: the reference current source is used for inputting the reference current to the input stage transistor, one end of the reference current source is coupled with a power supply voltage, the other end of the reference current source is the reference current input end and is coupled with a second pole of the input stage transistor; a first pole of the input stage transistor is coupled with a grounding end; the first pole of each output stage transistor is coupled to the ground terminal, the second pole of each output stage transistor is coupled to the first terminal of a corresponding one of the unit current source output switch groups, and the control pole of each output stage transistor is coupled to the control pole of the input stage transistor.
Optionally, the current conversion voltage circuit includes: the voltage analog signal generating circuit comprises a third operational amplifier, a first load resistor and a second load resistor, wherein the non-inverting input end of the third operational amplifier is respectively coupled with the voltage of the first output end, one end of the first load resistor is coupled with the voltage of the second output end, one end of the second load resistor is coupled with the inverting output end of the third operational amplifier, the non-inverting output end of the third operational amplifier is respectively coupled with the other end of the first load resistor and the first output voltage in the voltage analog signal, and the non-inverting output end of the third operational amplifier is respectively coupled with the other end of the second load resistor and the second output voltage in the voltage analog signal.
According to a second aspect of the present disclosure, there is provided a chip comprising a current steering digital to analog conversion circuit according to any one of the first aspects.
According to a third aspect of the present disclosure, there is provided an electronic device comprising the chip of the second aspect.
The current steering digital-to-analog conversion circuit, the chip and the current steering digital-to-analog conversion circuit in the electronic equipment of the embodiment of the disclosure comprise: the DAC main circuit is configured to convert an input digital signal into a control signal of a unit current source output switch group, and generate output current according to the control signal, the output current drives a load resistor and outputs a voltage analog signal, the unit current source output switch group is a switch group connected with the outputs of a plurality of unit current sources, and the plurality of unit current sources are realized by the current mirror circuit; a current mirror input control circuit configured to control a voltage of a reference current input in the current mirror circuit to be equal to an input reference voltage through a first operational amplifier; and the common-mode voltage control circuit is configured to control the common-mode voltage of the first output end voltage and the second output end voltage to be equal to the input reference voltage through the second operational amplifier, wherein the first output end voltage and the second output end voltage are two output end voltages obtained after the output of the plurality of unit current sources is controlled by the unit current source output switch group. It can be seen that, in the current steering digital-to-analog conversion circuit in the embodiment of the present application, the voltage of the reference current input end in the current mirror circuit is controlled to be equal to the input reference voltage through the first operational amplifier, and the common mode voltage of the output end voltages of the two outputs obtained after the outputs of the plurality of unit current sources are controlled by the unit current source output switch group is also controlled to be equal to the input reference voltage through the second operational amplifier. In this way, when the circuit stably works, the voltages of the two output ends corresponding to the plurality of unit current sources can be kept stable to be the input reference voltage, so that the output current of the unit current sources can also be kept stable, and the problem of linearity reduction between the output voltage and the input digital quantity DATA is effectively solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:
FIG. 1 is an exemplary circuit diagram of a prior art current steering DAC;
FIG. 2 is a schematic block diagram of a current steering digital-to-analog conversion circuit of an embodiment of the present disclosure
Fig. 3 is an exemplary circuit diagram of a current steering digital to analog conversion circuit of an embodiment of the present disclosure;
FIG. 4 is an exemplary circuit diagram of a common mode voltage control circuit of an embodiment of the present disclosure;
FIG. 5 is a schematic diagram showing the comparison of the differential nonlinear DNL simulation results corresponding to the circuit diagrams in FIGS. 1 and 3;
elements in the figures are illustrated schematically and not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.
In all embodiments of the present disclosure, since the source and drain of a Metal Oxide Semiconductor (MOS) transistor are symmetrical and the on-current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control pole and the remaining two terminals of the MOS transistor are referred to as the first pole and the second pole, respectively. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).
In order to solve the problem of low linearity between output voltage and input digital quantity of the existing current steering digital-to-analog converter, a novel current steering digital-to-analog converter circuit structure is provided. The current steering digital-to-analog conversion circuit of the embodiment of the disclosure is mainly based on the original current steering DAC circuit structure, a control circuit for controlling the constant voltage of a reference current input end in the current mirror circuit is added for the current mirror circuit of a unit current source, and a control circuit for controlling the output end voltages (a first output end voltage and a second output end voltage) of two outputs obtained after the output of a plurality of unit current sources is controlled by a unit current source output switch group is added, so that the output current of the unit current source is kept stable, and the problem of linearity reduction between the output voltage and an input digital quantity DATA in the existing current steering DAC circuit is effectively solved. The current steering digital-to-analog conversion circuit of the present disclosure is described in detail below.
As shown in fig. 2, a schematic block diagram of a current steering digital-to-analog conversion circuit 200 according to an embodiment of the present disclosure includes: DAC main circuit 210, current mirror input control circuit 220, and common mode voltage control circuit 230.
The DAC main circuit 210 is coupled to the current mirror input control circuit 220 and the common mode voltage control circuit 230, respectively, and the DAC main circuit 210 is configured to convert an input digital signal DATA into a control signal of a unit current source output switch set, and generate an output current according to the control signal, and output the output current to drive the load resistor, and output a voltage analog signal, wherein the unit current source output switch set is a switch set connected to the outputs of a plurality of unit current sources, and the plurality of unit current sources are implemented by the current mirror circuit. The output of each unit current source is connected with a switch, the opening and closing of the switches in the switch group are determined by control signals, and different control signals are combined by different switches. The conversion of the input digital signal DATA into a control signal of the unit current source output switch group is realized by a digital decoder. The voltage analog signals output in the embodiments of the present application are a set of voltage signals (Voutp, voutn).
The current mirror input control circuit 220 is coupled to the current mirror circuit in the DAC main circuit 210 and is configured to control the voltage of the reference current input in the current mirror circuit to be equal to the input reference voltage VCM through the first operational amplifier. The current mirror input terminal control circuit 220 mainly applies the negative feedback principle of an operational amplifier, that is, the principle that the voltages at the input terminals of the operational amplifier are equal under the stable operation of the circuit, and the input reference voltage VCM and the reference current input terminal are respectively connected with the two input terminals of the operational amplifier, so that the voltage at the reference current input terminal is equal to the input reference voltage VCM during the stable operation of the circuit, and the input reference voltage VCM is a constant voltage, so that the voltage at the reference current input terminal can be stabilized to a constant value (input reference voltage VCM) through the current mirror input terminal control circuit 220.
The common-mode voltage control circuit 230 is coupled to the DAC main circuit 210 and configured to control, through the second operational amplifier, that the common-mode voltage of the first output voltage Vp and the second output voltage Vn is equal to the input reference voltage VCM, where the first output voltage Vp and the second output voltage Vn are output voltages of two outputs obtained after the outputs of the plurality of unit current sources are controlled by the unit current source output switch set. The common-mode voltage control circuit 230 is for controlling the common-mode voltage of the first output voltage Vp and the second output voltage Vn to be stable. The specific common-mode voltage control circuit 230 also applies the negative feedback principle of the operational amplifier, that is, the principle that the voltages at the input ends of the operational amplifier are equal in the stable operation of the circuit, and connects the common-mode voltage of the first output end voltage Vp and the second output end voltage Vn and the reference common-mode voltages corresponding to the two input reference voltages VCM to the two input ends of the operational amplifier respectively, so that the common-mode voltage of the first output end voltage Vp and the second output end voltage Vn is equal to the reference common-mode voltage in the stable operation of the circuit.
Further, as shown in fig. 3, an exemplary circuit diagram of a current steering digital-to-analog conversion circuit 200 is provided by an embodiment of the present disclosure. In fig. 3, the current mirror input control circuit 220 includes: the inverting input terminal of the first operational amplifier 221 is coupled to the input reference voltage VCM, the non-inverting input terminal of the first operational amplifier 221 is coupled to the input terminal Vr of the reference current in the current mirror circuit 211, and the output terminal of the first operational amplifier 221 is coupled to the control electrode of the input stage transistor Mn0 of the current mirror circuit 211 that receives the reference current Iref. The output terminal of the input stage transistor Mn0 of the current mirror circuit 211 is coupled to receive the reference current Iref in order to make the current flowing through the input stage transistor Mn0 equal to the reference current Iref.
As shown in fig. 3, the common mode voltage control circuit 230 includes: a first common mode detection circuit 231, a second common mode detection circuit 232, a second operational amplifier 233, and a common mode compensation circuit 234, wherein the first common mode detection circuit 231 is configured to detect a common mode voltage vcm_in of the first output terminal voltage Vp and the second output terminal voltage Vn, and input the common mode voltage vcm_in to a non-inverting input terminal of the second operational amplifier 233; a second common mode detection circuit 232 configured to convert the input reference voltage VCM into a reference common mode voltage vcm_ref and input the reference common mode voltage vcm_ref to an inverting input terminal of the second operational amplifier 233; the common mode compensation circuit 234 is coupled to the output terminal of the second operational amplifier 233, and is configured to adjust the common mode voltage vcm_in between the first output terminal voltage Vp and the second output terminal voltage Vn according to the output result of the second operational amplifier 233, so that vcm_in is equal to vcm_ref.
Further, as shown in fig. 4, the first common mode detection circuit 231 includes: the first current source 2311, the first transistor Mn1 and the second transistor Mn2, wherein one end of the first current source 2311 is coupled to the ground, and the other end of the first current source 2311 is coupled to the first pole of the first transistor Mn1, the first pole of the second transistor Mn2 and the non-inverting input end of the second operational amplifier 233, respectively; the second pole of the first transistor Mn1 and the second pole of the second transistor Mn2 are coupled to the power voltage VDD, the control pole of the first transistor Mn1 is coupled to the first output voltage Vp, and the control pole of the second transistor Mn2 is coupled to the second output voltage Vn; the second common mode detection circuit 232 includes: the second current source 2321, the third transistor Mn3 and the fourth transistor Mn4, wherein one end of the second current source 2321 is coupled to the ground, and the other end of the second current source 2321 is respectively coupled to the first pole of the third transistor Mn3, the first pole of the fourth transistor Mn4 and the inverting input end of the second operational amplifier 233; the second pole of the third transistor Mn3 and the second pole of the fourth transistor Mn4 are coupled to the power voltage VDD, and the control pole of the third transistor Mn3 and the control pole of the fourth transistor Mn4 are coupled to the input reference voltage VCM. The first transistor Mn1, the second transistor Mn2, the third transistor Mn3, and the fourth transistor Mn4 are N-type transistors, for example, N-type MOS transistors. The current values of the first current source 2311 and the second current source 2321 are equal.
As shown in fig. 4, the common mode compensation circuit 234 includes: the control electrode of the fifth transistor Mp5 and the control electrode of the sixth transistor Mp6 are coupled to the output end of the second operational amplifier 233, the first electrode of the fifth transistor Mp5 and the first electrode of the sixth transistor Mp6 are coupled to the power supply voltage VDD, the second electrode of the fifth transistor Mp5 is respectively coupled to one end of the first resistor R1 and the first output end voltage Vp, and the second electrode of the sixth transistor Mp6 is respectively coupled to one end of the second resistor R2 and the second output end voltage Vn; the other end of the first resistor R1 and the other end of the second resistor R2 are coupled to the ground. The fifth transistor Mp5 and the sixth transistor Mp6 are P-type transistors, for example, P-type MOS transistors. The resistance values of the first resistor R1 and the second resistor R2 are equal.
As shown in fig. 3, the DAC main circuit 210 includes: a current mirror circuit 211, a unit current source output switch group 212, a current conversion voltage circuit 213, and a digital decoder 214, wherein the currentA mirror circuit 211 configured to mirror the plurality of unit current sources (I) according to a mirror ratio using the reference current Iref LSB ) The method comprises the steps of carrying out a first treatment on the surface of the The first end of each switch in the unit current source output switch group 212 is coupled to the output end of a unit current source respectively, the second end of each switch is coupled to the first output end voltage Vp respectively, the third end of each switch is coupled to the second output end voltage Vn respectively, the number of switches in the unit current source output switch group 212 is equal to the number of unit current sources, and the unit current source output switch group 212 receives the control signal; a digital decoder 214 configured to receive an input digital signal DATA and convert the input digital signal DATA into a control signal; the current conversion voltage circuit 213 is coupled to the first output voltage Vp and the second output voltage Vn, respectively, and is configured to convert the output current into output voltage analog signals (Voutp, voutn).
As shown in fig. 3, the current mirror circuit 211 includes: the reference current source 2111, the input stage transistor Mn0 and the output stage transistor Mn7, wherein the reference current source 2111 is used for inputting the reference current Iref to the input stage transistor Mn0, one end of the reference current source 2111 is coupled to the power voltage VDD, the other end of the reference current source 2111 is the reference current input end Vr, and the reference current input end Vr is coupled to the second pole of the input stage transistor Mn 0; the first pole of the input stage transistor Mn0 is coupled to the ground terminal; the first pole of each output stage transistor Mn7 is coupled to the ground, the second pole of each output stage transistor Mn7 is coupled to the first pole of a corresponding one of the unit current source output switch sets 212, and the control pole of each output stage transistor Mn7 is coupled to the control pole of the input stage transistor Mn 0. The input stage transistor Mn0 and the output stage transistor Mn7 are N-type transistors, for example, N-type MOS transistors. The mirror ratio of the current mirror circuit is determined by the conducting channel width to length ratio W/L of the input stage transistor Mn0 and the output stage transistor Mn 7.
The current conversion voltage circuit 213 includes: the non-inverting input terminal of the third operational amplifier 2131 is coupled to the first output terminal voltage Vp, one end of the first load resistor 2132, the inverting input terminal of the third operational amplifier 2131 is coupled to the second output terminal voltage Vn, one end of the second load resistor 2133, the inverting output terminal of the third operational amplifier 2131 is coupled to the other end of the first load resistor 2132, the first output voltage Voutp in the voltage analog signal, and the non-inverting output terminal of the third operational amplifier 2131 is coupled to the other end of the second load resistor 2133, the second output voltage Voutn in the voltage analog signal. The current conversion voltage circuit 213 converts the output differential current into a differential voltage output, and the third operational amplifier 2131 operates in a negative feedback mode.
The operation principle of the current steering digital-to-analog conversion circuit 200 of the embodiment of the present disclosure is described with reference to the circuit diagrams in fig. 3 and 4: when the circuit is operating stably, the first operational amplifier 221 operates in a negative feedback mode, according to the negative feedback principle, the voltage at the input end of the first operational amplifier 221 is equal, that is, the voltage Vr at the input end of the reference current is equal to the input reference voltage VCM, that is, vr=vcm, and meanwhile, the output of the first operational amplifier 221 controls the voltage at the control electrode (gate) of the input stage transistor Mn0 in the current mirror circuit 211, so that the current flowing through Mn0 is equal to the input reference current Iref. The first common-mode detection circuit 231 detects the common-mode voltage vcm_in of Vp and Vn and outputs the same to the non-inverting input terminal of the second operational amplifier 233, and simultaneously converts the reference voltage Vcm to the reference common-mode voltage vcm_ref and outputs the same to the non-inverting input terminal of the second operational amplifier 233, the output terminal of the second operational amplifier 233 controls the PMOS transistors Mp5 and Mp6 in the common-mode compensation circuit 234 to adjust the common-mode voltage vcm_in of Vp and Vn, and the common-mode voltage control circuit 230 is a negative feedback structure, so that the common-mode voltage of Vp and Vn, i.e., vcm_in= (vp+vn)/2=vcm, is generated when the circuit is stably operating. The current conversion voltage circuit 213 converts the differential current output from the current steering dac 200 into a differential voltage output, the third operational amplifier 2131 operates in the negative feedback mode, vp=vn during the stable circuit operation, and vr=vp=vn=vcm, which is obtained by combining the obtained (vp+vn)/2=vcm and vr=vcm, can be obtained when the circuit operates stably, that is, the two output voltages Vp and Vn corresponding to the plurality of unit current sources are equal and kept constant as VCM, and therefore, the output current I of the unit current source is LSB Will not change with the input digital signal DATA, thereby effectively improving the line of the current rudder D/A converterDegree of sex. According to the circuit principle of the current steering dac 200, it can be obtained that the output differential voltage Voutp-voutn=data× 2*I of the current steering dac LSB *RL。
Further, in order to intuitively illustrate the technical effects of the current steering DAC (100) according to the embodiments of the present disclosure, fig. 5 shows simulation results of the current steering DAC (100) and Differential Non-linearity (DNL) of the current steering DAC (200) according to the embodiments of the present disclosure, where the abscissa is the output voltage, the ordinate is the DNL value, and curve a is the result of the current steering DAC (100); the curve b is a result of the current steering DAC 200 according to the embodiment of the present disclosure, and comparing the curve a and the curve b, it can be seen that DNL in the curve a increases with the increase of the output voltage, and DNL in the curve b is substantially unchanged, so that the current steering DAC according to the embodiment of the present disclosure can effectively improve the problem of the linearity reduction between the output voltage and the input digital DATA of the current steering DAC.
The embodiment of the disclosure also provides a chip. The chip includes a current steering digital-to-analog conversion circuit according to an embodiment of the present disclosure. The chip is, for example, a digital power supply type chip, a CPU processor including the digital power supply type chip.
The embodiment of the disclosure also provides electronic equipment. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is, for example, a general computer, a server.
In summary, when the circuit stably works, the current steering digital-to-analog conversion circuit in the embodiment of the disclosure can keep the output current of the unit current source stable and does not change along with the change of the output voltage, so that the problem of reduced linearity between the output voltage and the input digital quantity DATA is effectively solved.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the disclosure may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (10)
1. A current steering digital to analog conversion circuit, comprising: a DAC main circuit, a current mirror input end control circuit and a common mode voltage control circuit,
the DAC main circuit is configured to convert an input digital signal into a control signal of a unit current source output switch group, and generate an output current according to the control signal, wherein the output current drives a load resistor and outputs a voltage analog signal, and the unit current source output switch group is a switch group connected with the outputs of a plurality of unit current sources, and the plurality of unit current sources are realized by a current mirror circuit;
the current mirror input end control circuit is configured to control the voltage of a reference current input end in the current mirror circuit to be equal to an input reference voltage through a first operational amplifier;
the common mode voltage control circuit is configured to control the common mode voltage of the first output end voltage and the second output end voltage to be equal to the input reference voltage through the second operational amplifier, wherein the first output end voltage and the second output end voltage are output end voltages of two outputs obtained after the output of the plurality of unit current sources is controlled by the unit current source output switch group.
2. The current steering digital to analog conversion circuit of claim 1, wherein said current mirror input control circuit comprises: the first operational amplifier is configured to provide a first signal,
the inverting input end of the first operational amplifier is coupled with the input reference voltage, the non-inverting input end of the first operational amplifier is coupled with the input end of the reference current in the current mirror circuit, and the output end of the first operational amplifier is coupled with the control electrode of the input stage transistor receiving the reference current in the current mirror circuit.
3. The current steering digital to analog conversion circuit of claim 1, wherein the common mode voltage control circuit comprises: a first common mode detection circuit, a second common mode detection circuit, the second operational amplifier and a common mode compensation circuit,
wherein the first common mode detection circuit is configured to detect a common mode voltage of the first output terminal voltage and the second output terminal voltage and input the common mode voltage to a non-inverting input terminal of the second operational amplifier;
the second common mode detection circuit is configured to convert the input reference voltage into a reference common mode voltage and input the reference common mode voltage to an inverting input terminal of the second operational amplifier;
the common mode compensation circuit is coupled to the output terminal of the second operational amplifier and configured to adjust a common mode voltage of the first output terminal voltage and the second output terminal voltage according to an output result of the second operational amplifier.
4. The current steering digital to analog conversion circuit of claim 3, wherein said first common mode detection circuit comprises: the first current source, the first transistor and the second transistor, wherein one end of the first current source is coupled with the grounding end, and the other end of the first current source is respectively coupled with the first pole of the first transistor, the first pole of the second transistor and the non-inverting input end of the second operational amplifier; the second pole of the first transistor and the second pole of the second transistor are coupled with a power supply voltage, the control pole of the first transistor is coupled with the first output terminal voltage, and the control pole of the second transistor is coupled with the second output terminal voltage;
the second common mode detection circuit includes: the second current source, the third transistor and the fourth transistor, wherein one end of the second current source is coupled with the ground end, and the other end of the second current source is respectively coupled with the first pole of the third transistor, the first pole of the fourth transistor and the inverting input end of the second operational amplifier; the second pole of the third transistor and the second pole of the fourth transistor are coupled to a power supply voltage, and the control pole of the third transistor and the control pole of the fourth transistor are coupled to the input reference voltage.
5. A current steering digital to analog conversion circuit according to claim 3, wherein the common mode compensation circuit comprises: a fifth transistor, a sixth transistor, a first resistor, a second resistor,
the control electrode of the fifth transistor and the control electrode of the sixth transistor are coupled to the output end of the second operational amplifier, the first electrode of the fifth transistor and the first electrode of the sixth transistor are coupled to a power supply voltage, the second electrode of the fifth transistor is respectively coupled to one end of the first resistor and the first output end voltage, and the second electrode of the sixth transistor is respectively coupled to one end of the second resistor and the second output end voltage;
the other end of the first resistor and the other end of the second resistor are coupled with a grounding end.
6. The current steering digital to analog conversion circuit according to any one of claims 1 to 5, wherein the DAC main circuit comprises: the current mirror circuit, the unit current source output switch group, the current conversion voltage circuit and the digital decoder,
wherein the current mirror circuit is configured to mirror out a plurality of unit current sources according to a mirror proportion by using the reference current;
the first end of each switch in the unit current source output switch group is respectively coupled with the output end of one unit current source, the second end of each switch is respectively coupled with the voltage of the first output end, the third end of each switch is respectively coupled with the voltage of the second output end, the number of the switches in the unit current source output switch group is equal to the number of the unit current sources, and the unit current source output switch group receives the control signal;
the digital decoder is configured to receive the input digital signal and convert the input digital signal into the control signal;
the current conversion voltage circuit is coupled to the first output terminal voltage and the second output terminal voltage respectively and is configured to convert the output current into the output voltage analog signal.
7. The current steering digital to analog conversion circuit of claim 6, wherein the current mirror circuit comprises: a reference current source, an input stage transistor, a plurality of output stage transistors,
the reference current source is used for inputting the reference current to the input stage transistor, one end of the reference current source is coupled with a power supply voltage, the other end of the reference current source is the reference current input end and is coupled with a second pole of the input stage transistor;
a first pole of the input stage transistor is coupled with a grounding end;
the first pole of each output stage transistor is coupled to the ground terminal, the second pole of each output stage transistor is coupled to the first terminal of a corresponding one of the unit current source output switch groups, and the control pole of each output stage transistor is coupled to the control pole of the input stage transistor.
8. The current steering digital to analog conversion circuit of claim 7, wherein the current conversion voltage circuit comprises: a third operational amplifier, a first load resistor, a second load resistor,
the non-inverting input end of the third operational amplifier is respectively coupled with the voltage of the first output end, the inverting input end of the first load resistor is respectively coupled with the voltage of the second output end, the inverting output end of the second load resistor is respectively coupled with the other end of the first load resistor and the first output voltage in the voltage analog signal, and the non-inverting output end of the third operational amplifier is respectively coupled with the other end of the second load resistor and the second output voltage in the voltage analog signal.
9. A chip comprising a current steering digital-to-analog conversion circuit according to any of claims 1-8.
10. An electronic device comprising a chip according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310094500.5A CN116131858A (en) | 2023-01-17 | 2023-01-17 | Current rudder digital-to-analog conversion circuit, chip and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310094500.5A CN116131858A (en) | 2023-01-17 | 2023-01-17 | Current rudder digital-to-analog conversion circuit, chip and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116131858A true CN116131858A (en) | 2023-05-16 |
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ID=86311432
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310094500.5A Pending CN116131858A (en) | 2023-01-17 | 2023-01-17 | Current rudder digital-to-analog conversion circuit, chip and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116131858A (en) |
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2023
- 2023-01-17 CN CN202310094500.5A patent/CN116131858A/en active Pending
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