CN116127914A - Power consumption optimization method, device, equipment and storage medium - Google Patents
Power consumption optimization method, device, equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a power consumption optimization method, a device, equipment and a storage medium, wherein the method comprises the following steps: acquiring RTL backward SAIF files based on a preset RTL design file of the target integrated circuit, and reading RTL backward SAIF files into preset back-end design software to perform time sequence unit layout on the target integrated circuit; and when the time sequence unit layout is carried out, carrying out power consumption optimization on the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimization command. According to the invention, RTL backward SAIF files can be generated based on preset RTL design files, the switching behavior conditions of the preset RTL design files are obtained through RTL backward SAIF files, then power consumption analysis is performed based on RTL backward SAIF files and preset power consumption driving optimization commands, and finally time sequence units with high turnover rate in the target integrated circuit are gathered and configured according to the switching behavior conditions and power consumption analysis results, so that the power consumption of the target integrated circuit is reduced.
Description
Technical Field
The present invention relates to the field of electronic digital data processing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for optimizing power consumption.
Background
In the chip design process of an integrated circuit, the power consumption problem of the designed integrated circuit is often considered, and the clock tree design is one of the main directions of the low-power-consumption physical design of the integrated circuit because the clock signal is the signal with the highest flip frequency, the largest driving load and the farthest transmission distance in the whole chip.
The gate clock is adopted to turn off the unnecessary clock through logic operation; or the circuit power consumption is reduced by adopting the traditional low-power design methods such as a multi-voltage domain technology, a power supply shutdown technology and the like.
The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present invention and is not intended to represent an admission that the foregoing is prior art.
Disclosure of Invention
The invention mainly aims to provide a power consumption optimization method, a device, equipment and a storage medium, and aims to provide a power consumption optimization method for performing time sequence unit layout optimization based on SAIF files. In order to achieve the above object, the present invention provides a power consumption optimizing method. The method comprises the following steps:
acquiring a RTL backward SAIF file based on a preset RTL design file of the target integrated circuit;
reading the RTL backward SAIF file into preset back-end design software through a preset reading command, wherein the preset back-end design software is used for carrying out time sequence unit layout on the target integrated circuit;
and when the time sequence unit layout is carried out, carrying out power consumption optimization on the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimization command optDynamicPower.
Optionally, the step of obtaining the RTL backward SAIF file based on the preset RTL design file of the target integrated circuit includes:
acquiring a RTL formward SAIF file based on a preset RTL design file of the target integrated circuit;
inputting the initial testbench test platform file, the preset RTL design file and the RTL forward SAIF file into a VCS to obtain a RTL backward SAIF file.
Optionally, the step of obtaining the RTL formward SAIF file based on the preset RTL design file of the target integrated circuit includes:
and loading a preset RTL design file of the target integrated circuit into a VCS, wherein the VCS is used for converting the preset RTL design file into a gate level netlist and outputting a RTL formward SAIF file after the conversion of the preset RTL design file is completed.
Optionally, the step of inputting the initial testbench test platform file, the preset RTL design file, and the RTL forward SAIF file into the VCS to obtain the RTL backward SAIF file includes:
inputting an initial testbench test platform file into a VCS, and starting testbench;
calling the RTL forward SAIF file and the preset RTL design file in the testbench to load the RTL forward SAIF file and the preset RTL design file into a VCS;
calling a preset PLI system function in the testbench to obtain the node turnover rate of the RTL forward SAIF file;
and simulating the preset RTL design file in the VCS based on the node turnover rate of the RTL forward SAIF file to obtain a RTL backward SAIF file.
Optionally, the step of performing power consumption optimization on the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimization command optDynamicPower when performing the timing unit layout includes:
acquiring switching behavior information of a comprehensive invariant in the preset RTL design file based on the RTL backward SAIF file;
invoking the preset power consumption driving optimization command optDynamicPower to obtain a power consumption analysis result of the preset RTL design file;
acquiring a time sequence unit exceeding a preset turnover rate in the target integrated circuit based on the power consumption analysis result and the switching behavior information of the comprehensive invariant in the preset RTL design file;
and when the time sequence unit layout is carried out, gathering and configuring the time sequence units exceeding a preset turnover rate in the target integrated circuit.
Optionally, the step of calling the preset power consumption driving optimization command optDynamicPower to obtain a power consumption analysis result of the preset RTL design file includes:
invoking the preset power consumption driving optimization command optdynamicower to analyze the element information of the preset RTL design file, and obtaining element power consumption analysis of the preset RTL design file;
invoking the preset power consumption driving optimization command optDynamicPower to analyze node information of the preset RTL design file to obtain element switching power consumption analysis of the preset RTL design file;
and obtaining a power consumption analysis result of the preset RTL design file based on the element power consumption analysis and the element switching power consumption analysis.
Optionally, the step of calling the preset power consumption driving optimization command optdynamicPower to analyze node information of the preset RTL design file and obtain element switching power consumption analysis of the preset RTL design file includes:
invoking the preset power consumption driving optimization command optdynamicower to read the RTL backward SAIF file, and reversely marking the turnover rate in the RTL backward SAIF file to a file node of the preset RTL design file;
traversing file nodes in the preset RTL design file, obtaining the reverse standard rate of each file node, and obtaining the element switching power consumption analysis of the preset RTL design file.
In addition, to achieve the above object, the present invention also proposes a power consumption optimizing apparatus including:
the analysis module is used for obtaining a RTL backward SAIF file based on a preset RTL design file of the target integrated circuit;
the reading module is used for reading the RTL backward SAIF file into preset back-end design software through a preset reading command, and the preset back-end design software is used for carrying out time sequence unit layout on the target integrated circuit;
and the optimizing module is used for optimizing the power consumption of the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimizing command optDynamicPower when the time sequence unit layout is carried out.
In addition, to achieve the above object, the present invention also proposes a power consumption optimizing apparatus, the apparatus comprising: a memory, a processor, and a power consumption optimization program stored on the memory and executable on the processor, the power consumption optimization program configured to implement the steps of the power consumption optimization method as described above.
In addition, to achieve the above object, the present invention also proposes a storage medium having stored thereon a power consumption optimizing program which, when executed by a processor, implements the steps of the power consumption optimizing method as described above.
The method is based on a preset RTL design file of a target integrated circuit, and RTL backward SAIF files are obtained; reading the RTL backward SAIF file into back-end design software through a preset reading command, wherein the preset back-end design software is used for carrying out time sequence unit layout on the target integrated circuit; and when the time sequence unit layout is carried out, carrying out power consumption optimization on the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimization command optDynamicPower. According to the invention, RTL backward SAIF files can be generated based on preset RTL files of the target integrated circuit, the switching behavior of the preset RTL design files can be obtained through RTL backward SAIF files, then power consumption analysis is performed based on RTL backward SAIF files and preset power consumption driving optimization commands, and finally time sequence units with high turnover rate in the target integrated circuit are gathered and configured according to the switching behavior and the power consumption analysis result, namely, the wiring length between the time sequence units with high turnover rate is reduced, so that the turnover power consumption is reduced, and therefore, the power consumption of the target integrated circuit can be reduced.
Drawings
FIG. 1 is a schematic diagram of a power consumption optimization device of a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a flowchart of a power consumption optimization method according to a first embodiment of the present invention;
FIG. 3 is a flow chart of a second embodiment of the power consumption optimization method of the present invention;
FIG. 4 is a flowchart of a third embodiment of a power consumption optimization method according to the present invention;
fig. 5 is a block diagram showing the structure of a first embodiment of the power consumption optimizing apparatus of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic diagram of a power consumption optimizing device in a hardware running environment according to an embodiment of the present invention.
As shown in fig. 1, the power consumption optimizing device may include: a processor 1001, such as a central processing unit (Central Processing Unit, CPU), a communication bus 1002, a user interface 1003, a network interface 1004, a memory 1005. Wherein the communication bus 1002 is used to enable connected communication between these components. The user interface 1003 may include a Display, an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may further include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a Wireless interface (e.g., a Wireless-Fidelity (WI-FI) interface). The Memory 1005 may be a high-speed random access Memory (Random Access Memory, RAM) or a stable nonvolatile Memory (NVM), such as a disk Memory. The memory 1005 may also optionally be a storage device separate from the processor 1001 described above.
Those skilled in the art will appreciate that the structure shown in fig. 1 does not constitute a limitation of the power consumption optimizing device, and may include more or fewer components than shown, or may combine certain components, or may be a different arrangement of components.
As shown in fig. 1, an operating system, a data storage module, a network communication module, a user interface module, and a power consumption optimization program may be included in the memory 1005 as one type of storage medium.
In the power consumption optimization device shown in fig. 1, the network interface 1004 is mainly used for data communication with a network server; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the power consumption optimizing apparatus of the present invention may be disposed in the power consumption optimizing apparatus, and the power consumption optimizing apparatus calls the power consumption optimizing program stored in the memory 1005 through the processor 1001 and executes the power consumption optimizing method provided by the embodiment of the present invention.
An embodiment of the present invention provides a power consumption optimization method, referring to fig. 2, fig. 2 is a schematic flow chart of a first embodiment of the power consumption optimization method of the present invention.
In this embodiment, the power consumption optimization method includes the following steps:
step S10: acquiring a RTL backward SAIF file based on a preset RTL design file of the target integrated circuit;
it should be noted that, the execution body of the method of the embodiment may be a computing service device having functions of data processing, network communication and program running, for example, a tablet computer, a personal computer, or other electronic devices capable of implementing the same or similar functions. The power consumption optimizing method provided by the present embodiment and the embodiments described below will be specifically described herein with the above-described power consumption optimizing apparatus (optimizing apparatus for short).
It should be understood that a digital integrated circuit is composed of two basic devices, one is a logic device whose output signal is affected only by the current state of the input signal, called a combinational logic device, and the device has no memory function, so long as the input signal changes, the output signal changes accordingly. The other type is a logic device, called a sequential logic device, in which the output signal is related to not only the state of the input signal at the current time but also the state of the input signal at the previous time, and the device has a memory function. RTL (Register Transfer Level ) design refers to the description of circuits containing these two types of devices using a hardware description language (a language capable of describing logic devices, such as Verilog HDL language), which description is based on transfer between registers and is therefore referred to as RTL (register transfer level) design. The preset RTL design file may be a file generated by performing RTL design based on the functional requirement of the target integrated circuit.
It should be noted that, the above-mentioned preset RTL design file also needs to be converted into the target integrated circuit through behavior simulation, timing simulation and post-simulation. And SAIF files are generated in the process of carrying out behavior simulation on the preset RTL design files, the SAIF files (switching activity interchange format) and the internal switching format files of the switching behaviors are ASCII files (or internal switching format files for recording the switching behaviors of the integrated circuits) for recording information exchanged between the simulator and the power consumption analysis. After the RTL code is simulated, the SAIF file can be recorded under a certain working scene, and the SAIF file can be generated through a gate-level netlist or the RTL code under the static probability and the turnover rate of signals on interconnection lines and unit pins within a period of time. The RTL backward SAIF file may be obtained by simulating an RTL code in a preset RTL design file, and may be a switching behavior file in which a comprehensive invariant turnover rate in the preset RTL design file is recorded, where the switching behavior may be a turnover rate and a static probability in the preset RTL design file, and the turnover refers to a change in a logic value of a node signal, and the static refers to a change in a logic value of the node signal. Synthesis means that design inputs such as HDL language, schematic diagram and the like are translated into gate-level connections (or gate-level netlists) composed of AND, OR, NOT and the like basic logic units, the generated logic connections are optimized according to design targets and requirements (or constraint conditions), and gate-level netlist files are output. Before and after synthesis, the number of registers and the structure of the registers in the design are unchanged, the input/output ports and the level boundaries are unchanged, and the black boxes in the design are unchanged, namely the synthesis invariants.
Step S20: reading the RTL backward SAIF file into preset back-end design software through a preset reading command, wherein the preset back-end design software is used for carrying out time sequence unit layout on the target integrated circuit;
it should be noted that, after the RTL backward SAIF file is obtained, the preset back-end design software may read the RTL backward SAIF file by optimizing a preset read command preset in the device, where the preset back-end software may be a layout and wiring tool such as Cadence Innovus, synopsys ICC2, and the specific type of the preset back-end software is not limited in this embodiment. In addition, the timing unit is a clock logic device of the integrated circuit.
Step S30: and when the time sequence unit layout is carried out, carrying out power consumption optimization on the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimization command optDynamicPower.
It should be understood that, in the chip design process, after the standard cell placement and clock tree design are completed, in order not to affect the timing sequence in the subsequent optimization process, the clock line is generally not modified in a large scale, so that the power consumption of the chip is generally not increased greatly, and therefore, the approximate power consumption can be obtained after the layout of the timing sequence cells is completed.
It should be understood that the preset power consumption driving optimization command optdynamicPower is a command to be called integrated in Cadence Innovus, and can be used for replacing a unit of a target integrated circuit and optimizing power consumption on the premise of meeting a time sequence. In the embodiment, a design method of cooperative optimization of turnover rate load is adopted to carry out low-power-consumption design in the layout stage of the time sequence units. Specifically, the preset power consumption may be used to drive the optimization command optDynamicPower to perform low-power consumption collaborative optimization with the above (the command is to perform unit replacement, and optimize power consumption on the premise of meeting the time sequence) and the RTL backward SAIF file.
The embodiment obtains a RTL backward SAIF file based on a preset RTL design file of a target integrated circuit; reading the RTL backward SAIF file into preset back-end design software through a preset reading command, wherein the preset back-end design software is used for carrying out time sequence unit layout on the target integrated circuit; and when the time sequence unit layout is carried out, carrying out power consumption optimization on the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimization command optDynamicPower. According to the embodiment, RTL backward SAIF files can be generated based on the preset RTL files of the target integrated circuit, the switching behavior of the preset RTL design files is obtained through RTL backward SAIF files, then power consumption analysis is performed based on RTL backward SAIF files and the preset power consumption driving optimization command, and finally time sequence units with high turnover rate in the target integrated circuit are gathered and configured according to the switching behavior and the power consumption analysis result, namely, the wiring length between the time sequence units with high turnover rate is reduced, so that the turnover power consumption is reduced, and therefore the power consumption of the target integrated circuit can be reduced.
Referring to fig. 3, fig. 3 is a flowchart illustrating a second embodiment of the power consumption optimizing method according to the present invention, and based on the embodiment shown in fig. 2, the second embodiment of the power consumption optimizing method according to the present invention is provided.
As shown in fig. 3, step S10 in this embodiment includes:
step S101: acquiring a RTL formward SAIF file based on a preset RTL design file of the target integrated circuit;
it should be noted that, the RTL formward SAIF file may be directly generated by the RTL code of the preset RTL file, or may be generated during synthesis (i.e. the process of converting the RTL code in the preset RTL design file into the gate-level netlist), and the RTL formward SAIF file generated during synthesis more specifically includes more switching activity information in the preset RTL design file, so that the accuracy of the subsequent power consumption analysis may be improved.
It should be understood that, specifically, based on the preset RTL design file of the target integrated circuit, the method for obtaining the RTL formward SAIF file may be: in this embodiment, the preset RTL design file may be synthesized by a simulation synthesis tool such as cadence plus, etc., so as to obtain the RTL formward SAIF file. It is also possible that: the preset RTL design file is loaded into the VCS, and the VCS is a compiling type Verilog simulator which can be used for converting the preset RTL design file into a gate level netlist and outputting RTL formward SAIF files after the conversion of the preset RTL design file is completed.
Step S102: inputting the initial testbench test platform file, the preset RTL design file and the RTL forward SAIF file into a VCS to obtain a RTL backward SAIF file.
It should be noted that testbench is a verification means, and is a "virtual platform" that simulates the input excitation and output verification of an actual environment. Because there is no stimulus input in the software environment, the output correctness of the design cannot be evaluated, but the design can be analyzed and verified on a software level on testbench. In this embodiment, testbench may run in the VCS, and the VCS may be enabled by entering an initial testbench test platform file into the VCS.
Further, in the present embodiment, step S102 includes:
step S1021: inputting an initial testbench test platform file into a VCS, and starting testbench;
step S1022: calling the RTL forward SAIF file and the preset RTL design file in the testbench to load the RTL forward SAIF file and the preset RTL design file into a VCS;
step S1023: calling a preset PLI system function in the testbench to obtain the node turnover rate of the RTL forward SAIF file;
step S1024: and simulating the preset RTL design file in the VCS based on the node turnover rate of the RTL forward SAIF file to obtain a RTL backward SAIF file.
It should be noted that, after the initial testbench test platform file is input into the VCS, the testbench may be started, then the RTL forward SAIF file and the preset RTL design file may be called in the testbench, and the RTL forward SAIF file and the preset RTL design file may be loaded into the VCS. In addition, the preset PLI system function can be directly called through testbench, and the PLI system function can detect the turnover of the nodes in the file, so that the turnover rate of each node in the file can be obtained. Therefore, the embodiment can call the preset PLI system function in testbench to obtain the node turnover rate of the RTL forward SAIF file.
It should be understood that after the node turnover rate of the RTL forward SAIF file is obtained, the testbench test file may be input again in the VCS to load the node turnover rate of the RTL forward SAIF file, and the simulation is performed on the testbench test file and on the preset RTL design file simultaneously through the VCS to obtain the RTL backward SAIF file.
It can be understood that after the RTL code in the preset RTL design file is simulated, the obtained RTL backward SAIF file contains the switching behavior information of the integrated invariant in the preset RTL design. When the power consumption analysis is carried out later, the tool is used for transmitting the turnover rate of the comprehensive unchanged object through the internal simulator, so that the turnover rate of all other nodes can be obtained, and the power consumption analysis of the gate-level circuit is carried out.
In this embodiment, the preset RTL design file of the target integrated circuit is loaded into the VCS, and the VCS is configured to convert the preset RTL design file into a gate netlist, and output RTL formward SAIF files after the conversion of the preset RTL design file is completed. Inputting an initial testbench test platform file into a VCS, and starting testbench; calling an RTL forward SAIF file and a preset RTL design file in a testbench, so that the RTL forward SAIF file and the preset RTL design file are loaded into a VCS; calling a preset PLI system function in a testbench to obtain the node turnover rate of the RTL forward SAIF file; based on the node turnover rate of the RTL forward SAIF file, a preset RTL design file is simulated in the VCS to obtain a RTL backward SAIF file. According to the embodiment, more switch activity information in the preset RTL design file can be obtained by generating the RTL formward SAIF file, so that the accuracy of comprehensive invariant flip rate analysis in the RTL formward SAIF file can be improved, and the accuracy of subsequent power consumption analysis can be improved.
Referring to fig. 4, fig. 4 is a schematic flow chart of a third embodiment of the power consumption optimizing method according to the present invention, based on the embodiment shown in fig. 2 or 3, the third embodiment of the power consumption optimizing method according to the present invention is proposed, and fig. 4 is an example of the embodiment proposed based on the embodiment shown in fig. 1.
Further, as an embodiment, step S30 in the present embodiment includes:
step S301: acquiring switching behavior information of a comprehensive invariant in the preset RTL design file based on the RTL backward SAIF file;
step S302: invoking the preset power consumption driving optimization command optDynamicPower to obtain a power consumption analysis result of the preset RTL design file;
it should be noted that, after the preset power consumption driving optimization command optdynamicopower is called, cadence Innovus may perform power consumption analysis of the target integrated circuit based on the element information and the node information in the preset RTL design file.
Therefore, further, in the present embodiment, step S301 includes:
step S3021: invoking the preset power consumption driving optimization command optdynamicower to analyze the element information of the preset RTL design file, and obtaining element power consumption analysis of the preset RTL design file;
it should be noted that, the component information of the preset RTL design file may be a process library including power consumption information, which is generally provided by a foundry of the component; parasitic parameters such as parasitic capacitance, parasitic resistance and the like of wires in a preset RTL design file can be also adopted, the parasitic parameters are generally provided by a back-end RC parasitic parameter tool, and the information is not needed to be analyzed in a simple power consumption analysis.
Step S3022: invoking the preset power consumption driving optimization command optDynamicPower to analyze node information of the preset RTL design file to obtain element switching power consumption analysis of the preset RTL design file;
it should be noted that, the node information of the preset RTL design file may be a gate level netlist circuit of the preset RTL design file, which may be obtained by synthesizing the preset RTL design file; the switching behavior of each node in the preset RTL design file may also be a file, such as a node turnover rate (turnover times of signals such as clock and data in unit time), etc.; a file for calculating the roll-over rate of each node is also possible. The analysis of the inversion rate may include three cases:
(1) If a VCD/SAIF file is provided, the true flip rate can be reversely marked on the node of the file, then the reverse mark rate of the file is checked, and finally the power consumption value is reported.
(2) Manually setting node turnover rate: the register, clock gate, and flip rate of the rural memory/black box are set according to the empirical values.
(3) Using a default roll-over rate: default roll-over rates are used with simulation tools by setting variables.
It should be understood that, in this embodiment, after the RTL backward SAIF file is obtained, the preset power consumption driving optimization command optdynamicower is called to read RTL backward SAIF file, and the turnover rate in the RTL backward SAIF file is reversely marked to the file node of the preset RTL design file; traversing file nodes in a preset RTL design file to obtain the anti-standard rate of each file node, thereby obtaining the element switching power consumption analysis of the preset RTL design file. Specifically, the simulation tool is used for transmitting the turnover rate of the comprehensive unchanged object in the RTL backward SAIF file through the internal simulator, so that the turnover rate of all other nodes of the preset RTL design file can be obtained, and further the element switch power consumption analysis of the preset RTL design file is obtained.
Step S3023: and obtaining a power consumption analysis result of the preset RTL design file based on the element power consumption analysis and the element switching power consumption analysis.
Step S303: acquiring a time sequence unit exceeding a preset turnover rate in the target integrated circuit based on the power consumption analysis result and the switching behavior information of the comprehensive invariant in the preset RTL design file;
it should be noted that, after the power consumption analysis result of the preset RTL design file is obtained, the preset turnover rate corresponding to the low power consumption requirement can be obtained based on the power consumption analysis result, and then the time sequence unit exceeding the preset turnover rate in the target integrated circuit can be obtained after the turnover rate of all the nodes in the preset RTL design file is obtained based on the switching behavior information of the integrated invariable in the preset RTL design file.
Step S304: and when the time sequence unit layout is carried out, gathering and configuring the time sequence units exceeding a preset turnover rate in the target integrated circuit.
It should be noted that, the above-mentioned gathering configuration may refer to reducing the wiring length between the timing units greater than the preset flip rate, so as to reduce the wire delay between the timing units with high flip rate, thereby reducing the power consumption of the target integrated circuit.
Based on RTL backward SAIF file, the embodiment obtains the switching behavior information of the comprehensive unchanged object in the preset RTL design file; invoking a preset power consumption driving optimization command optDynamicPower to analyze the element information of the preset RTL design file to obtain element power consumption analysis of the preset RTL design file; invoking a preset power consumption driving optimization command optDynamicPower to analyze node information of a preset RTL design file to obtain element switching power consumption analysis of the preset RTL design file; based on the element power consumption analysis and the element switching power consumption analysis, obtaining a power consumption analysis result of the preset RTL design file; acquiring a time sequence unit exceeding a preset turnover rate in a target integrated circuit based on a power consumption analysis result and switching behavior information of a comprehensive invariant in a preset RTL design file; and when the time sequence unit layout is carried out, gathering and configuring the time sequence units exceeding the preset turnover rate in the target integrated circuit. Therefore, the embodiment can obtain not only the component power consumption analysis of the preset RTL design file, but also the component switching power consumption analysis of the preset RTL design file by combining the RTL backward SAIF file and the power consumption driving command. After the more accurate preset turnover rate is obtained based on the common analysis of the two types of power consumption analysis results, the layout and wiring tool can combine the condition of the switching behavior in the RTL backward SAIF file, so that the gathering effect between time sequence units with the turnover rate being greater than the preset turnover rate is more obvious, and the time sequence convergence of the target integrated circuit is facilitated. Therefore, the power consumption of the target integrated circuit can be reduced.
In addition, the embodiment of the invention also provides a storage medium, wherein the storage medium is stored with a power consumption optimizing program, and the power consumption optimizing program realizes the steps of the power consumption optimizing method when being executed by a processor.
Referring to fig. 5, fig. 5 is a block diagram showing the structure of a first embodiment of the power consumption optimizing apparatus of the present invention.
As shown in fig. 5, the power consumption optimizing apparatus according to the embodiment of the present invention includes:
the analysis module 501 is configured to obtain a RTL backward SAIF file based on a preset RTL design file of the target integrated circuit;
the reading module 502 is configured to read the RTL backward SAIF file into preset back-end design software through a preset reading command, where the preset back-end design software is configured to perform a time sequence unit layout on the target integrated circuit;
and an optimizing module 503, configured to optimize power consumption of the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimizing command optDynamicPower when the timing unit layout is performed.
The embodiment obtains a RTL backward SAIF file based on a preset RTL design file of a target integrated circuit; reading the RTL backward SAIF file into preset back-end design software through a preset reading command, wherein the preset back-end design software is used for carrying out time sequence unit layout on the target integrated circuit; and when the time sequence unit layout is carried out, carrying out power consumption optimization on the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimization command optDynamicPower. According to the embodiment, RTL backward SAIF files can be generated based on the preset RTL files of the target integrated circuit, the switching behavior of the preset RTL design files is obtained through RTL backward SAIF files, then power consumption analysis is performed based on RTL backward SAIF files and the preset power consumption driving optimization command, and finally time sequence units with high turnover rate in the target integrated circuit are gathered and configured according to the switching behavior and the power consumption analysis result, namely, the wiring length between the time sequence units with high turnover rate is reduced, so that the turnover power consumption is reduced, and therefore the power consumption of the target integrated circuit can be reduced.
Other embodiments or specific implementation manners of the power consumption optimizing apparatus of the present invention may refer to the above method embodiments, and are not described herein again.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as described above, comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (10)
1. A power consumption optimization method, characterized in that the power consumption optimization method comprises the steps of:
acquiring a RTL backward SAIF file based on a preset RTL design file of the target integrated circuit;
reading the RTL backward SAIF file into preset back-end design software through a preset reading command, wherein the preset back-end design software is used for carrying out time sequence unit layout on the target integrated circuit;
and when the time sequence unit layout is carried out, carrying out power consumption optimization on the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimization command optDynamicPower.
2. The power consumption optimization method of claim 1, wherein the step of obtaining RTL backward SAIF file based on the preset RTL design file of the target integrated circuit comprises:
acquiring a RTL formward SAIF file based on a preset RTL design file of the target integrated circuit;
inputting the initial testbench test platform file, the preset RTL design file and the RTL forward SAIF file into a VCS to obtain a RTL backward SAIF file.
3. The power consumption optimization method of claim 2, wherein the step of obtaining RTL formward SAIF file based on the preset RTL design file of the target integrated circuit comprises:
and loading a preset RTL design file of the target integrated circuit into a VCS, wherein the VCS is used for converting the preset RTL design file into a gate level netlist and outputting a RTL formward SAIF file after the conversion of the preset RTL design file is completed.
4. The power consumption optimizing method as claimed in claim 2, wherein the step of inputting the initial testbench test platform file, the preset RTL design file, and the RTL forward SAIF file into the VCS to obtain the RTL backward SAIF file comprises:
inputting an initial testbench test platform file into a VCS, and starting testbench;
calling the RTL forward SAIF file and the preset RTL design file in the testbench to load the RTL forward SAIF file and the preset RTL design file into a VCS;
calling a preset PLI system function in the testbench to obtain the node turnover rate of the RTL forward SAIF file;
and simulating the preset RTL design file in the VCS based on the node turnover rate of the RTL forward SAIF file to obtain a RTL backward SAIF file.
5. The power consumption optimization method as claimed in claim 1, wherein the step of performing power consumption optimization on the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimization command optDynamicPower when performing the timing unit layout includes:
acquiring switching behavior information of a comprehensive invariant in the preset RTL design file based on the RTL backward SAIF file;
invoking the preset power consumption driving optimization command optDynamicPower to obtain a power consumption analysis result of the preset RTL design file;
acquiring a time sequence unit exceeding a preset turnover rate in the target integrated circuit based on the power consumption analysis result and the switching behavior information of the comprehensive invariant in the preset RTL design file;
and when the time sequence unit layout is carried out, gathering and configuring the time sequence units exceeding a preset turnover rate in the target integrated circuit.
6. The power consumption optimization method as claimed in claim 5, wherein the step of calling the preset power consumption driving optimization command optDynamicPower to obtain a power consumption analysis result of the preset RTL design file comprises:
invoking the preset power consumption driving optimization command optdynamicower to analyze the element information of the preset RTL design file, and obtaining element power consumption analysis of the preset RTL design file;
invoking the preset power consumption driving optimization command optDynamicPower to analyze node information of the preset RTL design file to obtain element switching power consumption analysis of the preset RTL design file;
and obtaining a power consumption analysis result of the preset RTL design file based on the element power consumption analysis and the element switching power consumption analysis.
7. The power consumption optimization method as claimed in claim 6, wherein the step of calling the preset power consumption driving optimization command optDynamicPower to analyze node information of the preset RTL design file and obtain the component switching power consumption analysis of the preset RTL design file includes:
invoking the preset power consumption driving optimization command optdynamicower to read the RTL backward SAIF file, and reversely marking the turnover rate in the RTL backward SAIF file to a file node of the preset RTL design file;
traversing file nodes in the preset RTL design file, obtaining the reverse standard rate of each file node, and obtaining the element switching power consumption analysis of the preset RTL design file.
8. A power consumption optimizing apparatus, characterized in that the power consumption optimizing apparatus comprises:
the analysis module is used for obtaining a RTL backward SAIF file based on a preset RTL design file of the target integrated circuit;
the reading module is used for reading the RTL backward SAIF file into preset back-end design software through a preset reading command, and the preset back-end design software is used for carrying out time sequence unit layout on the target integrated circuit;
and the optimizing module is used for optimizing the power consumption of the target integrated circuit based on the RTL backward SAIF file and a preset power consumption driving optimizing command optDynamicPower when the time sequence unit layout is carried out.
9. A power consumption optimizing device, the device comprising: a memory, a processor and a power consumption optimization program stored on the memory and executable on the processor, the power consumption optimization program being configured to implement the steps of the power consumption optimization method of any one of claims 1 to 7.
10. A storage medium having stored thereon a power consumption optimizing program which, when executed by a processor, implements the steps of the power consumption optimizing method according to any one of claims 1 to 7.
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