CN116127894A - Circuit, method, device and medium for data sorting - Google Patents

Circuit, method, device and medium for data sorting Download PDF

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Publication number
CN116127894A
CN116127894A CN202211658286.3A CN202211658286A CN116127894A CN 116127894 A CN116127894 A CN 116127894A CN 202211658286 A CN202211658286 A CN 202211658286A CN 116127894 A CN116127894 A CN 116127894A
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data
comparator
parallel
selector
output
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夏城
郭超
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Shenzhen Dapu Microelectronics Co Ltd
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Shenzhen Dapu Microelectronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a circuit, a method, a device and a medium for data sorting, which are applicable to the technical field of sorting. The number of the parallel comparator units is the same as that of the data to be sequenced of the previous data interface, a first input end of the comparator is connected with the output end of the register group, a second input end of the comparator is connected with the previous data interface, and the output end of the comparator is connected with the control end of the data selector; the input end of the data selector is respectively connected with the output end of the register group, the front stage data interface, the input signal interface and the enabling signal interface. The current data to be sequenced and the stored data are processed in parallel through the comparators in each parallel comparator unit, so that the data parallel sequencing is realized, the sequencing time is reduced, meanwhile, the clock cycle of the current circuit is determined according to the data quantity of the sequencing data, namely, the whole sequencing time of n sequencing data is n clock cycles, so that the breakthrough of time complexity to O (nlog) is realized 2 n) shortens the data ordering event complexity to O (n).

Description

Circuit, method, device and medium for data sorting
Technical Field
The present invention relates to the field of ordering technologies, and in particular, to a circuit, a method, an apparatus, and a medium for data ordering.
Background
Ordering is one of the basic operations of data processing, some important algorithms (such as human data compression and the like) can relate to data ordering, and the execution efficiency of the algorithms can be influenced by the speed of data ordering. The software data ordering algorithm is developed to be mature, and common software ordering algorithms include insert ordering, hill ordering and selection orderingSequencing, heap sequencing, bubbling sequencing, quick sequencing, merging sequencing and the like, wherein the average time complexity of each algorithm is O (n 2 )、O(n 1.3 )、O(n 2 )、O(nlog 2 n)、O(n 2 )、O(nlog 2 n)、O(nlog 2 n), it can be seen that the average time complexity of each algorithm does not break through to O (nlog) 2 n)。
The more data participating in data sorting in the existing software sorting algorithm, the more time cost for data sorting is generated, the smaller and better the delay of data processing is required for the algorithm with higher real-time requirements (real-time compression algorithm), which means that the higher the time cost requirement for data sorting is, and the conventional software sorting algorithm cannot meet the requirement for real-time.
Thus, a need exists in the art for a circuit that seeks data ordering.
Disclosure of Invention
The invention aims to provide a circuit, a method, a device and a medium for ordering data, which realize the breakthrough of time complexity to O (nlog) 2 n) shortens the data ordering event complexity to O (n).
In order to solve the technical problems, the invention provides a data ordering circuit, which comprises a front data interface and parallel comparator units, wherein the number of the parallel comparator units is the same as that of data to be ordered of the front data interface, and the parallel comparator units comprise comparators, data selectors and register groups;
the first input end of the comparator is connected with the output end of the register set, the second input end of the comparator is connected with the front-stage data interface, and the output end of the comparator is connected with the control end of the data selector; the comparator is used for comparing the current data to be sequenced with the stored data of the register group in parallel to obtain parallel result data, and determining corresponding control end data of the data selector according to the parallel result data;
the input end of the data selector is respectively connected with the output end of the register set, the front-stage data interface, the input signal interface and the enabling signal interface, and the data selector is used for determining output data of the register set of the next clock period according to the relation between signals of the corresponding input end and data of the control end so as to facilitate sequencing of the data to be sequenced next; the register set is used for latching the output data and the parallel result data of the current clock cycle so as to finish the data sorting of the current data to be sorted in the current clock cycle.
Preferably, the number of the parallel comparator units is at least two, the input signal interface and the enable signal interface are fixed input signal interfaces and fixed enable signal interfaces in the data selector of the first-stage parallel comparator unit, and the input signal interfaces and the enable signal interfaces in the data selector of the other parallel comparator units are respectively connected with the output end of the register group of the last parallel comparator unit and the output end of the comparator of the last parallel comparator unit.
Preferably, the data selector includes a first data selector and a second data selector;
the first input end of the first data selector is connected with the output end of the register set, the second input end of the first data selector is connected with the front-stage data interface, the output end of the first data selector is connected with the first input end of the second data selector, and the control end of the first data selector is connected with the output end of the comparator;
a second input end of the second data selector is connected with the input signal interface; and the control end of the second data selector is connected with the enabling signal interface.
In order to solve the technical problem, the invention also provides a data sorting method which is applied to a data sorting circuit, wherein the circuit comprises a front data interface and parallel comparator units, the number of the parallel comparator units is the same as that of data to be sorted of the front data interface, and the parallel comparator units comprise comparators, data selectors and register groups; the first input end of the comparator is connected with the output end of the register set, the second input end is connected with the front stage data interface, the output end is connected with the control end of the data selector, the input end of the data selector is respectively connected with the output end of the register set, the front stage data interface, the input signal interface and the enabling signal interface, and the method comprises the following steps:
the comparator is controlled to compare the current data to be sequenced with the stored data of the register group in parallel to obtain parallel result data, and the control end data of the corresponding data selector is determined according to the parallel result data;
controlling the data selector to determine output data of the register group of the next clock period according to the relation between the signal of the corresponding input end and the data of the control end so as to facilitate the sequencing of the next data to be sequenced;
The control register set latches the output data and the parallel result data of the current clock cycle so as to finish the data sorting of the current data to be sorted in the current clock cycle.
Preferably, the controlling the comparator to determine control end data of the corresponding data selector according to the parallel result data includes:
controlling the comparator to acquire the data to be ordered and the stored data;
when the data to be ordered is smaller than the stored data, determining that the control end data of the corresponding data selector is 1;
and when the data to be ordered is larger than or equal to the stored data, determining that the control end data of the corresponding data selector is 0.
Preferably, the controlling the data selector determines output data of the register set of a next clock cycle according to a relation between a signal of a corresponding input terminal and the control terminal data, including:
the data selector is controlled to acquire the control end data, the input signals of the input signal interface, the enable signals of the enable signal interface, the data to be ordered and the output end signals of the register group;
when the enabling signal is 1, determining output data of the next clock cycle as the input signal of the data selector currently;
When the control end data is 0 and the enabling signal is 0, determining that the output data of the next clock period is the same as the output data of the current clock period;
and when the control end data is 1 and the enabling signal is 0, determining the output data of the next clock period as the data to be sequenced.
Preferably, when the data to be ordered is plural, the output data of the current register set in the current clock cycle is less than or equal to the output data of each subsequent register set starting from the current register set.
In order to solve the technical problem, the invention also provides a data sorting device which is applied to a data sorting circuit, wherein the circuit comprises a front data interface and parallel comparator units, the number of the parallel comparator units is the same as that of data to be sorted of the front data interface, and the parallel comparator units comprise comparators, data selectors and register groups; the first input end of the comparator is connected with the output end of the register set, the second input end is connected with the front stage data interface, the output end is connected with the control end of the data selector, the input end of the data selector is respectively connected with the output end of the register set, the front stage data interface, the input signal interface and the enabling signal interface, and the method comprises the following steps:
The first control module is used for controlling the comparator to compare the current data to be sequenced with the storage data of the register group in parallel to obtain parallel result data, and determining corresponding control end data of the data selector according to the parallel result data;
the second control module is used for controlling the data selector to determine output data of the register group of the next clock period according to the relation between the signal of the corresponding input end and the data of the control end so as to facilitate the ordering of the next data to be ordered;
and the third control module is used for controlling the register group to latch the output data and the parallel result data of the current clock cycle so as to finish the data ordering of the current data to be ordered in the current clock cycle.
In order to solve the technical problem, the present invention further provides a device for ordering data, including:
a memory for storing a computer program;
a processor for implementing the steps of the method of data sorting as described above when executing the computer program.
To solve the above technical problem, the present invention further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the method for ordering data as described above.
The invention provides a data sequencing circuit, which comprises a front data interface and parallel comparator units, wherein the number of the parallel comparator units is the same as that of data to be sequenced of the front data interface, and the parallel comparator units comprise comparators, data selectors and register groups; the first input end of the comparator is connected with the output end of the register set, the second input end of the comparator is connected with the front data interface, and the output end of the comparator is connected with the control end of the data selector; the input end of the data selector is respectively connected with the output end of the register group, the front stage data interface, the input signal interface and the enabling signal interface. The comparator is used for comparing the current data to be ordered with the stored data of the register group in parallel to obtain parallel result data, determining control end data of a corresponding data selector according to the parallel result data, determining output data of the register group of the next clock period according to the relation between signals of a corresponding input end and the control end data so as to be convenient for ordering of the next data to be ordered, and the register group is used for latching the output data and the parallel result data of the current clock period so as to be convenient for completing data ordering of the current data to be ordered in the current clock period. The circuit processes the current data to be ordered and the stored data in parallel through the comparators in each parallel comparator unit to realize the parallel ordering of the data, Reducing the ordering time, and determining the clock cycle of the current circuit according to the data quantity of the ordering data, namely, the total ordering time of n ordering data is n clock cycles, thereby realizing the time complexity break through to O (nlog 2 n) shortens the complexity of the data ordering event to O (n), has simple circuit structure and shorter combinational logic path, and further shortens the cost of the data ordering time.
In addition, the invention also provides a data sorting method, a data sorting device and a data sorting medium, which have the same beneficial effects as the data sorting circuit.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a schematic diagram of a circuit for ordering data according to an embodiment of the present invention;
FIG. 2 is a block diagram of a parallel comparator unit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an N parallel data sorting circuit according to an embodiment of the present invention;
FIG. 4 is a flowchart of a method for ordering data according to an embodiment of the present invention;
FIG. 5 is a block diagram of a data sorting apparatus according to an embodiment of the present invention;
fig. 6 is a block diagram of another apparatus for data sorting according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
The core of the invention is to provide a circuit, a method, a device and a medium for ordering data, which realize the breakthrough of time complexity to O (nlog) 2 n) shortens the data ordering event complexity to O (n).
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
It should be noted that, the circuit for ordering data provided by the invention solves the problem that the time complexity breaks through to O (nlog 2 n). Breakthrough O here (nlog 2 n) is represented by the formula O (nlog 2 n) below, according to the parallelism characteristic of the hardware circuit, the comparison of a plurality of data can be carried out at the same time.
Fig. 1 is a schematic diagram of a circuit for ordering data, which is provided in an embodiment of the present invention, as shown in fig. 1, and includes a front-stage data interface 1 and parallel comparator units 2, where the number of parallel comparator units 2 is the same as the number of data to be ordered of the front-stage data interface 1, and the parallel comparator units 2 include comparators 3, data selectors 4 and register groups 5;
the first input end of the comparator 3 is connected with the output end of the register group 5, the second input end is connected with the front stage data interface 1, and the output end is connected with the control end of the data selector 4; the comparator 3 is used for comparing the current data to be sequenced with the stored data of the register group 5 in parallel to obtain parallel result data, and determining the corresponding control end data of the data selector 4 according to the parallel result data;
the input end of the data selector 4 is respectively connected with the output end of the register set 5, the front stage data interface 1, the input signal interface 6 and the enabling signal interface 7, and the data selector 4 is used for determining the output data of the register set 5 of the next clock period according to the relation between the signal of the corresponding input end and the data of the control end so as to facilitate the ordering of the next data to be ordered; the register set 5 is used for latching the output data and the parallel result data of the current clock cycle so as to complete the data sorting of the current data to be sorted in the current clock cycle.
Specifically, the data to be sequenced is stored in the front data interface, and the number of the parallel comparator units is the same as the number of the data to be sequenced in the front data interface, that is, the same as the number of the clock cycle of the circuit. And at the data input node to be sequenced, the data sequencing is completed at the same time, and only one data to be sequenced is input in each clock cycle. n pieces of data to be sequenced participate in sequencing, n clock cycles are consumed to input all comparison data into a sequencing circuit, and the circuit also needs to complete data sequencing in each clock cycle.
After the data is sorted, storing all the compared data to be sorted in the circuit, wherein one parallel comparator unit only stores one comparison data, and if 5 data to be sorted participate in sorting, at least 5 parallel comparator units are needed. After the data ordering is completed, all the data to be ordered can be stored.
The parallel comparator unit includes a comparator, a data selector, and a register set. The comparator is used for comparing the current data to be ordered with the storage data of the register group in parallel to obtain parallel result data. In this embodiment, parallel result data is obtained by parallel comparison of a plurality of comparators in a plurality of parallel comparator units in the current data to be sorted, which is implemented by the plurality of parallel comparator units set for all the data to be sorted. And the parallelism of the hardware circuit is fully utilized according to the parallel processing, so that the overhead of the data ordering time is shortened. Correspondingly, the stored data of the register set includes the already input data to be ordered, the initial value, and the data related to the next clock cycle.
For example, 5 data to be sorted are available, when the current data to be sorted is input to the comparators, the comparators do not interfere with each other to realize parallel processing due to the fact that 5 comparators exist and the 5 comparators act simultaneously. The first input end of the comparator is connected with the output end of the register group so as to facilitate the comparison of the stored data of the register group, the second input end of the comparator is connected with the front data interface so as to facilitate the reception of the data to be sequenced, and the output end of the comparator is connected with the control end of the data selector so as to facilitate the determination of the control end data of the corresponding data selector according to the parallel result data of the two data.
The type of the data selector is not limited, and may be a selector selected by N, or the number of the data selectors is not limited, so long as the output data of the register set of the next clock cycle can be determined when the current data to be ordered is run.
The input end of the data selector is respectively connected with the output end of the register set, the front stage data interface, the input signal interface and the enabling signal interface, and it is to be noted that signals corresponding to the input signal interface and the enabling signal interface are fixedly connected with 0 in the first stage parallel comparator unit. The data selector determines what value the next clock cycle register set updates to determine the ordering of the next data to be ordered. The register group is used for latching current data, wherein the current data is output data and parallel result data of a current clock cycle, so that data ordering of current data to be ordered in the current clock cycle is finished.
The embodiment of the invention provides a data sequencing circuit, which comprises a front data interface and parallel comparator units, wherein the number of the parallel comparator units is the same as that of data to be sequenced of the front data interface, and the parallel comparator units comprise comparators, data selectors and register groups; the first input end of the comparator is connected with the output end of the register set, the second input end of the comparator is connected with the front data interface, and the output end of the comparator is connected with the control end of the data selector; the input end of the data selector is respectively connected with the output end of the register group, the front stage data interface, the input signal interface and the enabling signal interface. The comparator is used for comparing the current data to be ordered with the stored data of the register group in parallel to obtain parallel result data, determining control end data of a corresponding data selector according to the parallel result data, determining output data of the register group of the next clock period according to the relation between signals of a corresponding input end and the control end data so as to be convenient for ordering of the next data to be ordered, and the register group is used for latching the output data and the parallel result data of the current clock period so as to be convenient for completing data ordering of the current data to be ordered in the current clock period. The circuit passes the ratio in each parallel comparator unit The comparator processes the current data to be ordered and the stored data in parallel to realize data parallel ordering and reduce ordering time, and meanwhile, the clock cycle of the current circuit is determined according to the data quantity of the ordered data, namely, the whole ordering time of n ordered data is n clock cycles, so that the time complexity breakthrough is realized to O (nlog) 2 n) shortens the complexity of the data ordering event to O (n), has simple circuit structure and shorter combinational logic path, and further shortens the cost of the data ordering time.
On the basis of the embodiment, since the data to be sequenced is sequenced, the number of the parallel comparator units is at least two, and the circuit structure for sequencing the data is formed by connecting at least two parallel comparator units in series. As an embodiment, the number of parallel comparator units is at least two, the input signal interface and the enable signal interface are fixed input signal interfaces and fixed enable signal interfaces in the data selector of the first-stage parallel comparator unit, and the input signal interfaces and the enable signal interfaces in the data selector of the other parallel comparator units are respectively connected with the output end of the register set of the last parallel comparator unit and the output end of the comparator of the last parallel comparator unit.
Specifically, the input signal interface and the enable signal interface are fixed input signal interfaces and fixed enable signal interfaces in the data selector of the first-stage parallel comparator unit, that is, the corresponding input signals and enable signals are fixedly connected to be 0. The input signal interface in the data selector of the other parallel comparator unit is connected with the output end of the register group of the last parallel comparator unit so as to facilitate updating data of the register group of the current clock cycle updated according to the last clock cycle as an input signal, and the enabling signal interface is connected with the output end of the comparator of the last parallel comparator unit so as to facilitate enabling signal according to the output data of the comparator.
The connection mode of the input signal interface and the enable signal interface in different parallel comparator units provided by the embodiment is convenient for comparing the current data to be sequenced and the circuit in the combinational logic is easy to run to a higher clock frequency, so that the expenditure of sequencing time is reduced.
Based on the above embodiment, when comparing the current data to be sorted, the selected data selector is not limited, the signal is input, the signal is enabled, and the data to be sorted is compared with the three data, and the data selector can be selected from one-out-of-three data, or can be combined in a mode of two data selectors. As one embodiment, the data selector includes a first data selector and a second data selector;
The first input end of the first data selector is connected with the output end of the register set, the second input end of the first data selector is connected with the front data interface, the output end of the first data selector is connected with the first input end of the second data selector, and the control end of the first data selector is connected with the output end of the comparator;
the second input end of the second data selector is connected with the input signal interface; the control terminal of the second data selector is connected with the enabling signal interface.
Specifically, fig. 2 is a block diagram of a parallel comparator unit according to an embodiment of the present invention, as shown in fig. 2, the data selector 4 includes a first data selector 8 and a second data selector 9, a first input terminal of the first data selector 8 (mux 0) is connected to an output terminal of the register set 5, a second input terminal of the first data selector 8 is connected to the front data interface 1 to receive data to be sorted, an output terminal is connected to a first input terminal of the second data selector 9 (mux 1), and a control terminal is connected to an output terminal of the comparator 3. A second input terminal of the second data selector 9 is connected to the input signal interface 6 and a control terminal is connected to the enable signal interface 7.0 is a first input port of the first data selector, 1 is a second input port of the first data selector, S is a control port of the first data selector, and the second data selector is the same. For example, the data is ordered from small to large, the data selector is composed of two data inputs, namely a first input port "0", a second input port "1" and a data-selected control port S. When s=1, the selector selects the "1" input output, and when s=0, the selector selects the "0" input output.
As shown in fig. 2, the output shift_en_o of the comparator (cmp) is connected to the control terminal (s terminal) of the first selector (mux 0), the data to be sorted (cmp_din_i) and the output terminal (dff output) of the register set are connected to the second input terminal ("1") and the first input terminal ("0") of the data input terminal of the first selector (mux 0), respectively, so that mux0 selects cmp_din_i output when shift_en_o=1, and mux0 selects dff output as output when shift_en_o=0.
The output terminal of the first selector (mux 0) is connected to the first input terminal (0 ") of the data input terminal of the second selector (mux 1), the input signal (shift_din_i) of the input signal interface is connected to the second input terminal (1") of the data input terminal of the second selector (mux 1), and the enable signal (shift_en_i) of the enable signal interface is connected to the control terminal (S terminal) of the data selection terminal of the second selector (mux 1). Mux1 selects the output of mux0 as output when shift_en_i=0, and mux1 selects shift_din_i as output when shift_en_i=1. The output of mux1 is connected to the input of dff. The output value of the next clock cycle of dff is determined by the input of dff.
It should be noted that, the combination logic of the data selector is set according to the data sorting, and the combination logic set according to the sorting from small to large of the data to be sorted is just one embodiment.
Fig. 3 is a schematic diagram of an N parallel data sorting circuit according to an embodiment of the present invention, as shown in fig. 3, one data sorting circuit includes N parallel comparator units 2 connected in series (unit 0-unit N), where an input signal interface 6 (shift_din_i)/an enable signal interface 7 (shift_en_i) in unit0 is tie0, and simultaneously accesses to-be-sorted data of a pre-stage data interface 1. The upper stage shift_dout_o/shift_en_o is connected to the shift_din_i/shift_en_i of the lower stage circuit, respectively, so as to complete data sorting.
The data selector provided by the embodiment of the invention comprises the connection relation corresponding to the first data selector and the second data selector and data output, is convenient for data sequencing, and realizes the specific value updated by the next clock period register set dff.
FIG. 4 is a flowchart of a method for sorting data according to an embodiment of the present invention, as shown in FIG. 4, the method is applied to a circuit for sorting data, the circuit includes a front-stage data interface and parallel comparator units, the number of the parallel comparator units is the same as the number of data to be sorted of the front-stage data interface, and the parallel comparator units include comparators, data selectors and register sets; the first input end of the comparator is connected with the output end of the register set, the second input end is connected with the front data interface, the output end is connected with the control end of the data selector, the input end of the data selector is respectively connected with the output end of the register set, the front data interface, the input signal interface and the enabling signal interface, and the comparator comprises:
S11: the control comparator compares the current data to be sequenced with the storage data of the register group in parallel to obtain parallel result data, and determines the control end data of the corresponding data selector according to the parallel result data;
s12: the control data selector determines output data of the register group of the next clock period according to the relation between the signal of the corresponding input end and the data of the control end so as to facilitate the sequencing of the next data to be sequenced;
s13: the control register set locks the output data and the parallel result data of the current clock cycle so as to finish the data ordering of the current data to be ordered in the current clock cycle.
Specifically, the comparator is mainly used for comparing the size of input data to be ordered and the size of the register group, and the parallel result data is obtained by parallel comparison of a plurality of comparators in the parallel comparator units in the current data to be ordered, wherein the parallel comparator units are arranged on all the data to be ordered. The data selector determines output data of a register set of a next clock cycle, the register set locking current output data and parallel result data of a current clock cycle.
The data sorting method provided by the embodiment of the invention is characterized in that a comparator is used for comparing current data to be sorted with stored data of a register group in parallel to obtain parallel result data, determining control end data of a corresponding data selector according to the parallel result data, and determining output data of the register group of the next clock cycle according to the relation between signals of a corresponding input end and the control end data so as to facilitate the next number to be sorted According to the ordering, the register group is used for latching the output data and the parallel result data of the current clock cycle so as to finish the data ordering of the current data to be ordered in the current clock cycle. The method processes the current data to be sequenced and the stored data in parallel by the comparators in each parallel comparator unit to realize the parallel sequencing of the data and reduce the sequencing time, and simultaneously determines the clock cycle of the current circuit according to the data quantity of the sequencing data, namely, the whole sequencing time of n sequencing data is n clock cycles, thereby realizing the breakthrough of the time complexity to O (nlog) 2 n) shortens the complexity of the data ordering event to O (n), has simple circuit structure and shorter combinational logic path, and further shortens the cost of the data ordering time.
On the basis of the above embodiment, when the data to be sorted is sorted from small to large, the control comparator in step S11 determines the control end data of the corresponding data selector according to the parallel result data, including:
the method comprises the steps that a comparator is controlled to obtain data to be ordered and stored data;
when the data to be ordered is smaller than the stored data, determining that the control end data of the corresponding data selector is 1;
when the data to be ordered is greater than or equal to the stored data, determining that the control end data of the corresponding data selector is 0.
It should be noted that, in the above embodiment, the storage data includes the data to be sorted of the inputted circuit, the threshold data after initialization, and the output data of the next cycle. Before parallel ordering, the circuit will set the initialization threshold of the register set to a maximum value, where the maximum value is determined based on the bit width of the register, e.g., 8 bits, and the maximum value is 255 to the power of 2.
When the data to be sorted (cmp_din_i) is smaller than the stored data (dff), the control end data (shift_en_o) of the data selector corresponding to the output of the comparator is 1, the data selector channel 1 is selected, and the data to be sorted (cmp_din_i) is transmitted into the data selector. Otherwise, the control end data is 0, and the data selector channel 0 is selected.
As an embodiment, the control data selector in step S12 determines output data of the register set of the next clock cycle according to a relation between the signal of the corresponding input terminal and the data of the control terminal, including:
the control data selector obtains control end data, an input signal of an input signal interface, an enable signal of an enable signal interface, data to be ordered and an output end signal of a register set;
when the enabling signal is 1, determining the output data of the next clock cycle as the input signal of the current data selector;
When the data of the control end is 0 and the enabling signal is 0, determining that the output data of the next clock period is the same as the output data of the current clock period;
when the data of the control end is 0 and the enabling signal is 1, determining the output data of the next clock period as the data to be sequenced.
Specifically, when the enable signal (shift_en_i) is 1, the value of the next clock cycle of the register set dff is updated to the input signal (shift_din_i) of the current data selector, which is the value of the unit register set dff of the previous stage. When the enable signal (shift_en_i) is 0 and the control side data (shift_en_o) is 0, the value of the next clock cycle of the register set dff remains unchanged. When the enable signal (shift_en_i) is 0 and the control side data (shift_en_o) is 1, the value of the next clock cycle of the register set dff is updated to the data to be ordered (cmp_din).
For example, taking 3, 10, 8, 6, 12 of these 5 data to be sorted as an example, the corresponding sorting table is shown in table 1:
TABLE 1 Circuit worksheet for ordering data
Figure BDA0004012498270000121
Figure BDA0004012498270000131
As shown in table 1, dff=xx represents the stored data of the current clock cycle, cmp represents the output shift_en_o=1 of cmp when cmp_din_i < dff output value is compared with cmp_din_i.
Taking unit0, unit1 as an example, describe the data comparison process: first clock cycle (1 clock) first data to be ordered cmp_din_i=3: unit0: dff=255; shift_en_i=0 (tie 0); shift_din_i=0 (tie 0); shift_en_o=1. The reasons are as follows:
3 (cmp_din_i) <255 (current clock cycle dff output value), i.e., the output of cmp is shift_en_o=1; shift_en_i=0 and shift_en_o=0, that is, after passing through two data selectors, cmp_din_i is input to the input terminal of the register set dff, that is, the output value for the second clock period dff becomes the value cmp_din_i (3) of the input terminal of dff.
unit1: dff=255; shift_en_i=1 (to unit0 shift_en_o); shift_din_i=255 (receiving the unit0 dff output value shift_dout_o); shift_en_o=1. The reason is the same as unit0 described above. shift_en_i=1, and shift_en_o=1 after passing through the two data selectors, the shift_din_i is input to the dff input terminal, that is, the output value becomes the second clock period dff becomes the value shift_din_i of the dff input terminal (255).
In the second clock cycle, the second data to be sorted cmp_din_i=10: unit0: dff=3; shift_en_i=0 (tie 0); shift_din_i=0 (tie 0); shift_en_o=0. That is, 10 (cmp_din_i) >3 (current dff output value) results in output shift_en_o=0 of cmp. After two data selectors, shift_en_i=0 and shift_en_o=0, the output value shift_dout_o of the register set dff is input to the dff input terminal, and the output value of the next clock cycle dff is unchanged.
Unit1: dff=255; shift_en_i=0 (to unit0 shift_en_o); shift_din_i=255 (receiving the unit0 dff output value shift_dout_o); shift_en_o=1. The reason is the same as unit0 described above. After two data selectors, shift_en_i=0 and shift_en_o=1, cmp_din_i is input to dff input, i.e., the output value at the third clock cycle dff becomes cmp_din_i (10).
And so on to complete the ordering of the 5 data to be ordered, through 5 blocks.
When it is to be noted that, in the whole sorting process, the unit-x dff value is not greater than the unit-x-N dff value all the time, as an embodiment, when the number of data to be sorted is multiple, the output data of the current register set in the current clock cycle is less than or equal to the output data of the subsequent register sets starting from the current register set.
When all the inputs of the data cmp_din_i to be ordered are finished, the data ordering is finished.
In this embodiment, according to the order of sorting from small to large, if the functions of the cmp comparator module of the circuit need to be adjusted, when cmp_din_i > dff is output, the cmp output value shift_en_o=1. In addition, before the ordering begins, all values of dff are initialized to a minimum value of 0. The present invention is not limited to this, and may be set according to actual conditions.
The small-to-large sorting process provided by the embodiment of the invention realizes the parallel sorting of data by parallel processing of the current data to be sorted and the stored data through the comparators in each parallel comparator unit, reduces the sorting time, and determines the clock cycle of the current circuit according to the data quantity of the sorted data, namely, the whole sorting time of n sorted data is n clock cycles, thereby realizing the breakthrough of time complexity to O (nlog) 2 n) bottleneck.
The invention further discloses a data sorting device corresponding to the method, which is applied to a data sorting circuit, wherein the circuit comprises a front data interface and parallel comparator units, the number of the parallel comparator units is the same as that of data to be sorted of the front data interface, and the parallel comparator units comprise comparators, data selectors and register groups; the first input end of the comparator is connected with the output end of the register set, the second input end of the comparator is connected with the front data interface, the output end of the comparator is connected with the control end of the data selector, the input end of the data selector is respectively connected with the output end of the register set, the front data interface, the input signal interface and the enabling signal interface, and fig. 5 is a structural diagram of a data sorting device provided by the embodiment of the invention. As shown in fig. 5, the data sorting apparatus includes:
The first control module 11 is used for controlling the comparator to compare the current data to be sequenced with the storage data of the register group in parallel to obtain parallel result data, and determining the control end data of the corresponding data selector according to the parallel result data;
the second control module 12 is configured to control the data selector to determine output data of the register set in a next clock cycle according to a relationship between the signal of the corresponding input terminal and the data of the control terminal so as to facilitate sorting of the next data to be sorted;
and the third control module 13 is used for controlling the register set to lock the output data and the parallel result data of the current clock cycle so as to finish the data ordering of the current data to be ordered in the current clock cycle.
Since the embodiments of the device portion correspond to the above embodiments, the embodiments of the device portion are described with reference to the embodiments of the method portion, and are not described herein.
For the description of the data sorting device provided by the present invention, please refer to the above method embodiment, the present invention is not repeated herein, and the method has the same beneficial effects as the above method for data sorting.
Fig. 6 is a block diagram of another apparatus for ordering data according to an embodiment of the present invention, as shown in fig. 6, where the apparatus includes:
A memory 21 for storing a computer program;
a processor 22 for implementing the steps of the method of data sorting when executing the computer program.
Processor 22 may include one or more processing cores, such as a 4-core processor, an 8-core processor, or the like, among others. The processor 22 may be implemented in hardware in at least one of a digital signal processor (Digital Signal Processor, DSP), a Field programmable gate array (Field-Programmable Gate Array, FPGA), a programmable logic array (Programmable Logic Array, PLA). The processor 22 may also include a main processor, which is a processor for processing data in an awake state, also referred to as a central processor (Central Processing Unit, CPU), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 22 may be integrated with an image processor (Graphics Processing Unit, GPU) for use in responsible for rendering and rendering of content required for display by the display screen. In some embodiments, the processor 22 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.
Memory 21 may include one or more computer-readable storage media, which may be non-transitory. Memory 21 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 21 is at least used for storing a computer program 211, which, when loaded and executed by the processor 22, is capable of implementing the relevant steps of the method for sorting data disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 21 may further include an operating system 212, data 213, and the like, and the storage manner may be transient storage or permanent storage. The operating system 212 may include Windows, unix, linux, among other things. The data 213 may include, but is not limited to, data related to a method of data ordering, and the like.
In some embodiments, the data sorting device may further include a display screen 23, an input/output interface 24, a communication interface 25, a power supply 26, and a communication bus 27.
Those skilled in the art will appreciate that the structure shown in fig. 6 does not constitute a limitation of the means for ordering data and may include more or less components than those shown.
The processor 22 implements the method of data ordering provided by any of the embodiments described above by invoking instructions stored in the memory 21.
For the description of the data sorting device provided by the present invention, please refer to the above method embodiment, the present invention is not repeated herein, and the method has the same beneficial effects as the above method for data sorting.
Further, the present invention also provides a computer readable storage medium having a computer program stored thereon, which when executed by the processor 22 performs the steps of a method of ordering data as described above.
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
For an introduction to a computer readable storage medium provided by the present invention, please refer to the above method embodiment, the present invention is not repeated herein, and the method has the same advantages as the above method for data sorting.
The method, the device and the medium for data sorting provided by the invention are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Claims (10)

1. A circuit for ordering data, wherein the circuit comprises a front data interface and parallel comparator units, the number of the parallel comparator units is the same as the number of data to be ordered of the front data interface, and the parallel comparator units comprise comparators, data selectors and register groups;
the first input end of the comparator is connected with the output end of the register set, the second input end of the comparator is connected with the front-stage data interface, and the output end of the comparator is connected with the control end of the data selector; the comparator is used for comparing the current data to be sequenced with the stored data of the register group in parallel to obtain parallel result data, and determining corresponding control end data of the data selector according to the parallel result data;
the input end of the data selector is respectively connected with the output end of the register set, the front-stage data interface, the input signal interface and the enabling signal interface, and the data selector is used for determining output data of the register set of the next clock period according to the relation between signals of the corresponding input end and data of the control end so as to facilitate sequencing of the data to be sequenced next; the register set is used for latching the output data and the parallel result data of the current clock cycle so as to finish the data sorting of the current data to be sorted in the current clock cycle.
2. A data sorting circuit as claimed in claim 1, characterized in that the number of parallel comparator units is at least two, the input signal interface and the enable signal interface being fixed input signal interfaces and fixed enable signal interfaces within the data selector of a first stage parallel comparator unit, the input signal interfaces and the enable signal interfaces within the data selector of the other parallel comparator unit being connected to the output of the register bank of a preceding parallel comparator unit and the output of the comparator of the preceding parallel comparator unit, respectively.
3. The data ordering circuit of claim 2, wherein the data selector includes a first data selector and a second data selector;
the first input end of the first data selector is connected with the output end of the register set, the second input end of the first data selector is connected with the front-stage data interface, the output end of the first data selector is connected with the first input end of the second data selector, and the control end of the first data selector is connected with the output end of the comparator;
A second input end of the second data selector is connected with the input signal interface; and the control end of the second data selector is connected with the enabling signal interface.
4. A method of data ordering, characterized in that it is applied to a circuit of data ordering, the circuit comprising a preceding data interface and parallel comparator units, the number of which is the same as the number of data to be ordered of the preceding data interface, the parallel comparator units comprising a comparator, a data selector and a register set; the first input end of the comparator is connected with the output end of the register set, the second input end is connected with the front stage data interface, the output end is connected with the control end of the data selector, the input end of the data selector is respectively connected with the output end of the register set, the front stage data interface, the input signal interface and the enabling signal interface, and the method comprises the following steps:
the comparator is controlled to compare the current data to be sequenced with the stored data of the register group in parallel to obtain parallel result data, and the control end data of the corresponding data selector is determined according to the parallel result data;
controlling the data selector to determine output data of the register group of the next clock period according to the relation between the signal of the corresponding input end and the data of the control end so as to facilitate the sequencing of the next data to be sequenced;
The control register set latches the output data and the parallel result data of the current clock cycle so as to finish the data sorting of the current data to be sorted in the current clock cycle.
5. The method of claim 4, wherein controlling the comparator to determine control side data of the corresponding data selector based on the parallel result data comprises:
controlling the comparator to acquire the data to be ordered and the stored data;
when the data to be ordered is smaller than the stored data, determining that the control end data of the corresponding data selector is 1;
and when the data to be ordered is larger than or equal to the stored data, determining that the control end data of the corresponding data selector is 0.
6. The method of claim 5, wherein said controlling the data selector to determine the output data of the register set for the next clock cycle based on the relationship of the signal at the corresponding input terminal and the data at the control terminal, comprises:
the data selector is controlled to acquire the control end data, the input signals of the input signal interface, the enable signals of the enable signal interface, the data to be ordered and the output end signals of the register group;
When the enabling signal is 1, determining output data of the next clock cycle as the input signal of the data selector currently;
when the control end data is 0 and the enabling signal is 0, determining that the output data of the next clock period is the same as the output data of the current clock period;
and when the control end data is 1 and the enabling signal is 0, determining the output data of the next clock period as the data to be sequenced.
7. A method according to claim 4 or 6, wherein when the data to be ordered is plural, the output data of the current register set in the current clock cycle is less than or equal to the output data of the subsequent register sets starting with the current register set.
8. A data sorting device, characterized in that it is applied to a data sorting circuit, the circuit includes a front-stage data interface and parallel comparator units, the number of the parallel comparator units is the same as the number of data to be sorted of the front-stage data interface, and the parallel comparator units include a comparator, a data selector and a register set; the first input end of the comparator is connected with the output end of the register set, the second input end is connected with the front stage data interface, the output end is connected with the control end of the data selector, the input end of the data selector is respectively connected with the output end of the register set, the front stage data interface, the input signal interface and the enabling signal interface, and the method comprises the following steps:
The first control module is used for controlling the comparator to compare the current data to be sequenced with the storage data of the register group in parallel to obtain parallel result data, and determining corresponding control end data of the data selector according to the parallel result data;
the second control module is used for controlling the data selector to determine output data of the register group of the next clock period according to the relation between the signal of the corresponding input end and the data of the control end so as to facilitate the ordering of the next data to be ordered;
and the third control module is used for controlling the register group to latch the output data and the parallel result data of the current clock cycle so as to finish the data ordering of the current data to be ordered in the current clock cycle.
9. An apparatus for ordering data, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the method of data sorting according to any of claims 4 to 7 when executing the computer program.
10. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the method of data sorting according to any of claims 4 to 7.
CN202211658286.3A 2022-12-22 2022-12-22 Circuit, method, device and medium for data sorting Pending CN116127894A (en)

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