CN116127881A - Data processing method for memory - Google Patents
Data processing method for memory Download PDFInfo
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- CN116127881A CN116127881A CN202310071699.XA CN202310071699A CN116127881A CN 116127881 A CN116127881 A CN 116127881A CN 202310071699 A CN202310071699 A CN 202310071699A CN 116127881 A CN116127881 A CN 116127881A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention relates to the technical field of integrated circuits, and discloses a data processing method for a memory, which comprises the steps of acquiring SET/CLR instructions; identifying an operational requirement of the SET/CLR instruction and corresponding operand content; and acquiring the value of the general register/special function register/memory according to the identified operand content, modifying the corresponding bit of the acquired value according to the operation requirement of the identified SET/CLR instruction, and finally writing the modified value back into the target space. Only one SET/CLR instruction is used, the address and bit to be modified can be directly designated, and the hardware automatically completes the read-write operation, thereby improving the execution efficiency.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a data processing method for a memory.
Background
In the current MCU system, in order to modify a certain bit of data in a register or a memory, a read instruction needs to be executed first, corresponding contents are read out from a target space, then a write instruction is executed after the modified instruction is executed, and finally corresponding data is written into the target space, so that a plurality of instructions and a plurality of cycles are required to complete the operation. However, in some cases, if it is required to modify the output level of an IO, modify a flag bit, modify a bit of a register, only one bit of the register needs to be modified quickly, and then multiple cycles of multiple instructions are still required, which affects the execution efficiency.
In order to simplify the operation process, some MCU designs may be used to facilitate bit operation in peripheral registers (such as IO registers), such as write 1 clear, write 1 set 1, etc., but extra design is needed here, which increases the complexity of CPU peripheral circuits.
Disclosure of Invention
The invention provides a data processing method for a memory, which can directly designate an address and a bit to be modified by using only one SET/CLR instruction, automatically complete read-write operation by hardware, and improve the execution efficiency, thereby solving the technical problems that the modification operation in the prior art needs to pass through a plurality of instruction periods to influence the execution efficiency and the like.
The invention can be realized by the following technical scheme:
a data processing method for a memory includes
Acquiring a SET/CLR instruction;
identifying an operational requirement of the SET/CLR instruction and corresponding operand content;
and acquiring the value of the general register/special function register/memory according to the identified operand content, modifying the corresponding bit of the acquired value according to the operation requirement of the identified SET/CLR instruction, and finally writing the modified value back into the target space.
Further, the method comprises three steps of value taking, decoding and executing, wherein
A value taking step: the instruction fetching unit fetches the SET/CLR instruction pointed by the current program counting register from the program memory and outputs the SET/CLR instruction to the decoding unit;
decoding: the decoding unit decodes the instruction output from the value unit according to the coding format and content of the instruction, wherein the SET/CLR operation code decoding unit identifies the SET/CLR instruction according to the operation code of the instruction, the operand decoding unit acquires operand content corresponding to the SET/CLR instruction according to the identification result of the operation code unit, determines an object (a register or a memory address needing to be operated) of the operation and a result (a bit needing to be modified) of the operation, and the decoding unit outputs the SET/CLR instruction operation code identification result and the operand identification result to the execution unit;
the method comprises the following steps: the execution unit operates according to the operation code identification result and the operand identification result output by the decoding unit, firstly the SET/CLR execution unit controls the read-write operation control unit to send read operation control, reads the content of a target address (a storage module), stores the read result in a read cache register, then the SET/CLR execution unit modifies the value in the read cache register according to the operand indication modification position obtained by decoding, and finally the modified value is written into the address corresponding to the target memory by the read-write control unit to complete modification of the data content of the corresponding address.
Further, the SET/CLR instruction is defined as
Further, it can be used for data processing of general or special host/memory.
The beneficial technical effects of the invention are as follows:
aiming at the characteristics of bit operation, the data processing method can specify an object to be operated and a bit to be operated through one instruction, namely a SET/CLR instruction, and then continuously execute complete required read-write operation by utilizing hardware, thereby improving the execution efficiency.
Drawings
FIG. 1 is a schematic overall flow chart of the present invention;
fig. 2 is a schematic view of the overall frame structure of the present invention.
Detailed Description
The following detailed description of the invention refers to the accompanying drawings and preferred embodiments.
As shown in fig. 1 and 2, the present invention provides a data processing method for a memory, including acquiring a SET/CLR instruction by a finger fetch unit; identifying the operation requirement of the SET/CLR instruction and the corresponding operand content through a decoding unit; the value of the general register/special function register/memory is acquired by the execution unit according to the identified operand content, the corresponding bit of the acquired value is modified according to the operation requirement of the identified SET/CLR instruction, and finally the modified value is written back into the target space. Therefore, only one SET/CLR instruction is used, and the read-write operation of the alignment can be completed in a shorter period, no additional peripheral logic is required to be designed independently, the operation efficiency can be effectively improved, the complexity of CPU peripheral is reduced, and the practicability is higher.
The method comprises the following steps:
definition of SET/CLR instructions
The instruction is to modify the value of a bit of a register or memory object.
The rectification operation flow comprises three steps of value taking, decoding and executing, wherein
A value taking step: the instruction fetching unit fetches the SET/CLR instruction pointed by the current program counting register from the program memory and outputs the SET/CLR instruction to the decoding unit;
decoding: the decoding unit decodes the SET/CLR instruction output from the value unit according to the coding format and content of the instruction, wherein the operation code decoding unit identifies the SET/CLR instruction according to the operation code of the instruction, the operand decoding unit acquires operand content corresponding to the SET/CLR instruction according to the identification result of the operation code decoding unit, determines an operation object, namely a register or a memory address needing to be operated and a bit needing to be modified as a result of the operation, and outputs the operation code identification result and the operand identification result of the SET/CLR instruction to the execution unit;
the method comprises the following steps: the execution unit operates according to the operation code identification result and the operand identification result output by the decoding unit, firstly, the execution unit controls the read-write operation control unit to send read operation control, reads the target address, namely the content of the storage module, stores the read result in the read cache register, then modifies the value in the read cache register according to the operand indication modification position obtained by decoding by the execution unit, and finally, writes the modified value into the address corresponding to the target memory by the read-write control unit to complete modification of the corresponding address data content.
The SET/CLR instruction of the above operation is used for operating the general purpose registers, only one cycle is required at this time, and is used for operating the special function registers and memories, which requires an additional read time of the special function registers or memories.
For example, the most significant bit of the value 0x0000FFFF of register address 0x00010080 needs to be modified to 1, which can be implemented using the SET [ R0], #31 instruction. Wherein the value of R0 needs to be configured to 0x00010080 prior to execution of the instruction. When the instruction is operated, the binary code of the instruction is obtained through the instruction taking unit; the SET/CLR operation code decoding unit of the decoding unit can identify the instruction as the SET/CLR instruction, and the operand decoding unit of the decoding unit can identify the related values of the general register R0 and the immediate # 31; the execution unit firstly reads the value 0x0000FFFF with the address of 0x00010080 from the memory, and stores the value 0x0000FFFF into the read cache register, then the SET/CLR execution unit modifies the highest value in the read cache register into 1, the result becomes 0x8000FFFF, finally the read-write control unit sends out write operation, and the result 0x8000FFFF is written into the address of the memory 0x00010080, so that the value modification process is realized.
In addition, the definition Rs, imm5 of the SET/CLR instruction can be easily generalized to processing systems with different bit widths. For example, for a 32-bit processing system, the immediate may be imm5, i.e., a 5-bit immediate, which may indicate a 32-bit position at most, and extend to higher or lower bit operating systems, simply by adjusting the indication range of the immediate.
The invention provides the instruction function of SET/CLR, which can operate on general registers and can also operate in an indirect addressing mode. For example, for general purpose register operations, the memory may be replaced with a general purpose register, and the operations at this time may be completed in one cycle since the general purpose register is read without additional latency. For other special function registers or memory operations, addresses that require operation may be specified using indirect addressing, where the operation requires additional latency due to the additional read time required for the special function registers or memory.
While particular embodiments of the present invention have been described above, it will be appreciated by those skilled in the art that these are merely illustrative, and that many changes and modifications may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims.
Claims (4)
1. A data processing method for a memory, characterized by: comprising
Acquiring a SET/CLR instruction;
identifying an operational requirement of the SET/CLR instruction and corresponding operand content;
and acquiring the value of the general register/special function register/memory according to the identified operand content, modifying the corresponding bit of the acquired value according to the operation requirement of the identified SET/CLR instruction, and finally writing the modified value back into the target space.
2. A data processing method for a memory according to claim 1, characterized in that: comprises three steps of value taking, decoding and executing, wherein
A value taking step: the instruction fetching unit fetches the SET/CLR instruction pointed by the current program counting register from the program memory and outputs the SET/CLR instruction to the decoding unit;
decoding: the decoding unit decodes the SET/CLR instruction output from the value unit according to the coding format and content of the instruction, wherein the SET/CLR operation code decoding unit identifies the SET/CLR instruction according to the operation code of the instruction, the operand decoding unit acquires operand content corresponding to the SET/CLR instruction according to the identification result of the operation code decoding unit, determines the object of the operation and the result of the operation, and outputs the operation code identification result and the operand identification result of the SET/CLR instruction to the execution unit;
the method comprises the following steps: the execution unit operates according to the operation code identification result and the operand identification result output by the decoding unit, firstly the execution unit controls the read-write operation control unit to send out read operation control, reads the content of a target address, stores the read result in the read cache register, then modifies the value in the read cache register according to the operand indication modification position obtained by decoding by the execution unit, and finally the modified value is written into the address corresponding to the target memory by the read-write control unit to complete modification of the data content of the corresponding address.
3. A data processing method for a memory according to claim 2, characterized in that: the SET/CLR instruction is defined as
4. A data processing method for a memory according to claim 1, characterized in that: can be used for data processing of general or special host/memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310071699.XA CN116127881A (en) | 2023-01-13 | 2023-01-13 | Data processing method for memory |
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| CN202310071699.XA CN116127881A (en) | 2023-01-13 | 2023-01-13 | Data processing method for memory |
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| CN116127881A true CN116127881A (en) | 2023-05-16 |
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