CN116127837A - Pixel circuit layout drawing method and device and related products - Google Patents
Pixel circuit layout drawing method and device and related products Download PDFInfo
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- CN116127837A CN116127837A CN202211673596.2A CN202211673596A CN116127837A CN 116127837 A CN116127837 A CN 116127837A CN 202211673596 A CN202211673596 A CN 202211673596A CN 116127837 A CN116127837 A CN 116127837A
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Abstract
The application discloses a pixel circuit layout drawing method, a pixel circuit layout drawing device and related products, wherein the method comprises the following steps: an index calculation step of judging whether the first pixel circuit layout is required to be used as a target pixel circuit layout to be optimized; the parameter adjustment step correspondingly adjusts the parameter of the layout graph according to the expected result index and the mapping relation of the parameter of the layout graph so as to correspondingly adjust the optimized layout characteristic of the parameter unit of the layout graph, so that the layout drawing is carried out on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout, and whether the second pixel circuit layout is required to be used as a new target pixel circuit layout to be optimized is judged; if yes, drawing the layout on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and executing an index calculation step to judge whether the new second pixel circuit layout needs to be optimized or not until the result index of the new second pixel circuit layout meets the design index.
Description
Technical Field
The application belongs to the technical field of circuit design, and particularly relates to a pixel circuit layout drawing method, a pixel circuit layout drawing device and related products.
Background
In the design of the pixel circuit layout, devices, connecting lines, layout figures and the like in the pixel circuit layout are required to be adjusted through multiple iterative designs so as to achieve all design targets. Since each iteration takes hours to days, the time-consuming cost of pixel circuit layout design is high.
Disclosure of Invention
The application provides a pixel circuit layout drawing method and device and related products, so as to overcome or alleviate the defects of the prior art.
A method of drawing a pixel circuit layout, comprising:
the index calculation step comprises the steps of calculating a result index of the created first pixel circuit layout, and comparing the result index with a design index to judge whether the first pixel circuit layout is required to be used as a target pixel circuit layout to be optimized;
parameter adjustment, namely responding to the requirement of re-optimizing the target pixel circuit layout, correspondingly adjusting the layout pattern parameter entry according to the expected result index and the mapping relation of the layout pattern entry so as to correspondingly adjust the optimized layout characteristics of the layout pattern parameter unit, and carrying out layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout, wherein each layout pattern on the first pixel circuit layout is abstracted into one layout pattern parameter unit;
jumping to an index calculation step to calculate a result index of the second pixel circuit layout, and comparing the result index with the design index to judge whether the second pixel circuit layout is required to be used as a new target pixel circuit layout to be optimized;
if yes, jumping to the parameter adjustment step to draw a layout on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and executing the index calculation step to judge whether the new second pixel circuit layout needs to be optimized or not until the result index of the new second pixel circuit layout meets the design index;
if not, the optimization of the second pixel circuit layout is ended.
A rendering apparatus of a pixel circuit layout, comprising:
the index calculation unit is used for calculating the result index of the created first pixel circuit layout and comparing the result index with the design index to judge whether the first pixel circuit layout is required to be used as a target pixel circuit layout to be optimized;
the parameter adjusting unit is used for responding to the requirement of re-optimizing the target pixel circuit layout, correspondingly adjusting the layout graph parameter according to the expected result index and the mapping relation of the layout graph parameter, correspondingly adjusting the optimized layout characteristics of the layout graph parameter unit, and carrying out layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout;
invoking the index calculation unit to calculate the result index of the second pixel circuit layout, and comparing the result index with the design index to judge whether the second pixel circuit layout is required to be used as a new target pixel circuit layout to be optimized;
if yes, calling the parameter adjusting unit to draw a new second pixel circuit layout on the basis of the new target pixel circuit layout, and executing the index calculating step to judge whether the new second pixel circuit layout needs to be optimized or not until the result index of the new second pixel circuit layout meets the design index;
if not, the optimization of the second pixel circuit layout is ended.
10. An electronic device comprising a memory for storing a computer executable program thereon and a processor for running the computer executable program to implement the method of any of claims 1-8.
According to the technical scheme, through an index calculation step, a result index of the created first pixel circuit layout is calculated and compared with a design index to judge whether the first pixel circuit layout is required to be used as a target pixel circuit layout to be optimized; parameter adjustment, namely responding to the requirement of re-optimizing the target pixel circuit layout, correspondingly adjusting the layout pattern parameter entry according to the expected result index and the mapping relation of the layout pattern entry so as to correspondingly adjust the optimized layout characteristics of the layout pattern parameter unit, and carrying out layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout, wherein each layout pattern on the first pixel circuit layout is abstracted into one layout pattern parameter unit; skipping to an index calculation step to calculate the result index of the second pixel circuit layout, and comparing the result index with the design index to judge whether the second pixel is required to be electrically connected
The road layout is used as a new target pixel circuit layout to be optimized; if yes, jumping to the parameter adjustment step to draw a new second pixel circuit layout on the basis of the 5 new target pixel circuit layout, and executing the new second pixel circuit layout
The index calculation step is used for judging whether the new second pixel circuit layout needs to be optimized or not until the result index of the new second pixel circuit layout meets the design index; if not, the optimization of the second pixel circuit layout is finished, so that the automatic iterative design of the pixel circuit layout design is realized, and the time-consuming cost is reduced.
Drawings
Fig. 1 is a flow chart of a drawing method of a pixel circuit layout according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a drawing device for a pixel circuit layout according to an embodiment of the present application.
Fig. 3A is a schematic 5 diagram of a result of applying the above technical solution of the embodiment of the present application to a first pixel circuit layout.
Fig. 3B is a partial schematic diagram of the result of applying the technical solution of the embodiment of the present application to a first pixel circuit layout.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application,
it will be apparent that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application are within the scope of the protection of the present application.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar pairs
Like, not to describe a particular order or sequence. It is to be understood that the data so used may be interchanged 5 where appropriate, so that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that "first
The objects identified by a "second" or the like are usually a class, and the number of the objects is not limited, for example, the first object may be one or a plurality of objects. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
Fig. 1 is a schematic flow chart of a drawing method of a pixel circuit layout according to an embodiment of the present application. As shown in fig. 1, it includes:
s101, calculating an index, namely calculating a result index of the created first pixel circuit layout, and comparing the result index with the design index to judge whether the first pixel circuit layout is required to be used as a target pixel circuit layout to be optimized;
in this embodiment, the index calculation step is performed by an index calculator, for example.
S102, parameter adjustment, namely performing re-optimization on the target pixel circuit layout, correspondingly adjusting the layout pattern parameter according to a mapping relation between an expected result index and the layout pattern parameter so as to correspondingly adjust the optimized layout characteristics of the layout pattern parameter unit, and performing layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout;
jumping to an index calculation step to calculate a result index of the second pixel circuit layout, and comparing the result index with the design index to judge whether the second pixel circuit layout is required to be used as a new target pixel circuit layout to be optimized;
if yes, jumping to the parameter adjustment step to draw a layout on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and executing the index calculation step to judge whether the new second pixel circuit layout needs to be optimized or not until the result index of the new second pixel circuit layout meets the design index;
if not, the optimization of the second pixel circuit layout is ended.
In this embodiment, the layout pattern parameter may be adjusted by a parameter generator.
Optionally, the method further comprises:
an parsing step comprising: analyzing the created original pixel circuit layout and determining the layout figure on the original pixel circuit layout;
an abstract step comprising: abstracting each layout figure into a layout figure parameterization unit, wherein each layout figure parameterization unit is provided with a corresponding layout figure parameter.
In the embodiment, considering the influence of the photosimulation of the pixel circuit, the influence of the process conditions on the device and the like, all layout elements on the pixel circuit layout are regarded as layout figures, so that each layout figure is abstracted into a layout figure parameterization unit, and the high-precision requirement of the pixel circuit design is met.
Each layout figure can be abstracted into a layout figure parameterization unit by parameterizing and programming the layout figure.
The layout pattern entries include, but are not limited to: device-related parameters such as, but not limited to, device electrical parameters, offset or offset angle of the device from a reference, device position parameters, device shape parameters, parameters of the patterns contained within the device; wiring related parameters including, but not limited to, minimum linewidth, maximum linewidth, minimum pitch, maximum pitch, different metal layer pitch, nested boundary distance between different metal layer patterns; pattern-related parameters including, but not limited to, position parameters, shape parameters, angle parameters, chamfer parameters, offset and angle relative to a reference object, and the like.
Optionally, the method further comprises:
the layout initial optimization step comprises the following steps: adjusting initial layout characteristics of the layout graphic parameter unit on the first pixel circuit layout;
and a parameter adjustment step, which comprises the steps of responding to the requirement of re-optimizing the target pixel circuit layout, correspondingly adjusting the input parameters of the layout graph by taking the initial layout characteristic as a reference according to the expected result index and the mapping relation of the input parameters of the layout graph, correspondingly adjusting the optimized layout characteristic of the layout graph parameter unit, and drawing the layout on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout.
Optionally, in the step of adjusting parameters, the initial layout feature is taken as a reference to further determine a direction of parameter adjustment according to the initial layout feature, so as to correspondingly adjust the layout pattern parameter.
By adjusting the initialized layout features, when the scheme of the embodiment of the application is executed, the initialized layout features are as close as possible to the optimized layout features, so that the processing time of layout optimization is shortened, the layout optimization is realized rapidly, and the result index is ensured to meet the requirements of design targets.
For example, if a capacitor is stretched laterally to be larger, the direction of parameter adjustment is: in the directions of larger capacitance value, larger lateral dimension of the capacitor and the like, otherwise, the search for small capacitance value is reduced.
Optionally, in the parameter adjustment step, based on an artificial intelligent model, the layout graph parameter is correspondingly adjusted according to a mapping relation between an expected result index and the layout graph parameter.
Optionally, the method further comprises:
generating model training samples in real time to train the artificial intelligence model in real time based on the training samples, the model training samples comprising: and the result index calculated in the index calculation step and the layout graph obtained in the parameter adjustment step are added into the parameters.
In the generation of model training samples, the most difficult link is to manually specify the input parameters of the layout graphic parameter unit. However, since there are a lot of input parameters, often more than 100, the parameter search space is very large. Generally, the layout pattern is commonly determined by n input parameters. Each of the layout pattern entries has a range of values located over a continuous domain. Assuming that m times of sampling are carried out in the value range when determining the entry of the layout graph, the complexity of the search space generated by the entry of the layout graph is m n . Even a relatively small module, such as a simple trigger, can have a number of parameters of up to tens or even hundreds. Assuming that there are only 50 samples, each of which is 1000 samples, then the search space also reaches 1000 50 . It is not possible nor necessary to search manually one by one in such a huge space to find a viable solution. Therefore, the method for generating the model training sample in real time automatically optimizes the entering parameters.
For example, a series of entries may also be automatically generated based on a model training sampler, forming automatically varying parameter value combinations, added to the training samples. Further, each time a value is randomly selected for each parameter to form an input parameter value list, and a result index list is correspondingly formed to form a training sample together.
If the artificial intelligent model is not used, drc and rc extraction, simulation, waveform drawing and index extraction are required to be carried out every time the parameter entering is manually modified in order to adjust the layout design, and the average time is 15 minutes.
By means of the method, the mapping relation between the result index and the layout graph parameter can be used for training the artificial intelligent model by collecting historical data and taking the historical data as training sample data, so that the artificial intelligent model has model parameters meeting requirements, and the result index can be rapidly determined by inputting the layout graph parameter when the scheme of the application is executed. Or based on the mode that the result index is closest to the design index, and based on the determined result index, determining the corresponding layout pattern entry according to the mapping relation.
The artificial intelligence model is generally implemented through a neural network, takes an input parameter as an input of the neural network, takes a result index as an output, and trains a large number of weights in the network. After training, the weight tends to be stable. The neural network at this time reflects the functional relationship between the input parameters and the result indicators reflected by the innumerable samples.
The collection history data may be collected offline or online. When the scheme of the embodiment of the application is about to be executed during online collection, the generated result index and the mapping relation of the input parameters of the layout graph are used as new historical data and added into training sample data.
Optionally, the method further comprises: a layout feature storage step, which comprises the step of storing the optimized layout features of the obtained second pixel circuit layout into a layout feature table;
and in the index calculation step, the optimized layout features are obtained from the layout feature table, so that the result index of the second pixel circuit layout is calculated according to the optimized layout features.
Target metrics include adherence to design rules. The design rules include: process geometry rules such as minimum linewidth, line spacing. The target metrics also include geometric and electrical performance metrics of the layout, such as peak voltage of the output signal, charge rate of key pixels within the driven pixel array, and the like.
A typical index calculation process comprises the steps of calculating whether a pixel circuit layout violates a geometric rule by a geometric rule checking tool, calculating parasitic resistance and capacitance by a parasitic resistance and capacitance calculating tool, generating a post-layout netlist with the parasitic resistance and capacitance, simulating the post-layout netlist by a simulation tool, generating an output signal waveform of a layout circuit, and extracting various characteristic data from the waveform by a waveform calculating tool to obtain an index. In general, all the result indexes must meet their respective expected value ranges (i.e., the requirements of the target indexes) at the same time, so as to prove that the pixel layout achieves the design target.
Optionally, the first pixel circuit layout and the second pixel circuit layout are both pixel circuit layouts. It is particularly useful for flat panel displays and the like.
Fig. 2 is a schematic structural diagram of a drawing device for a pixel circuit layout according to an embodiment of the present application. As shown in fig. 2, it includes:
an index calculation unit 201, configured to calculate a result index of the created first pixel circuit layout, and compare the result index with the design index to determine whether the first pixel circuit layout needs to be used as a target pixel circuit layout to be optimized;
a parameter adjustment unit 202, configured to correspondingly adjust the layout pattern parameter according to a mapping relationship between a desired result index and the layout pattern parameter in response to a re-optimization of the target pixel circuit layout, so as to correspondingly adjust an optimized layout feature of the layout pattern parameter unit, and perform layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout;
invoking the index calculation unit to calculate the result index of the second pixel circuit layout, and comparing the result index with the design index to judge whether the second pixel circuit layout is required to be used as a new target pixel circuit layout to be optimized;
if yes, calling the parameter adjusting unit to draw a new second pixel circuit layout on the basis of the new target pixel circuit layout, and executing the index calculating step to judge whether the new second pixel circuit layout needs to be optimized or not until the result index of the new second pixel circuit layout meets the design index;
if not, the optimization of the second pixel circuit layout is ended.
The present embodiments also provide a computer storage medium having stored thereon a computer executable program that is executed to implement any of the methods of the embodiments of the present application.
The embodiment of the application also provides an electronic device, which comprises a memory and a processor, wherein the memory is used for storing a computer executable program, and the processor is used for running the computer executable program to implement any one of the methods of the embodiment of the application.
The present embodiments also provide a computer program product having a computer executable program stored thereon, the computer executable program being executed to implement any of the methods of the embodiments of the present application.
Fig. 3A is a schematic diagram of a result of applying the technical solution of the embodiment of the present application to a first pixel circuit layout. As shown in fig. 3A, the TFT transistor aspect ratio was 9.14.
Fig. 3B is a partial schematic diagram of the result of applying the technical solution of the embodiment of the present application to a first pixel circuit layout. As in fig. 3B, the TFT aspect ratio after dragging is changed to 11.14.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.
Claims (10)
1. The pixel circuit layout drawing method is characterized by comprising the following steps of:
the index calculation step comprises the steps of calculating a result index of the created first pixel circuit layout, and comparing the result index with a design index to judge whether the first pixel circuit layout is required to be used as a target pixel circuit layout to be optimized;
parameter adjustment, namely responding to the requirement of re-optimizing the target pixel circuit layout, correspondingly adjusting the layout pattern parameter entry according to the expected result index and the mapping relation of the layout pattern entry so as to correspondingly adjust the optimized layout characteristics of the layout pattern parameter unit, and carrying out layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout, wherein each layout pattern on the first pixel circuit layout is abstracted into one layout pattern parameter unit;
jumping to an index calculation step to calculate a result index of the second pixel circuit layout, and comparing the result index with the design index to judge whether the second pixel circuit layout is required to be used as a new target pixel circuit layout to be optimized;
if yes, jumping to the parameter adjustment step to draw a layout on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and executing the index calculation step to judge whether the new second pixel circuit layout needs to be optimized or not until the result index of the new second pixel circuit layout meets the design index;
if not, the optimization of the second pixel circuit layout is ended.
2. The method of claim 1, wherein the method further comprises:
an parsing step comprising: analyzing the created original pixel circuit layout and determining the layout figure on the original pixel circuit layout;
an abstract step comprising: abstracting each layout figure into a layout figure parameterization unit, wherein each layout figure parameterization unit is provided with a corresponding layout figure parameter.
3. The method of claim 1, wherein the method further comprises:
the layout initial optimization step comprises the following steps: adjusting initial layout characteristics of the layout graphic parameter unit on the first pixel circuit layout;
and a parameter adjustment step, which comprises the steps of responding to the requirement of re-optimizing the target pixel circuit layout, correspondingly adjusting the input parameters of the layout graph by taking the initial layout characteristic as a reference according to the expected result index and the mapping relation of the input parameters of the layout graph, correspondingly adjusting the optimized layout characteristic of the layout graph parameter unit, and drawing the layout on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout.
4. A method according to claim 3, wherein in the parameter adjustment step, a direction of parameter adjustment is determined according to the initial layout feature, so as to correspondingly adjust the layout pattern.
5. The method according to claim 1, wherein in the parameter adjustment step, the layout pattern parameters are correspondingly adjusted according to a desired result index and a mapping relation of the layout pattern parameters based on an artificial intelligent model.
6. The method as in claim 5, further comprising:
generating model training samples in real time to train the artificial intelligence model in real time based on the training samples, the model training samples comprising: and the result index calculated in the index calculation step and the layout graph obtained in the parameter adjustment step are added into the parameters.
7. The method of claim 1, wherein the method further comprises: a layout feature storage step, which comprises the step of storing the optimized layout features of the obtained second pixel circuit layout into a layout feature table;
and in the index calculation step, the optimized layout features are obtained from the layout feature table, so that the result index of the second pixel circuit layout is calculated according to the optimized layout features.
8. The method according to claim 1, wherein in the index calculating step, a result index of the second pixel circuit layout is calculated from the generated layout netlist.
9. A drawing apparatus of a pixel circuit layout, comprising:
the index calculation unit is used for calculating the result index of the created first pixel circuit layout and comparing the result index with the design index to judge whether the first pixel circuit layout is required to be used as a target pixel circuit layout to be optimized;
the parameter adjusting unit is used for responding to the requirement of re-optimizing the target pixel circuit layout, correspondingly adjusting the layout graph parameter according to the expected result index and the mapping relation of the layout graph parameter, correspondingly adjusting the optimized layout characteristics of the layout graph parameter unit, and carrying out layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout;
invoking the index calculation unit to calculate the result index of the second pixel circuit layout, and comparing the result index with the design index to judge whether the second pixel circuit layout is required to be used as a new target pixel circuit layout to be optimized;
if yes, calling the parameter adjusting unit to draw a new second pixel circuit layout on the basis of the new target pixel circuit layout, and executing the index calculating step to judge whether the new second pixel circuit layout needs to be optimized or not until the result index of the new second pixel circuit layout meets the design index;
if not, the optimization of the second pixel circuit layout is ended.
10. An electronic device comprising a memory for storing a computer executable program thereon and a processor for running the computer executable program to implement the method of any of claims 1-8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211673596.2A CN116127837A (en) | 2022-12-26 | 2022-12-26 | Pixel circuit layout drawing method and device and related products |
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| CN202211673596.2A CN116127837A (en) | 2022-12-26 | 2022-12-26 | Pixel circuit layout drawing method and device and related products |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117332745A (en) * | 2023-11-22 | 2024-01-02 | 全芯智造技术有限公司 | Method, apparatus and medium for generating layout |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117332745A (en) * | 2023-11-22 | 2024-01-02 | 全芯智造技术有限公司 | Method, apparatus and medium for generating layout |
| CN117332745B (en) * | 2023-11-22 | 2024-02-13 | 全芯智造技术有限公司 | Method, apparatus and medium for generating layout |
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