CN116126771A - Communication system and method for two-wire SPI - Google Patents
Communication system and method for two-wire SPI Download PDFInfo
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- CN116126771A CN116126771A CN202310000677.4A CN202310000677A CN116126771A CN 116126771 A CN116126771 A CN 116126771A CN 202310000677 A CN202310000677 A CN 202310000677A CN 116126771 A CN116126771 A CN 116126771A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention belongs to the technical field of digital communication, and discloses a two-wire SPI communication system and method, wherein the two-wire SPI communication system comprises a master device and a slave device, the master device and the slave device both comprise a CPU (Central processing Unit), a bus, an SPI module and a GPIO module, the CPU is used for configuring an SPI register under the use scene of SPI, the SPI module is used for converting transmitted DATA into an SPI protocol and transmitting the SPI protocol through the GPIO module, SPI communication lines of the master device and the slave device consist of an SCK clock signal line and a DATA DATA signal line, and the SCK clock signal line is used for synchronizing a clock generated by the master device to the slave device; the DATA signal line is used for bi-directional transmission from master to slave and slave to master. The invention saves IO resources, and handshaking communication not only determines the transmission direction, but also ensures the effectiveness of data transmission.
Description
Technical Field
The invention belongs to the technical field of digital communication, and particularly relates to a two-wire SPI communication system and method.
Background
SPI (Serial Peripheral Interface) the serial peripheral interface is a high-speed full duplex communication bus proposed by motorola. The SPI protocol specifies four signal lines for data communication: (1) SCK clock signal line (2. MOSI master transmission data slave reception data signal line (3. MISO slave transmission data master reception data signal line (4. CS chip select signal line).
According to different transmission modes, the SPI can be configured into a full duplex mode, a half duplex mode, a receiving only mode and a transmitting only mode.
The polarity (at high level or low level) of the SCK signal in the SPI idle state can be selected according to the CPOL configuration; the clock edge (at the first clock edge or the second clock edge) of the SPI data sample may be selected according to the CPHA configuration. Taking full duplex mode with cpol=0 and spha=0 as an example, the MISO of the master device is connected to the MOSI of the slave device, the MOSI of the master device is connected to the MISO of the slave device, SCK is at low level in SPI idle state, the master device and the slave device sample data at the rising edge of SCK, and output data at the falling edge of SCK.
The standard SPI protocol requires a total of 4 IOs to enable communication of data. Under the limitation of part of application scenes and packaging, the number of IO needs to be reduced as much as possible. The reduction of the number of IOs is beneficial to reducing the area of the chip, thereby reducing the cost.
The patent application with publication number CN112559424a proposes a method for reducing the number of SPI IO. The scheme combines the MISO and the MOSI of the SPI into SDA through time division multiplexing for bidirectional transmission of data. The transmission mode is to complete the data output of MASTER and the data input of SLAVE or the data output of SLAVE and the data input of MASTER at the same time at the edge of SCK. This approach, while enabling bi-directional transmission over the data lines, is difficult to achieve with the data sent and sampled at the same clock edge. When SLAVE outputs, SCK generated by MASTER needs to be transmitted to SLAVE end for generating data, and then the data is transmitted back to MASTER end for sampling. This path may have a delay of about 40ns according to the process, and a large number of buffers need to be inserted at the CK end of the register used by the MASTER to sample the data in order to ensure that the data can be sampled correctly. The implementation mode not only increases the difficulty of time sequence constraint, but also increases the area of the chip due to a large number of buffers.
Disclosure of Invention
The invention aims to provide a two-wire SPI communication system and a two-wire SPI communication method, so as to solve the technical problems.
In order to solve the technical problems, the specific technical scheme of the two-wire SPI communication system and method provided by the invention is as follows:
the two-wire SPI communication system comprises a master device and a slave device, wherein the master device and the slave device both comprise a CPU, a bus, an SPI module and a GPIO module, the CPU is used for configuring an SPI register under the SPI use scene, the SPI module is used for converting transmitted DATA into an SPI protocol and transmitting the SPI protocol through the GPIO module, the SPI communication lines of the master device and the slave device consist of an SCK clock signal line and a DATA DATA signal line, and the SCK clock signal line is used for synchronizing a clock generated by the master device to the slave device; the DATA signal line is used for bi-directional transmission from master to slave and slave to master.
Further, the master device and the slave device communicate through handshake signals, wherein the handshake signals comprise request signals sent by the master device, read-write control signals sent by the master device and response signals sent by the slave device.
Further, the SCK signal during the master and slave handshakes is in a high or low state depending on the configuration of the CPOL.
Further, the handshake signals are generated by the driving of the SPI clk inside the SPI, the SPI clk is a clock inside the SPI and is derived from a system bus, the SPI clk of the master device and the SPI clk of the slave device are in the same frequency but are not synchronous, the handshake signal level width of the two-wire SPI is at least three SPI clk clock cycles, and the handshake signal level width is configured through software.
The invention also discloses a communication method of the two-wire SPI communication system, which comprises the following steps:
step 1: the master device sends out a high-level signal and a low-level signal after being enabled, and then sends out a read-write control signal, wherein the high level represents that the master device transmits to the slave device, the low level represents that the slave device transmits to the master device, and the DATA line is not driven after the master device sends out the read-write control signal, and the slave device waits for responding to the request;
step 2: the slave device always samples the change on the DATA line after being enabled, resamples the read-write control signal after sampling the jump of the high level and the low level, selects whether to receive the request of the master device according to the current state, and drives the DATA line to sequentially send a high level signal and a low level signal when the slave device can receive the request of the master device; when the slave device cannot accept the request of the master device, the slave device drives the DATA line to sequentially send a low-level signal and a high-level signal;
step 3: the master device judges whether the DATA transmission can be started or not according to the sampled response signals, and if the slave device can accept the DATA transmission, the DATA transmission can be started on the SCK clock signal line and the DATA DATA signal line immediately; if the slave device is not acceptable, the master device generates an error interrupt signal and waits for the CPU to process.
Further, the GPIO is a tri-state gate, the signals used on the GPIO include an output enable signal oe, a DATA output signal DATA out and a DATA input signal DATA in, the output enable signal oe is valid at a high level, the output enable signal oe is pulled down from the inside of the slave device after the slave device is enabled, the DATA output signal DATA out is continuously monitored for the signal on the DATA line, and the master device waits for sending a handshake signal and a read-write control signal; after the main equipment is enabled, the output enabling signal oe is pulled high, a handshake signal and a read-write control signal are started to be sent, the output enabling signal oe is pulled low immediately after the main equipment completes sending, and a response signal of the slave equipment is received; after the slave device recognizes the handshake signal and the read-write control signal, the slave device pulls the output enable signal oe high and sends a response signal.
Further, the two-wire SPI is used in a manner consistent with the standard SPI, and after the two-wire SPI is configured and enabled, software only needs to inquire the non-empty state bit of the sending FIFO and the non-full state bit of the receiving FIFO, and continuously writes data into the data register.
Further, the master device and the slave device communicate through handshake signals, the master device drives the DATA line to initiate a request to the slave device after enabling, the request signals are composed of a high level and a low level, the master device immediately sends read-write control signals after sending the request signals, the handshake signals have the level width of n spi clk clock periods, n is more than or equal to 3, the time point of sampling signals is the rising edge of the n-1 th spi clk, for the handshake signals on the DATA line, the slave device samples DATA on the DATA line on the second clock edge every time, the slave device immediately sends response signals after sampling the request signals to the master device, and the master device samples the response signals sent by the slave device on the second clock edge.
Further, the two-wire SPI is sent out by the master device to request signals and read-write control signals before each transmission start, and after the slave device responds correctly, the master device or the slave device transmits DATA by utilizing the SCK and the DATA wires.
The two-wire SPI communication system and the two-wire SPI communication method have the following advantages:
1. compared with the original SPI standard protocol, the two-line SPI mode only uses two IOs to realize the function of bidirectional transmission, and IO resources are saved.
2. The handshake communication both determines the transmission direction and ensures the validity of the data transmission.
3. In full duplex mode, the MISO path is a critical path limiting the SPI frequency, and the two-wire SPI effectively circumvents this problem.
Drawings
FIG. 1 is a schematic diagram of a master-slave device module structure of the present invention;
FIG. 2 is a schematic diagram of SPI master and slave connections of the present invention;
FIG. 3 is a flow chart of a two-wire SPI software configuration of the present invention;
FIG. 4 is a two-wire SPI handshake schematic of the present invention;
fig. 5 is a two-wire SPI data transmission diagram of the present invention.
Detailed Description
For a better understanding of the objects, structures and functions of the present invention, a two-wire SPI communication system and method according to the present invention will be described in further detail with reference to the accompanying drawings.
The invention provides a two-wire SPI communication system and a two-wire SPI communication method, which can reduce IO required by SPI. The signal lines used for the two-line SPI are: (1) SCK clock signal line (2) DATA data signal line. The SCK is a clock signal used for data transmission and is generated by the SPI master device; DATA is a DATA line supporting bi-directional transmissions from master to slave and slave to master.
In order to determine the transmission direction of SPI master-slave equipment and ensure that the master-slave equipment is in a state capable of transmitting, the invention introduces a master-slave equipment handshake mechanism. The process of handshaking is located before each data transmission. The handshake signals comprise a request signal sent by the master device, a read-write control signal sent by the master device and a response signal sent by the slave device. The SCK signal during the master and slave handshakes is in a high or low state depending on the configuration of the CPOL.
The handshake signals are driven by the SPI clk internal to the SPI, which is the clock internal to the SPI, typically from the system bus. Because SPI master-slave devices respectively belong to different systems, the SPI clk of the master device and the SPI slave device are synchronous at the same frequency. In order to ensure that master and slave devices can accurately sample handshake signals of the other party, the invention provides that the level width of two-wire SPI handshake signals is at least three SPI clk clock cycles. The handshake signal level width may be configured by software.
The specific handshake scheme is as follows:
the master device sends out a high-level signal and a low-level signal after being enabled, and then sends out a read-write control signal, wherein the high level represents the transmission of the master device to the slave device, and the low level represents the transmission of the slave device to the master device. After the master device sends out the read-write control signal, the DATA line is not driven any more, and the slave device waits for responding to the request.
The slave device always samples the change on the DATA line after being enabled, and resamples the read-write control signal after sampling the jump to the high-low level, and the slave device can select whether to accept the request of the master device according to the current state. The slave drives the DATA line to send a high signal followed by a low signal when the slave can accept the master's request. When the slave device cannot accept the request of the master device, the slave device drives the DATA line to transmit the low level signal and the high level signal sequentially.
The master device judges whether the DATA transmission can be started or not according to the sampled response signals, and if the slave device can accept the DATA transmission, the DATA transmission can be started on the SCK clock signal line and the DATA DATA signal line. If the slave is not acceptable, the master may generate an error interrupt signal waiting for the CPU to process.
FIG. 1 is a frame diagram of a master-slave device system in which SPI is located, including a CPU, a bus, an SPI module, a GPIO module, and other peripherals on the system. Under the use scene of SPI, CPU is mainly used for the configuration of SPI register, and SPI module is used for converting the data that send into SPI's protocol and sends through GPIO module.
As shown in fig. 2, the behavior of the GPIO module may be abstracted into a tri-state gate. The signals used on the GPIO module are output enable signals oe (active high), data output signals data out and data input signals data in. According to the two-wire SPI configuration flow shown in fig. 3, after the slave device is enabled, the slave device outputs the enable signal oe low, and the DATA output signal DATA out continuously monitors the signal on the DATA line, and waits for the master device to send the handshake signal and the read/write control signal. After the master device is enabled, the output enabling signal oe is pulled high, and a handshake signal and a read-write control signal are started to be sent. The master device immediately pulls down an output enabling signal oe after the transmission is completed, and receives a response signal of the slave device; after the slave device recognizes the handshake signal and the read-write control signal, the slave device pulls the oe signal high and sends a response signal.
Fig. 3 is a flowchart of SPI software configuration. The use mode of the two-wire SPI is consistent with that of the standard SPI, and after the two-wire SPI is configured and enabled, software only needs to inquire the non-empty state bit of the sending FIFO and the non-full state bit of the receiving FIFO, and data is continuously written into the data register. Compared to a standard SPI, a two-wire SPI may have a handshake failure due to the following reasons: (1) the master requests to receive data from the slave, the slave's transmit FIFO is empty, no data can be transmitted, and the slave sends a handshake failure signal. (2) The master device sends data, requests the slave device to receive, the slave device receiving FIFO is full, cannot receive data, and the slave device sends a handshake failure signal.
Fig. 4 is an example of an SPI successful handshake. Assume that the Clock Phase (CPHA) is 0, the IDLE state and SCK remain low for the handshake period. Shown is the handshake process with a handshake signal level width of 3 spiclk clock cycles. The master device drives the DATA line to initiate a request to the slave device after being enabled, the request signal being composed of a high level and a low level; the master device immediately transmits a read-write control signal after the request signal is transmitted. In order to ensure that the slave device cannot sample the wrong request signal and read-write control signal due to metastable state, the invention provides that if the level width of a handshake signal is n spi clk clock cycles, n is more than or equal to 3, the time point of the sampling signal is the rising edge of the n-1 th spi clk. Taking the handshake signal as an example of a three spiclk clock cycle length, for the handshake signal on the DATA line, the slave samples the DATA on the DATA line at the second clock edge at a time (at the 2 nd, 5 th, 8 th dashed lines in fig. 4). The slave device immediately transmits a response signal after sampling the request signal to the master device. The master device samples the response signal sent by the slave device, and also samples the response signal at the second clock edge.
Fig. 5 is a process of two-wire SPI completing handshake and transmitting data. The two-wire SPI needs to send a request signal and a read-write control signal by the master device before each transmission start, and after the slave device responds correctly, the master device or the slave device can transmit DATA by using the SCK and the DATA wires.
It will be understood that the invention has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (9)
1. The two-wire SPI communication system comprises a master device and a slave device, wherein the master device and the slave device both comprise a CPU, a bus, an SPI module and a GPIO module, the CPU is used for configuring an SPI register under the use scene of SPI, and the SPI module is used for converting transmitted DATA into an SPI protocol and transmitting the SPI protocol through the GPIO module; the DATA signal line is used for bi-directional transmission from master to slave and slave to master.
2. The two-wire SPI communication system of claim 1 wherein the master device and slave device communicate via handshake signals including a request signal sent by the master device, a read-write control signal sent by the master device, and a reply signal sent by the slave device.
3. A two-wire SPI communication system according to claim 2, characterized in that the SCK signal during the master and slave handshakes is in a high or low state depending on the configuration of the CPOL.
4. A two-wire SPI communication system according to claim 2, wherein the handshake signals are driven by a SPI clk internal to the SPI, the SPI clk being an internal clock from the system bus, the SPI clk of the master and slave devices being co-frequency but not synchronized, the handshake signal level width of the two-wire SPI being at least three SPI clk clock cycles, the handshake signal level width being configured by software.
5. A method of communicating a two-wire SPI communication system according to any of claims 1-4, comprising the steps of:
step 1: the master device sends out a high-level signal and a low-level signal after being enabled, and then sends out a read-write control signal, wherein the high level represents that the master device transmits to the slave device, the low level represents that the slave device transmits to the master device, and the DATA line is not driven after the master device sends out the read-write control signal, and the slave device waits for responding to the request;
step 2: the slave device always samples the change on the DATA line after being enabled, resamples the read-write control signal after sampling the jump of the high level and the low level, selects whether to receive the request of the master device according to the current state, and drives the DATA line to sequentially send a high level signal and a low level signal when the slave device can receive the request of the master device; when the slave device cannot accept the request of the master device, the slave device drives the DATA line to sequentially send a low-level signal and a high-level signal;
step 3: the master device judges whether the DATA transmission can be started or not according to the sampled response signals, and if the slave device can accept the DATA transmission, the DATA transmission can be started on the SCK clock signal line and the DATA DATA signal line immediately; if the slave device is not acceptable, the master device generates an error interrupt signal and waits for the CPU to process.
6. The communication method according to claim 5, wherein the GPIO is a tri-state gate, the signals used on the GPIO include an output enable signal oe, a DATA output signal DATA out and a DATA input signal DATA in, the output enable signal oe is valid at a high level, the output enable signal oe is pulled low from the inside of the slave device after the slave device is enabled, the signal on the DATA line is continuously monitored on the DATA output signal DATA out, and the master device waits for sending a handshake signal and a read-write control signal; after the main equipment is enabled, the output enabling signal oe is pulled high, a handshake signal and a read-write control signal are started to be sent, the output enabling signal oe is pulled low immediately after the main equipment completes sending, and a response signal of the slave equipment is received; after the slave device recognizes the handshake signal and the read-write control signal, the slave device pulls the output enable signal oe high and sends a response signal.
7. The communication method of claim 5, wherein the two-wire SPI is used in a manner consistent with a standard SPI, and after the two-wire SPI configuration is completed and enabled, software only needs to query a transmit FIFO non-empty status bit and a receive FIFO non-full status bit, and continue writing data into the data register.
8. The communication method according to claim 5, wherein the master device and the slave device communicate via handshake signals, the master device drives the DATA line to initiate a request to the slave device after being enabled, the request signals are composed of a high level and a low level, the master device immediately sends a read/write control signal after the request signals are sent, the handshake signals have a level width of n spi clk clock periods, n is equal to or greater than 3, the time point of the sampling signals is the rising edge of the n-1 th spi clk, for the handshake signals on the DATA line, the slave device samples DATA on the DATA line at every second clock edge, the slave device immediately sends a response signal after sampling the request signal of the master device, and the master device samples the response signal sent by the slave device at the second clock edge.
9. The communication method of claim 5, wherein the two-wire SPI is sent by the master device with a request signal and a read/write control signal before each transmission is started, and the master device or the slave device transmits DATA using SCK and DATA lines after the slave device responds correctly.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117251403A (en) * | 2023-11-08 | 2023-12-19 | 北京紫光芯能科技有限公司 | Communication mode configuration method and device of SPI protocol master-slave equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117251403A (en) * | 2023-11-08 | 2023-12-19 | 北京紫光芯能科技有限公司 | Communication mode configuration method and device of SPI protocol master-slave equipment |
| CN117251403B (en) * | 2023-11-08 | 2024-05-14 | 北京紫光芯能科技有限公司 | Communication mode configuration method and device of SPI protocol master-slave equipment |
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