CN116110881A - Metal interconnection structure of integrated circuit - Google Patents

Abstract

The invention relates to a metal interconnection structure of an integrated circuit. Comprising the following steps: the first metal layer comprises a base part and a connecting part which are connected with each other, the connecting part comprises a first end part which is contacted with the base part, the base part comprises a second end part which is contacted with the connecting part, and the line width of the first end part is smaller than that of the second end part; the second metal layer and the first metal layer are arranged at intervals in the thickness direction of the integrated circuit; a conductive via for connecting the first metal layer and the second metal layer; the conductive through hole comprises a first conductive end and a second conductive end which are opposite to each other, the first conductive end is contacted with the connecting part of the first metal layer, and the second conductive end is contacted with the second metal layer; the dummy conductive via is positioned between the conductive via and the base and comprises a third conductive end and a fourth conductive end which are opposite, and the third conductive end is contacted with the connecting part. The metal interconnection structure of the integrated circuit provided by the invention can improve the reliability of the integrated circuit.

Description

Metal interconnection structure of integrated circuit

Technical Field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a metal interconnection structure of an integrated circuit.

Background

In the field of integrated circuit manufacturing, the back-end metal interconnection lines are all formed by mutually communicating each layer of metal line through holes so as to realize external control of devices. As shown in fig. 1 and 2, the rear metal is an upper metal layer 11, and is electrically connected to a lower metal layer 13 through a via hole 12. However, during fabrication, different materials are typically used to form multiple interfaces, particularly where stress migration occurs at the via connections. Stress migration is a physical phenomenon that stress gradients are formed between different parts of metal connecting lines due to the fact that thermal expansion coefficients of a multi-layer metal interconnection structure and surrounding medium materials are different at a certain temperature, and crystal lattice vacancies 14 in the metal are collected to a place where stress is concentrated under the action of stress, so that cavities are formed in the metal. When the void formed by stress migration reaches a certain degree, the metal interconnection line can be opened, and related devices are disabled. Stress migration is a significant cause of integrated circuit failure.

Disclosure of Invention

In view of the foregoing, embodiments of the present application provide a metal interconnection structure of an integrated circuit to solve at least one of the problems in the background art.

In order to achieve the above purpose, the technical scheme of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a metal interconnection structure of an integrated circuit, including:

a first metal layer including a base portion and a connection portion connected to each other, the connection portion including a first end portion in contact with the base portion, the base portion including a second end portion in contact with the connection portion, a line width of the first end portion being smaller than a line width of the second end portion;

the second metal layer and the first metal layer are arranged at intervals in the thickness direction of the integrated circuit;

a conductive via for connecting the first metal layer and the second metal layer; the conductive through hole comprises a first conductive end and a second conductive end which are opposite to each other, the first conductive end is in contact with the connecting part of the first metal layer, and the second conductive end is in contact with the second metal layer;

and the dummy conductive through hole is positioned between the conductive through hole and the base part and comprises a third conductive end and a fourth conductive end which are opposite, and the third conductive end is in contact with the connecting part.

Optionally, the connecting portion includes:

the first channel region, the relay region and the second channel region are sequentially arranged along the direction away from the base, wherein the line width of the relay region is larger than that of the first channel region and that of the second channel region, the third conductive end of the pseudo conductive through hole is in contact with the relay region, and the first conductive end of the conductive through hole is in contact with the second channel region.

Optionally, the distance of the relay area from the conductive via is less than the distance of the relay area from the base.

Alternatively, both ends of the relay region in a direction perpendicular to the direction from the base to the conductive via protrude from both sides of the first channel region and the second channel region.

Optionally, two parts of the relay area protruding from two sides of the first channel area and the second channel area are a first convex part and a second convex part; the first convex part and the second convex part are symmetrically arranged, and the first convex part and the second convex part are contacted with at least one pseudo conductive through hole.

Optionally, the number of the dummy conductive vias is at least two, and at least two of the dummy conductive vias are arranged in a direction perpendicular to the direction from the base to the conductive vias.

Optionally, the dummy conductive vias include at least a first dummy conductive via, a second dummy conductive via, and a third dummy conductive via; the first and third dummy conductive vias are in contact with the first and second protrusions, respectively, and the second dummy conductive via is in contact with a relay section portion located between the first and second protrusions.

Optionally, the line width of the first channel region is greater than the line width of the second channel region.

Optionally, the cross-sectional area of the dummy conductive via and the cross-sectional area of the conductive via are the same.

Optionally, the metal interconnection structure further includes:

and the fourth conductive end of the dummy conductive through hole is contacted with the third metal layer.

The metal interconnection structure of the integrated circuit provided by the embodiment of the application comprises: a first metal layer including a base portion and a connection portion connected to each other, the connection portion including a first end portion in contact with the base portion, the base portion including a second end portion in contact with the connection portion, a line width of the first end portion being smaller than a line width of the second end portion; the second metal layer and the first metal layer are arranged at intervals in the thickness direction of the integrated circuit; a conductive via for connecting the first metal layer and the second metal layer; the conductive through hole comprises a first conductive end and a second conductive end which are opposite to each other, the first conductive end is in contact with the connecting part of the first metal layer, and the second conductive end is in contact with the second metal layer; and the dummy conductive through hole is positioned between the conductive through hole and the base part and comprises a third conductive end and a fourth conductive end which are opposite, and the third conductive end is in contact with the connecting part. Wherein the connecting portion of the first metal layer can limit movement of crystal lattice vacancies to the conductive through hole, thereby improving the condition of voids at the conductive through hole. And the dummy conductive through hole positioned at the connecting part can attract the vacancy to move to the dummy conductive through hole, so that the condition of the cavity at the conductive through hole is further improved. Therefore, the metal interconnection structure of the integrated circuit provided by the embodiment of the application can improve the condition of the cavity at the conductive through hole and improve the reliability of the integrated circuit.

Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 is a schematic diagram of a prior art metal interconnect structure of an integrated circuit;

FIG. 2 is a schematic diagram of the top view of FIG. 1;

FIG. 3 is a schematic diagram of a metal interconnection structure of an integrated circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of the top view of FIG. 3;

fig. 5 is a schematic illustration of the movement of the vacancies in fig. 4.

Reference numerals illustrate:

the prior art comprises the following steps: 11. a metal layer is arranged on the upper surface; 12. a through hole; 13. a lower metal layer; 14. lattice vacancies;

the application comprises the following steps: 30. a first metal layer; 31. a base; 32. a connection part; 321. a first channel region; 322. a relay zone; 323. a second channel region; 40. a second metal layer; 50. a conductive via; 60. a dummy conductive via; 70. a vacancy; 80. and a third metal layer.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the application; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present application.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical aspects of the present application. Preferred embodiments of the present application are described in detail below, however, the present application may have other implementations in addition to these detailed descriptions.

To solve the technical problems in the prior art, the embodiment of the present application provides a metal interconnection structure of an integrated circuit, as shown in fig. 3 and fig. 4, where the metal interconnection structure of the integrated circuit includes a first metal layer 30, a second metal layer 40, a conductive via 50 and a dummy conductive via 60.

The first metal layer 30 includes a base 31 and a connection portion 32 connected to each other, the connection portion 32 including a first end portion in contact with the base 31, the base 31 including a second end portion in contact with the connection portion 32, a line width of the first end portion being smaller than a line width of the second end portion;

the second metal layer 40 and the first metal layer 30 are disposed at intervals in the thickness direction of the integrated circuit;

the conductive via 50 is used to connect the first metal layer 30 and the second metal layer 40; the conductive via 50 includes opposite first and second conductive ends, the first conductive end being in contact with the connection portion 32 of the first metal layer 30 and the second conductive end being in contact with the second metal layer 40;

the dummy conductive via 60 is located between the conductive via 50 and the base 31 and includes third and fourth opposite conductive ends, the third conductive end being in contact with the connection portion 32.

Wherein the first metal layer 30 includes a base portion 31 and a connection portion 32 connected to each other, and the line width of the first end portion is smaller than the line width of the second end portion. In this way, the line width becomes narrower from the base 31 to the connecting portion 32 at the portion where the base 31 and the connecting portion 32 are connected, so that movement of crystal lattice vacancies 70 (hereinafter referred to as vacancies) from the base 31 to the connecting portion 32 can be restricted. That is, movement of the void 70 to the conductive via 50 can be restricted, the concentration of the void 70 at the conductive via 50 can be reduced, and the condition of the void at the conductive via 50 can be improved.

It will be appreciated that the thickness direction of the integrated circuit may also be referred to as the up-down direction of the integrated circuit. The conductive via 50 is used to connect the first metal layer 30 and the second metal layer 40, that is, to conductively connect the first metal layer 30 and the second metal layer 40, which are located at upper and lower positions, respectively.

The dummy conductive via 60 may attract a portion of the vacancies 70 moving from the first metal layer 30 to the conductive via 50, disperse the distribution of vacancies 70, reduce the concentration of vacancies 70 at the conductive via 50, and improve the cavitation at the conductive via 50, thereby protecting the conductive via 50.

In some embodiments, the cross-sectional area of the dummy conductive via 60 and the cross-sectional area of the conductive via 50 are the same. Thus, the manufacturing process of the integrated circuit is facilitated. As can be appreciated, since the dummy conductive via 60 is extended in the thickness direction (up-down direction) of the integrated circuit as is the conductive via 50. Thus, the cross-section may be a cross-section parallel to the horizontal plane. It will be appreciated that the cross-sectional areas may be the same shape and size.

Thus, the structure, size, material, fabrication process, etc. of the dummy conductive via 60 may be the same as the conductive via 50, except that the fourth conductive end of the dummy conductive via 60 is not connected to the second metal layer 40. In this way, the fabrication process of the integrated circuit is simpler.

In this embodiment, the conductive via 50 and the dummy conductive via 60 are perpendicular to the first metal layer 30, and the conductive via 50 is perpendicular to the second metal layer 40. In this way, the first metal layer 30 and the second metal layer 40 are disposed in parallel, which facilitates the fabrication of the conductive via 50 and the dummy conductive via 60.

From tests it was confirmed that within a certain number range, the greater the number of dummy conductive vias 60, the greater the total number of attractive voids 70, and the lower the concentration of voids 70 at the conductive vias 50. The number of the dummy conductive vias 60 is set to be at least two. And, at least two of the dummy conductive vias 60 are arranged in a direction perpendicular to the direction from the base 31 to the conductive vias 50. I.e. perpendicular to the direction of extension of the connection portion 32, instead of being distributed in the direction of extension of the connection portion 32. In this way, the dummy conductive via 60 is disposed so as not to increase the resistance between the first metal layer 30 and the conductive via 50 much.

In some embodiments, the connection portion 32 includes:

a first channel region 321, a relay region 322, and a second channel region 323 sequentially arranged in a direction away from the base 31, wherein a line width of the relay region 322 is greater than a line width of the first channel region 321 and the second channel region 323, a third conductive end of the dummy conductive via 60 is in contact with the relay region 322, and a first conductive end of the conductive via 50 is in contact with the second channel region 323. In this embodiment, the line width of the first channel region 321 is denoted as W1 in the drawing, the line width of the relay region 322 is denoted as W2 in the drawing, and the line width of the second channel region 323 is denoted as W3 in the drawing. From the above, W2> W1 and W2> W3.

Note that the relay region 322 is used to arrange more dummy conductive vias 60 to increase the number of attracting voids 70. In this embodiment, the extending direction of the first channel region 321 and the second channel region 323 may be the same as the extending direction of the entire connection portion 32, and the extending direction of the relay region 322 may be different from the extending direction of the first channel region 321 or the second channel region 323 to accommodate more dummy conductive vias 60.

It will be appreciated that the first channel region 321 and the second channel region 323 may be an integral channel region interrupted by a relay region 322, forming the first channel region 321 and the second channel region 323 spaced apart from each other. Thus, in some embodiments, the extension direction and line width of the first channel region 321 and the second channel region 323 are the same. For convenience of description, it is assumed in the following description that the extending directions and line widths of the first and second channel regions 321 and 323 are the same. It will be appreciated that the direction of extension and line width of the two may also be different. In the case where the two are different, if the later-described part or structure needs to be based on the positions of the first passage area 321 and the second passage area 323, it may be an optional one if not described.

In some embodiments, the distance of the relay area 322 from the conductive via 50 is less than the distance of the relay area 322 from the base 31. It has been found from testing that, over a range of distances, the distance of the relay region 322 from the conductive via 50 is less than the distance of the relay region 322 from the base 31, thereby further reducing the concentration of voids 70 at the conductive via 50. The dummy conductive via 60 and the conductive via 50 must be spaced apart from each other by a predetermined distance. So that the voids 70 attracted to the dummy conductive vias 60 do not become voids 70 at the conductive vias 50.

In some embodiments, both ends of the relay region 322 in a direction perpendicular to the direction from the base 31 to the conductive via 50 protrude from both sides of the first channel region 321 and the second channel region 323. In this way, the dummy conductive vias 60 are distributed on both sides of the first channel region 321 and the second channel region 323, so that the distribution of paths of the dummy conductive vias 60 attracting the voids 70 is more reasonable, and the voids 70 move more smoothly.

Specifically, two portions of the relay area 322 protruding from both sides of the first channel area and the second channel area are a first convex portion and a second convex portion:

the first protruding portion and the second protruding portion are symmetrically disposed with respect to each other, and the first protruding portion and the second protruding portion are both in contact with at least one dummy conductive via 60.

The dummy conductive vias 60 on both sides of the first and second channel regions 321 and 323 can be more uniformly distributed by being symmetrically disposed with each other. The path distribution of the dummy conductive vias 60 attracting the voids 70 is more reasonable and the voids 70 move more smoothly, thereby maximizing the ability of the dummy conductive vias 60 to attract the voids 70. It will be appreciated that the axis of symmetry may be the center line of the first channel region 321 and the second channel region 323. If the first and second channel regions 321 and 323 are rectangular in shape, the center line is the symmetry axis of the rectangle. If other regular shapes, there may be a corresponding line that makes both sides axisymmetric. If irregularly shaped, may be a line approximating the central axis.

In some embodiments, the number of the dummy conductive vias 60 is at least two, and at least two of the dummy conductive vias 60 are arranged in a direction perpendicular to the direction from the base 31 to the conductive vias 50.

Specifically, the dummy conductive via 60 includes at least a first dummy conductive via, a second dummy conductive via, and a third dummy conductive via; the first and third dummy conductive vias are in contact with the first and second protrusions, respectively, and the second dummy conductive via is in contact with a relay section portion located between the first and second protrusions.

It is understood that the dummy conductive via 60 located between the first protrusion and the second protrusion may be located in the extending direction of the first channel region 321 and the second channel region 323, or may be on the center line of the first channel region 321 and the second channel region 323. In this way, the dummy conductive via 60 is substantially opposite the void 70 moving over the first channel region 321 and the second channel region 323, facilitating the attraction of more voids 70.

In some embodiments, the line width of the first channel region 321 is greater than the line width of the second channel region 323. In this way, the path of the velocity of movement of the void 70 toward the relay zone 322 is wider and the movement is smoother, while the path of movement of the void 70 from the relay zone 322 toward the conductive via 50 is relatively narrower, which is advantageous for protecting the conductive via 50. Namely, in this embodiment, W1> W3.

In some embodiments, the relay zone 322 has:

a first width, which is a line width of the relay region 322;

and a second width in a direction from the base 31 to the conductive via 50;

the second width is greater than the line widths of the first and second channel regions 321 and 323.

As described above, the line width of the relay area 322 is W2. In addition, in the present embodiment, the second width is denoted as W4 in the drawing. Thus, W4> W1 and W4> W3.

It is understood that, for convenience of description, the line width is along the extending direction of the first and second channel regions 321 and 323. Therefore, the first width is the line width W2 of the relay area 322. In this embodiment, the first width W2 is larger than the second width W4, and the first width is considered to be the length of the relay zone 322, and the second width is considered to be the width of the relay zone 322. In this embodiment, the second width is greater than the line widths of the first channel region 321 and the second channel region 323, that is, W4> W1 and W4> W3, so that the relay region 322 has enough metal area for the movement of the void 70 after the dummy conductive via 60 is disposed.

In some embodiments, the metal interconnect structure further comprises:

and a third metal layer 80, wherein one end of the dummy conductive via 60 is connected to the first metal layer 30, and the other end is connected to the third metal layer 80.

It will be appreciated that one end of the dummy conductive via 60 is connected to the first metal layer 30, i.e., both are conductively connected. In this way, the third metal layer 80 increases the volume of conductive material of the dummy conductive via 60, more advantageously attracting the void 70. It will be appreciated that the third metal layer 80 may not be provided, i.e., the dummy conductive via 60 is open. Or the third metal layer 80 is disconnected or conductively connected to a low potential, but the third metal layer 80 cannot be connected to the second metal layer 40, otherwise the dummy conductive via 60 is identical to the conductive via 50, affecting the function of the integrated circuit.

In some embodiments, the metal interconnect structure further comprises:

a dielectric layer (not shown) between the first metal layer 30 and the second metal layer 40; the conductive via 50 and the dummy conductive via 60 are both located within the dielectric layer. By providing the dielectric layer, the first metal layer 30 and the second metal layer 40 can be insulated and separated, and the conductive via 50 and the dummy conductive via 60 can be easily manufactured.

In some embodiments, the material of the first metal layer 30 and the second metal layer 40 may be one or more of titanium (Ti), tiN (TiN), aluminum (Al), and the like.

In some embodiments, the material of the conductive via 50 and the dummy conductive via 60 may be one or more of tungsten (W), titanium (Ti), tiN (TiN), and the like.

In some embodiments, the material of the dielectric layer may be silicon dioxide (SiO ₂ ) One or more of dielectric materials such as silicon nitride (SiN) and silicon oxynitride (SiON).

In connection with fig. 5, the movement of the voids 70 under stress in the metal interconnect structure of the integrated circuit according to the embodiments of the present application will be described. The concentration of aggregated vacancies 70 is largely created by the base 31, with a plurality of vacancies 70 moving from the base 31 toward the conductive via 50 at a temperature, the arrows in the figure indicating the direction of movement of the vacancies 70. And the relay region 322 is located in the middle of the moving path of the base 31 to the conductive via 50, the dummy conductive via 60 on the relay region 322 is dispersed in advance with a large portion of the voids 70, so that the concentration of the voids 70 moving to the conductive via 50 is significantly reduced. Also, since the material of the dummy conductive via 60 is also a conductive material, the resistance on the path along which the base 31 moves toward the conductive via 50, that is, the resistance of the metal interconnection structure, is not substantially increased. In this way, the conductive vias 50 are protected and the function of the integrated circuit is not affected. On the other hand, from the stress perspective, the stress gradient on the connection portion 32 is dispersed under the stress, and the dummy conductive vias 60 on the relay region 322 collectively disperse the stress on the conductive vias 50, so that the stress in the vicinity of the conductive vias 50 is relatively reduced.

It should be understood that the above examples are illustrative and are not intended to encompass all possible implementations encompassed by the claims. Various modifications and changes may be made in the above embodiments without departing from the scope of the disclosure. Likewise, the individual features of the above embodiments can also be combined arbitrarily to form further embodiments of the invention which may not be explicitly described. Therefore, the above examples merely represent several embodiments of the present invention and do not limit the scope of protection of the patent of the present invention.

Claims (10)

1. A metal interconnect structure for an integrated circuit, comprising:

a first metal layer including a base portion and a connection portion connected to each other, the connection portion including a first end portion in contact with the base portion, the base portion including a second end portion in contact with the connection portion, a line width of the first end portion being smaller than a line width of the second end portion;

the second metal layer and the first metal layer are arranged at intervals in the thickness direction of the integrated circuit;

a conductive via for connecting the first metal layer and the second metal layer; the conductive through hole comprises a first conductive end and a second conductive end which are opposite to each other, the first conductive end is in contact with the connecting part of the first metal layer, and the second conductive end is in contact with the second metal layer;

and the dummy conductive through hole is positioned between the conductive through hole and the base part and comprises a third conductive end and a fourth conductive end which are opposite, and the third conductive end is in contact with the connecting part.

2. The metal interconnect structure of an integrated circuit of claim 1, wherein the connection portion comprises:

the first channel region, the relay region and the second channel region are sequentially arranged along the direction away from the base, wherein the line width of the relay region is larger than that of the first channel region and that of the second channel region, the third conductive end of the pseudo conductive through hole is in contact with the relay region, and the first conductive end of the conductive through hole is in contact with the second channel region.

3. The metal interconnect structure of an integrated circuit of claim 2, wherein a distance of the relay region from the conductive via is less than a distance of the relay region from the base.

4. The metal interconnection structure of an integrated circuit according to claim 2, wherein both ends of the relay region in a direction perpendicular to a direction from the base portion to the conductive via protrude from both sides of the first channel region and the second channel region.

5. The metal interconnection structure of an integrated circuit according to claim 4, wherein two portions of the relay region protruding from both sides of the first channel region and the second channel region are a first protrusion and a second protrusion; the first convex part and the second convex part are symmetrically arranged, and the first convex part and the second convex part are contacted with at least one pseudo conductive through hole.

6. The metal interconnection structure of an integrated circuit according to claim 1, wherein the number of the dummy conductive vias is at least two, and at least two of the dummy conductive vias are arranged in a direction perpendicular to the direction from the base portion to the conductive vias.

7. The metal interconnect structure of an integrated circuit of claim 5, wherein the dummy conductive via includes at least a first dummy conductive via, a second dummy conductive via, and a third dummy conductive via; the first and third dummy conductive vias are in contact with the first and second protrusions, respectively, and the second dummy conductive via is in contact with a relay section portion located between the first and second protrusions.

8. The metal interconnect structure of claim 3, wherein a linewidth of the first channel region is greater than a linewidth of the second channel region.

9. The metal interconnect structure of an integrated circuit of any of claims 1-6, wherein a cross-sectional area of said dummy conductive via and a cross-sectional area of said conductive via are the same.

10. The metal interconnect structure of an integrated circuit of any of claims 1-6, wherein the metal interconnect structure further comprises:

and the fourth conductive end of the dummy conductive through hole is contacted with the third metal layer.

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