CN116107381A - Reference voltage source circuit and chip - Google Patents
Reference voltage source circuit and chip Download PDFInfo
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- CN116107381A CN116107381A CN202211629933.8A CN202211629933A CN116107381A CN 116107381 A CN116107381 A CN 116107381A CN 202211629933 A CN202211629933 A CN 202211629933A CN 116107381 A CN116107381 A CN 116107381A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention discloses a reference voltage source circuit and a chip, which comprise a bias current generating circuit, a reference voltage source circuit and a reference voltage source circuit, wherein the bias current generating circuit is used for providing bias current; a reference voltage generating circuit for generating a reference voltage of zero temperature coefficient according to the bias current; and a reference voltage output circuit for generating a reference voltage according to the reference voltage, wherein the reference voltage source circuit further includes a feedback path connected between the bias current generating circuit and the reference voltage output circuit, the feedback path being for feeding back the reference voltage to the bias current generating circuit so that the bias current generating circuit generates the bias current according to the reference voltage, thereby outputting a low temperature drift, low offset reference voltage.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a reference voltage source circuit and a chip.
Background
Reference voltage source circuits are widely used in integrated circuits and system-in-chip, and are generally used for generating a reference voltage less affected by temperature inside the chip, and are used as reference voltages for other analog circuit units.
Fig. 1 shows a schematic diagram of a reference voltage source circuit according to the prior art, as shown in fig. 1, a reference voltage source circuit 100 includes transistors M1 and M2, an error amplifier OP, transistors Q1 and Q2, and resistors R0 and R1, wherein the transistors Q1 and Q2 are Bipolar Junction Transistors (BJTs), and the error is detectedThe difference amplifier OP is used for clamping the base-emitter voltage V of the transistor Q1 and the transistor Q2 BE Which mainly uses the base-emitter voltage V of a triode BE Inversely proportional to temperature, the base-emitter voltage difference DeltaV of transistor Q1 and transistor Q2 BE ＝V BE1 -V BE2 The characteristic of being proportional to the temperature is V BE And DeltaV BE And overlapping the reference voltages according to a certain proportion relationship to obtain the reference voltage Vr1 with the zero temperature coefficient.
Fig. 2 shows a schematic diagram of an error amplifier according to the prior art, and as shown in fig. 2, the error amplifier OP includes PMOS transistors M3 and M4 and NMOS transistors M5 and M6. Offset voltage is generated between positive and negative input ends of the error amplifier OP, namely between the control ends VP and VN of the transistor M5 and the transistor M6, and the offset voltage is superimposed on the reference voltage Vr1 after being amplified, so that the offset voltage Vosr of the reference voltage Vr1 is difficult to reduce, and the deviation of the reference voltage Vr1 between different wafers (wafers) and between chips (die) is larger.
Specifically, the equivalent offset voltage Vos between the positive and negative input terminals of the error amplifier OP is:
wherein gmp and gmn are the transconductance of the PMOS and NMOS respectively, and the equivalent offset voltage Vos is:
Vos≈Vosp+Vosn
when the reference voltage Vr1 is not superimposed with the equivalent offset voltage Vos, the expression of the reference voltage Vr1 is:
after the equivalent offset voltage Vos is superimposed, the expression of the finally output reference voltage Vr1 is:
when neglecting other offset, the offset voltage Vosr generated by the influence of the error amplifier OP on the reference voltage Vr1 is:
wherein, the value of R1/R0 is determined by the zero temperature coefficient of the reference voltage Vr1. In practical application, the transistor Q1 and the transistor Q2 are not single transistors, and are generally formed by connecting a plurality of transistors in parallel, and the number ratio of the transistor Q1 to the transistor Q2 in the prior art is mostly 1:8, the number ratio of the triode Q1 to the triode Q2 is 1:8, the value of R1/R0 is usually between 50 and 70, so that the offset voltage Vosr of the reference voltage Vr1 is higher.
Therefore, a new reference voltage source circuit has to be proposed to solve the above-mentioned problems.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a reference voltage source circuit and a chip, which can output a reference voltage with low temperature drift and low offset.
According to an aspect of the present invention, there is provided a reference voltage source circuit including a bias current generating circuit for supplying a bias current; a reference voltage generating circuit for generating a reference voltage of zero temperature coefficient according to the bias current; and a reference voltage output circuit for generating a reference voltage from the reference voltage, wherein the reference voltage source circuit further includes a feedback path connected between the bias current generating circuit and the reference voltage output circuit, the feedback path being for feeding back the reference voltage to the bias current generating circuit so that the bias current generating circuit generates the bias current from the reference voltage.
Optionally, the bias current generating circuit includes a first error amplifier, the negative input terminal is connected with the reference voltage, and the positive input terminal is connected with the first node voltage; the first transistor and the first resistor are sequentially connected between the power supply and the grounding end, the control end of the first transistor is connected with the output end of the first error amplifier, the drain end of the first transistor outputs the bias current, and the first node voltage is the common node voltage of the first transistor and the first resistor.
Optionally, the reference voltage generating circuit includes: the control end of the second transistor is connected with the control end of the first transistor, the first end of the third transistor is connected with the control end of the first transistor, the second transistor is used for copying the bias current, and the third transistor is used for generating the reference voltage according to the bias current.
Optionally, the reference voltage output circuit includes: the negative input end of the second error amplifier is connected with the reference voltage, and the positive input end of the second error amplifier is connected with the second node voltage; the control end of the fourth transistor is connected with the output end of the second error amplifier, wherein a common node of the third resistor and the fourth resistor is used for outputting the reference voltage, and the second node voltage is the common node voltage of the fourth resistor and the fifth resistor.
Optionally, the resistance value of the fourth resistor is adjustable, and the voltage value change of the reference voltage is realized by adjusting the resistance value of the fourth resistor.
Optionally, the third transistor is an NMOS transistor, and the first transistor, the second transistor, and the fourth transistor are PMOS transistors.
Optionally, the reference voltage source circuit further comprises a starting circuit for controlling the reference voltage to work at a correct direct current working point.
Optionally, the bias current
Wherein μ is carrier mobility of the third transistor, C ox For the gate oxide capacitance density of the third transistor,V TH and W is the channel width of the third transistor, and L is the channel length of the third transistor.
Optionally, the reference voltage is obtained by multiplying the temperature coefficient of the carrier mobility by a negative coefficient, which is adjusted by adjusting the temperature coefficient of the threshold voltage
And (3) the value of the third transistor is realized, wherein Ibias is the bias current, W is the channel width of the third transistor, and L is the channel length of the third transistor. />
According to another aspect of the present invention, there is provided a chip including the reference voltage source circuit described above.
According to the reference voltage source circuit and the reference voltage source chip, the characteristics that the carrier mobility and the threshold voltage of the MOS tube are inversely proportional to the temperature are utilized, the temperature coefficient of the carrier mobility is multiplied by a negative coefficient and then is overlapped with the temperature coefficient of the threshold voltage, the negative temperature coefficient of the threshold voltage is counteracted, the reference voltage with zero temperature coefficient is obtained, the low temperature drift characteristic of the output reference voltage is ensured, meanwhile, the reference voltage can be generated by the reference voltage generating circuit without an error amplifier, the reference voltage cannot be offset due to the influence of the error amplifier, and the low offset characteristic of the output reference voltage is ensured.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic diagram of a reference voltage source circuit according to the prior art;
fig. 2 shows a schematic diagram of the structure of an error amplifier according to the prior art;
FIG. 3 shows a schematic diagram of a reference voltage source circuit according to an embodiment of the invention;
FIG. 4 shows a circuit connection diagram of a reference voltage source circuit according to an embodiment of the invention;
fig. 5 shows a schematic diagram of offset voltage generation of a reference voltage source according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same elements or modules are denoted by the same or similar reference numerals in the various figures. For clarity, the various features of the drawings are not drawn to scale.
It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or circuit is "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
Also, certain terms are used throughout the description and claims to refer to particular components. It will be appreciated by those of ordinary skill in the art that a hardware manufacturer may refer to the same component by different names. The present patent specification and claims do not take the form of an element or components as a functional element or components as a rule.
Furthermore, it should be noted that relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the present application, a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal, and in an on state of the MOS transistor, a current flows from the first terminal to the second terminal. The first end, the second end and the control end of the PMOS tube are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the NMOS tube are respectively a drain electrode, a source electrode and a grid electrode.
Fig. 3 shows a schematic diagram of a reference voltage source circuit according to an embodiment of the present invention, and as shown in fig. 3, the reference voltage source circuit 200 includes a bias current generating circuit 210, a reference voltage generating circuit 220, and a reference voltage output circuit 230.
The bias current generating circuit 210 is configured to provide a bias current Ibias, the reference voltage generating circuit 220 is configured to generate a reference voltage Vr2 with a zero temperature coefficient according to the bias current Ibias, and the reference voltage output circuit 230 is configured to generate a reference voltage Vo according to the reference voltage Vr 2.
The reference voltage source circuit 200 further includes a feedback path connected between the bias current generating circuit 210 and the reference voltage output circuit 230 for feeding back the reference voltage Vo to the bias current generating circuit 210 so that the bias current generating circuit 210 generates the bias current Ibias according to the reference voltage Vo.
Fig. 4 shows a circuit connection diagram of a reference voltage source circuit according to an embodiment of the present invention, as shown in fig. 4, a bias current generating circuit 210 includes an error amplifier OPA, and a transistor MP1 and a resistor R0 sequentially connected between a power supply VDD and a ground terminal, wherein a positive input terminal of the error amplifier OPA is connected to a reference voltage Vo, a negative input terminal is connected to a node a, an output terminal is connected to a control terminal of the transistor MP1, and the error amplifier OPA is used for controlling a drain current of the transistor MP1, i.e., a bias current Ibias, according to an error value of a node voltage Va of the reference voltage Vo and the node a so that the node voltage Va is equal to a reference voltage Vo, wherein the node a is a common node of the transistor MP1 and the resistor R0, and the bias current Ibias has the expression:
the reference voltage generating circuit 220 includes a transistor MP2, a transistor MN1, and a resistor Rs sequentially connected between the power supply VDD and the ground, where the control terminal of the transistor MP2 is connected to the output terminal of the error amplifier OPA, the drain terminal current of the transistor MP2 is equal to the bias current Ibias, the first terminal of the transistor MN1 is connected to the control terminal for generating the reference voltage Vr2, the reference voltage Vr2 is output by a common node of the transistor MP2 and the transistor MN1, the transistor MP2 and the transistor MN1 both operate in a saturation region, and the expression of the bias current Ibias may be:
from this, the expression of the reference voltage Vr2 follows:
The temperature T is derived from both sides of equation (3):
wherein μ is carrier mobility, C of transistor MN1 ox The capacitance density, V, of the gate oxide layer of transistor MN1 TH The threshold voltages of the transistors MN1 are all process parameters, and are independent of the circuit structure. W is the channel width of the transistor MN1, and L is the channel length of the transistor MN 1.
At CMIn the OS process, carrier mobility μ and threshold voltage V TH All are inversely proportional to the temperature, and the temperature coefficients are all negative values. From equation (4), the temperature coefficient of the carrier mobility μ is multiplied by a negative coefficient and then is correlated with the threshold voltage V TH Is superimposed by the temperature coefficient of (a) to obtain the threshold voltage V TH The negative temperature coefficient of (2) is counteracted to obtain a reference voltage Vr2 with zero temperature coefficient, wherein the negative coefficient is adjusted by adjusting
Is realized by the value of (1). />
The reference voltage output circuit 230 includes an error amplifier OPB, and a transistor MP3, a resistor R2, and a resistor R1 sequentially connected between the power supply VDD and the ground, wherein the negative input terminal of the error amplifier OPB is connected to the reference voltage Vr2, the positive input terminal is connected to the node B, the output terminal is connected to the control terminal of the transistor MP3, the common node of the resistor R3 and the resistor R2 is used for outputting the reference voltage Vo, the error amplifier OPB is used for controlling the voltage drop of the transistor MP3 according to the error value of the node voltage Vb of the reference voltage Vr2 and the node B so that the node voltage Vb is equal to the reference voltage Vr2, wherein the node B is the common node of the resistor R2 and the resistor R1, and the expression of the reference voltage Vo is:
although the reference voltage generating circuit 220 in the reference voltage source circuit 200 provided by the invention does not have the error amplifier OP, so that the reference voltage Vo provided by the invention does not have the offset caused by the error amplifier OP, the circuit still has the offset voltage.
Fig. 5 shows a schematic diagram of offset voltage generation of a reference voltage source according to an embodiment of the present invention, as shown in fig. 5, offset voltage Vos1 of reference voltage source circuit 200 is mainly formed by multiplying offset voltage Vosp at a control terminal of transistor MP2 by a certain coefficient and then superimposing the multiplied offset voltage Vosp on reference voltage Vo, and offset voltage Vosn at a control terminal of transistor MN1 is directly superimposed on reference voltage Vo, where the expression is as follows:
wherein gmp and gmn are the transconductance of the transistor MP2 and the transistor MN1, respectively, and are assumed to be approximately equal for convenience of comparison with the prior art
Vos1＝Vosp+Vosn(7)，
Equation (7) and the prior art reference voltage Vr1 offset voltage Vosr
By comparison, it can be seen that the offset voltage Vos1 of the reference voltage Vo provided by the invention is far smaller than the offset voltage Vosr of the reference voltage Vr1 in the prior art, so that the offset voltage Vos1 of the output reference voltage Vo can be effectively improved by the reference voltage source circuit 200 provided by the invention, and the deviation of the reference voltage Vo between different wafers and between chips is reduced.
Further, the resistor R2 in the reference voltage output circuit 230 is a selectable or variable resistor, and the voltage value of the reference voltage Vo can be changed by changing the resistance value of the resistor R2, so as to meet the requirements of different circuits on the reference voltage Vo.
Further, the transistors MP1, MP2 and MP3 are PMOS transistors, and the transistor MN1 is an NMOS transistor.
Further, there is a positive feedback path of the reference voltage Vr 2-reference voltage Vo-reference voltage Vr2 in the reference voltage source circuit 200, and the positive feedback loop gain of the positive feedback path needs to be lower than 0dB.
Further, the reference voltage source circuit 200 further includes a start-up circuit, which is used to ensure that the reference voltage Vr2 operates at a correct dc operating point, and may be, for example, a timing control circuit.
According to the reference voltage source circuit 200 provided by the embodiment of the invention, the carrier mobility μ and the threshold voltage V of the MOS tube are utilized TH The temperature coefficient of the carrier mobility mu is multiplied by a negative coefficient and then is inversely proportional to the threshold voltage V TH Is superimposed by the temperature coefficient of (2) and the threshold voltage V TH The negative temperature coefficient of (2) is offset to obtain the reference voltage Vr2 with zero temperature coefficient, so that the low temperature drift characteristic of the output reference voltage Vo is ensured, and meanwhile, the reference voltage generating circuit 220 can generate the reference voltage Vr2 without an error amplifier OP, so that the reference voltage Vr2 cannot be offset under the influence of the error amplifier OP, and the low offset characteristic of the output reference voltage Vo is ensured.
Correspondingly, the invention also provides a chip which can be a system-on-chip. Wherein the chip further comprises the reference voltage source circuit 200 of the above embodiment.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the appended claims and their equivalents.
Claims (10)
1. A reference voltage source circuit comprising:
a bias current generating circuit for providing a bias current;
a reference voltage generating circuit for generating a reference voltage of zero temperature coefficient according to the bias current; and
a reference voltage output circuit for generating a reference voltage from the reference voltage,
wherein the reference voltage source circuit further includes a feedback path connected between the bias current generating circuit and the reference voltage output circuit, the feedback path being for feeding back the reference voltage to the bias current generating circuit so that the bias current generating circuit generates the bias current according to the reference voltage.
2. The reference voltage source circuit of claim 1, wherein the bias current generating circuit comprises:
the negative input end of the first error amplifier is connected with the reference voltage, and the positive input end of the first error amplifier is connected with the first node voltage;
a first transistor and a first resistor which are connected between a power supply and a grounding end in sequence, wherein the control end of the first transistor is connected with the output end of the first error amplifier,
the drain terminal of the first transistor outputs the bias current, and the first node voltage is a common node voltage of the first transistor and the first resistor.
3. The reference voltage source circuit of claim 2, wherein the reference voltage generation circuit comprises:
the control end of the second transistor is connected with the control end of the first transistor, the first end of the third transistor is connected with the control end,
wherein the second transistor is configured to replicate the bias current, and the third transistor is configured to generate the reference voltage according to the bias current.
4. A reference voltage source circuit according to claim 3 wherein the reference voltage output circuit comprises:
the negative input end of the second error amplifier is connected with the reference voltage, and the positive input end of the second error amplifier is connected with the second node voltage;
a fourth transistor, a third resistor, a fourth resistor and a fifth resistor which are connected between the power supply and the grounding end in sequence, wherein the control end of the fourth transistor is connected with the output end of the second error amplifier,
the common node of the third resistor and the fourth resistor is used for outputting the reference voltage, and the second node voltage is the common node voltage of the fourth resistor and the fifth resistor.
5. The reference voltage source circuit of claim 4 wherein the resistance of the fourth resistor is adjustable, and wherein the voltage value of the reference voltage is varied by adjusting the resistance of the fourth resistor.
6. The reference voltage source circuit of claim 4 wherein the third transistor is an NMOS transistor and the first, second, and fourth transistors are PMOS transistors.
7. The reference voltage source circuit of claim 4, further comprising:
and the starting circuit is used for controlling the reference voltage to work at a correct direct current working point.
8. The reference voltage source circuit of claim 3 wherein,
the bias current
Wherein μ is carrier mobility of the third transistor, C ox For the capacitance density of the gate oxide layer of the third transistor, V TH And W is the channel width of the third transistor, and L is the channel length of the third transistor.
9. The reference voltage source circuit of claim 8 wherein,
the reference voltage is obtained by multiplying the temperature coefficient of the carrier mobility by a negative coefficient, and the negative coefficient is obtained by adjusting
And (3) the value of the third transistor is realized, wherein Ibias is the bias current, W is the channel width of the third transistor, and L is the channel length of the third transistor.
10. A chip comprising a reference voltage source circuit as claimed in any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211629933.8A CN116107381A (en) | 2022-12-19 | 2022-12-19 | Reference voltage source circuit and chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211629933.8A CN116107381A (en) | 2022-12-19 | 2022-12-19 | Reference voltage source circuit and chip |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104049671A (en) * | 2014-07-03 | 2014-09-17 | 中国科学院微电子研究所 | Zero-temperature-coefficient reference voltage generation circuit for three-dimensional memory |
| CN112034922A (en) * | 2020-11-06 | 2020-12-04 | 成都铱通科技有限公司 | Positive temperature coefficient bias voltage generating circuit with accurate threshold |
| US20210132644A1 (en) * | 2019-11-05 | 2021-05-06 | Shenzhen GOODIX Technology Co., Ltd. | Ldo, mcu, fingerprint module and terminal device |
| CN114690831A (en) * | 2022-03-21 | 2022-07-01 | 电子科技大学 | Current self-biased series CMOS band-gap reference source |
| CN115113676A (en) * | 2021-03-18 | 2022-09-27 | 纮康科技股份有限公司 | Reference circuit with temperature compensation function |
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2022
- 2022-12-19 CN CN202211629933.8A patent/CN116107381A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104049671A (en) * | 2014-07-03 | 2014-09-17 | 中国科学院微电子研究所 | Zero-temperature-coefficient reference voltage generation circuit for three-dimensional memory |
| US20210132644A1 (en) * | 2019-11-05 | 2021-05-06 | Shenzhen GOODIX Technology Co., Ltd. | Ldo, mcu, fingerprint module and terminal device |
| CN112034922A (en) * | 2020-11-06 | 2020-12-04 | 成都铱通科技有限公司 | Positive temperature coefficient bias voltage generating circuit with accurate threshold |
| CN115113676A (en) * | 2021-03-18 | 2022-09-27 | 纮康科技股份有限公司 | Reference circuit with temperature compensation function |
| CN114690831A (en) * | 2022-03-21 | 2022-07-01 | 电子科技大学 | Current self-biased series CMOS band-gap reference source |
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