CN116106729B - Scan chain and combinational logic fault diagnosis method based on cost loss factor - Google Patents
Scan chain and combinational logic fault diagnosis method based on cost loss factor Download PDFInfo
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Abstract
The application discloses a scan chain based on a cost loss factor and a combined logic fault diagnosis method, which relate to the field of EDA detection, and find out all fault scan chains and judge fault types by detecting a chip to be detected; determining suspicious ranges of suspicious scan cells in a failed scan chain using the set of ATPG test patterns; injecting faults of the same type as the fault scanning chain into each candidate scanning unit in the suspicious range in sequence, and calculating cost loss factors of the fault scanning chain by comparing simulation responses of the candidate scanning units and fault circuit responses to determine target fault points of the fault scanning chain; modifying the target fault point location, and comparing the total cost loss factor accumulated in the current period with the accumulation in the previous period; if the total cost loss factor is not less than the previous period, determining all fault points and ending the fault diagnosis of the chip; the scheme can save peripheral hardware cost, can accurately position fault points on each fault scanning chain, and improves diagnosis efficiency and detection precision.
Description
Technical Field
The embodiment of the application relates to the field of EDA detection, in particular to a scan chain based on a cost loss factor and a combinational logic fault diagnosis method.
Background
With the advent of bipolar transistors, integrated circuits have evolved over half a century, with the development of improved semiconductor processing techniques and EDA tools, continually enabling more complex systems to be implemented on a single chip, with higher clock frequencies and greater system densities. The manufacturing process of the chip is smaller and smaller, the scale of the digital chip is larger and larger, and the testing cost is further increased and even exceeds the original cost of the functional part of the chip.
How to consider testing problems during chip design is an important part of current chip designs. Testing has become a very important factor in the design and fabrication of integrated circuits, which has not been used solely as a means of testing and verifying chip products, but rather has been a closely related expertise to integrated circuit designs, and has been an organic whole with design and fabrication. Design For Test (DFT) opens up a feasible way For the whole testing field, and DFT has become a key link of chip Design. The diagnosis of scan chain and combinational logic faults is a major problem that is relatively fundamental and is severely disturbed.
In the conventional technology, the main methods of scan chains and combinational logic diagnosis are as follows:
1. Observing defect reactions at different positions based on a diagnostic technique of the tester;
2. Hardware-based diagnostic techniques facilitate diagnostic procedures through additional hardware overhead;
3. and the related algorithm diagnosis technology based on software can realize fault diagnosis efficiently and quickly.
However, with the continued development of integrated circuit chips, higher clock frequencies and greater system densities have placed higher demands on test diagnostics. Diagnostic techniques based on testers are difficult to apply to chips with embedded compression circuits without using bypass mode. Hardware-based approaches facilitate the diagnostic process using some special scan chain and scan cell designs, however they typically require special designs for the scan chain/scan cell and have additional hardware overhead, which is unacceptable in many real world products. So current eye-turning software-based techniques use algorithmic diagnostics to identify faulty scanning units. However, the existing algorithm diagnosis program is less, and related algorithms have the defects of long time consumption, complex and redundant process, low accuracy, incapability of detecting all fault points and the like. The technical scheme of the patent application of the invention of CN1531046A is as follows: a plurality of initial value vectors associated with the inverters are selected for each corresponding scan chain set in a plurality of logic integrated circuits having the same configuration. The initial vectors in the same corresponding scan chain set are compared with each other, and the elements with fixed values in the initial value vectors are confirmed. When the number of elements of the fixed value reaches a certain desired percentage, the elements are selected as a standard pattern for the scan chain set. Finally, the initial value vector of the scanning chain in the logic integrated circuit for fault location and the standard pattern related to the scanning chain are compared with each other, and whether the scanning chain has a faulty inverter is determined through the difference of comparison results. Although the method can realize the positioning of the scanning chain faults, belongs to a comparison basic classical method in a fault positioning diagnosis method, the method has the defects of low actual operation efficiency, long time consumption and the like of comparison basicity, can not position all faults in a short time efficiently, and can miss part of fault positions due to intermittent faults and other problems, thereby being not beneficial to the diagnosis test of a large-scale basic logic circuit scanning chain.
Therefore, if the above-described fault diagnosis technique is used to determine the true fault point, there are the following main problems:
1. the number of test vectors is huge, and the traditional physical and hardware fault detection method is not applicable.
2. Finding these faults wastes the working time of the engineer and also wastes a lot of test expenses (the test machine is charged in time).
3. The related algorithm can only diagnose single faults in the scan chain, and can not accurately judge and check a plurality of actual fault conditions.
Disclosure of Invention
The embodiment of the application provides a scan chain based on a cost loss factor and a combinational logic fault diagnosis method, which solve the problems of complex fault diagnosis, high hardware cost and low detection precision, and comprise the following steps:
s1, finding out all fault scan chains by detecting a chip to be detected and judging fault types;
S2, determining suspicious ranges of suspicious scanning units in the fault scanning chain by using an ATPG test mode set corresponding to the scanning chain;
s3, sequentially injecting faults of the same type as the fault scanning chain into each candidate scanning unit in the suspicious range, calculating cost loss factors of the fault scanning chain by comparing simulation responses of the candidate scanning units and fault circuit responses, and determining target fault points of the fault scanning chain;
S4, modifying the target fault point location, and comparing the total cost loss factor accumulated in the current period with the total cost loss factor accumulated in the previous period; if the total cost loss factor of the current period is not less than the total cost loss factor of the previous period, determining all fault points and ending the fault diagnosis of the chip.
Specifically, S3 includes:
S31, sequentially injecting the selected candidate scanning units into faults of the same type as the faults, changing the suspicious bit values of the candidate scanning units according to the fault types in the loading process, and loading the fault scanning chains;
S32, performing four-value (0, 1, X, Z) logic simulation on the loaded fault scanning chain, capturing test response, and calculating a logic probability value of the test response;
s33, changing the suspicious bit again according to the assumed output value of the fault type in the unloading process, and unloading the fault scanning chain;
S34, obtaining logic probability of updating the candidate scanning units according to simulation response and fault circuit response of the candidate scanning units in the loading and unloading processes, and calculating the cost loss factor of the fault scanning chain according to the logic probability and the number of fault bits.
Specifically, the cost loss factors comprise a class-two cost loss factor and a class-two cost loss factor, and the class-two cost loss factors are calculated based on a probability search method; s31 includes:
Setting suspicious bits corresponding to the candidate scanning units and adjacent bits thereof as output values which are subjected to fault after loading; and calculating the first logic probability of all the candidate scanning units loaded in the suspicious range through the position of fault injection and the probability of triggered faults.
Specifically, S32 includes: capturing a test response of the four-value logic simulation; updating and calculating the first logic probability based on a test response and a COP algorithm to obtain a second logic probability of the candidate scanning unit;
S33 includes: setting the suspicious bit corresponding to the candidate scanning unit and the adjacent bit thereof as output values which are failed after unloading, wherein the values captured by other normal chains are unchanged; updating and calculating a third logic probability of the candidate scanning unit after unloading through the following formula;
Wherein, Is the logical probability of the occurrence of a "0" for the ith candidate scan cell,/>Logical probability of occurrence of "1" for ith candidate scan cell,/>Logical probability of the i+1 candidate scan cell appearing "0"/>The logical probability of the i+1 candidate scan cell having a "1", pr, is the probability that the fault is triggered.
Specifically, S34 includes: calculating a matching score Match according to the ratio of the number of the explained fault bits to the total number of the fault bits after the fault injection is accumulated; wherein the matching score is obtained based on historical simulated responses and observed fault circuit responses;
calculating Mismatch scores Mismatch according to the ratio of the number of the good values of the accumulated errors to the total number of the good values in the test mode; the mismatch score is used to describe the difference between the simulated and good values observed in the event of an injection fault;
and calculating the cost loss factors CL 1 of the type according to the matching score and the non-matching score, wherein the formula is as follows:
CL1＝K1*Match+K2*Mismatch
Wherein, K 1 and K 2 are correlation coefficients, and K 1 is a negative value and K 2 is a positive value;
The type A mismatch score UF 1 calculated when a fault is detected and the type B mismatch score UF 2 calculated when no fault is detected in a historical period are obtained, and the type two cost loss factors CL 2 are calculated according to two types of mismatch scores, wherein the formula is as follows:
CL2＝L1*UF1+L2*UF2
Wherein, L 1 and L 2 are positive values, and the two types of mismatch scores are judged according to the two mismatch probabilities;
And determining the target fault point according to the one type of cost loss factors and the two types of cost loss factors.
Specifically, the process of determining the target fault point includes:
acquiring the one type of cost loss factors and the two types of cost loss factors of all the candidate scanning units in the suspicious range, and sorting the one type of cost loss factors in ascending order;
When only one lowest cost loss factor exists, determining the corresponding candidate scanning unit as the target fault point of the fault scanning chain; and when at least two identical lowest cost loss factors exist, comparing the two kinds of cost loss factors of a plurality of uncertain points, and determining the uncertain point with the smaller two kinds of cost loss factors as the target fault point.
Specifically, S2 includes: based on the fault type loading and unloading value characteristics, the modified ATPG test mode is used for covering the influence of a fault unit on the result obtained after the scanning process, and the upper bound and the lower bound of the suspicious range are identified by comparing the analog value obtained in the test process with the value observed in the fault circuit response.
Specifically, S4 includes: after the target fault point of the x-th period is determined, the fault is injected and the sum of the first class cost loss factor and the second class cost loss factor corresponding to the scanning unit is recalculated after modification, and the total cost loss factor CL x in the x-th period is obtained and is expressed as follows:
CL x＝CLx1+CLx2 wherein CL 1x represents a class of cost penalty factors for the x-th period and CL 2x represents a class of cost penalty factors for the x-th period;
And when the CL x≥CLx-1 is adopted, indicating that the total cost loss factor in the x-th period is not less than the total cost loss factor in the x-1 th period, indicating that all fault points are found, and ending the chip fault diagnosis.
Specifically, when CL x≤Lx-1 indicates that the total cost loss factor in the x-th period is not greater than the total cost loss factor in the x-1 th period, the current scan point is removed, the suspicious range is redetermined, the next fault point is found, and the rest target fault points are determined by traversing all scan units until all fault points are queried.
Specifically, the fault scan chain is identified by a flushing pattern of several chains, and a fault result different from a predetermined result occurs according to a fault occurring in a part of units or combinational logic of the scan chain during loading or unloading.
The technical scheme provided by the embodiment of the application has the beneficial effects that at least: the scheme uses the matching degree cost loss factor calculation to carry out fault diagnosis, combines two types of cost loss calculation methods to carry out the algorithm simultaneously, improves the decision accuracy and reduces the traditional fault diagnosis time. Through carrying out corresponding operation by utilizing the known fault type judgment in the loading and unloading process, the influence of faults on other good point positions is avoided, the method has good effect on accurate fault point position judgment of multiple fault situations, the peripheral hardware cost can be saved, the fault points on each fault scanning chain can be accurately positioned, and the diagnosis efficiency and the detection precision are improved.
Drawings
FIG. 1 is a flow chart of a scan chain and combinational logic fault diagnosis method based on cost penalty factors;
FIG. 2 is a flow chart for calculating a cost penalty factor of a type of candidate scan cell;
FIG. 3 is a flow chart for calculating a candidate scan cell class II cost penalty factor;
FIG. 4 is a logic diagram of a scan chain and combinational logic fault diagnosis method based on cost penalty factors;
FIG. 5 is an algorithm flow chart of a scan chain and combinational logic fault diagnosis method based on cost penalty factors.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.
References herein to "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
Fig. 1 is a flowchart of a scan chain and combinational logic fault diagnosis method based on a cost loss factor according to an embodiment of the present application, including the following steps:
s1, finding out all fault scan chains by detecting the chip to be detected and judging the fault type.
The fault type of a faulty scan chain is typically identified by the flushing pattern of some of the chains, and the scan chain may have a different fault result during loading (load) or unloading (unload) from the originally intended result because part of the units or combinational logic in the scan chain fail. Taking table 1 as an example, it is assumed here that one scan chain is shifted in a pattern of "0001110001110001", and a comparison is made according to these examples listed in the table, and then a fault determination is made according to the observation result and the original setting result, and most of the cases in the actual case are intermittent faults. And judging all fault scan chains of the chip and corresponding fault types through contents shown in table 1.
TABLE 1 Fault Scan chain and fault type
| Fault type | Unloading value (permanent fault) | Unloading value (intermittent fault) |
| Clip 0 | 0000000000000000 | 0000100000100000 |
| Clip 1 | 1111111111111111 | 1101111101111111 |
| Slow and slow | 001110001110001X | —— |
| Quick speed | X000111000111000 | —— |
| Slowly rise up | 000110000110000X | 000110001110001X |
| Slowly descend | 001111001111001X | 001111001110001X |
| Fast rise | X001111001111001 | X001111000111000 |
| Rapidly descend | X000110000110000 | X000110000111000 |
S2, determining suspicious ranges of suspicious scanning units in the fault scanning chain by using the ATPG test mode set corresponding to the scanning chain.
After the fault type is determined, the specific modified ATPG test mode is used according to the corresponding loading and unloading value characteristics, the influence of the fault unit on the result obtained after the scanning process is covered, and other values in the scanning chain are not influenced. The upper and lower bounds of the candidate scan cells, i.e., the suspicious ranges of suspicious scan cells in the fault scan chain, are identified by comparing the analog values obtained during the test with the values observed in the fault circuit response.
S3, sequentially injecting faults of the same type as the fault scanning chain into each candidate scanning unit in the suspicious range, calculating cost loss factors of the fault scanning chain by comparing simulation responses of the candidate scanning units and fault circuit responses, and determining target fault points of the fault scanning chain.
The main purpose of the process is to calculate the cost loss factors, the scheme adopts the synchronous calculation of the first type cost loss factors and the second type cost loss factors, and the second type cost loss factors are calculated based on a probability search method. The method specifically comprises the following detailed steps:
s31, sequentially injecting the selected candidate scanning units into faults of the same type as the faults, changing the suspicious bit values of the candidate scanning units according to the fault types in the loading process, and loading the fault scanning chains.
The purpose of fault injection is to observe the difference of the front and rear output test responses, and the scheme can be split into two independent parts, namely, the process of calculating the first class and second class cost loss factors of the selected candidate scan chain, and the scheme participates in fig. 3 and 4.
For one type of cost loss factor calculation step, the suspicious bit corresponding to the candidate scanning unit and the adjacent bits thereof are set as output values which fail after loading, namely, the output values which should be changed after assuming that the failure occurs, and other bits can be correctly shifted in. And then loading the fault scanning chain after the fault injection.
And for the second-class cost loss factor calculation step, judging through logic probability, and calculating the first logic probability of all candidate scanning units loaded in the suspicious range through the position of fault injection and the probability that the fault is triggered after loading is completed.
S32, performing four-value (0, 1, X, Z) logic simulation on the loaded fault scanning chain, capturing test response, and calculating a logic probability value of the test response.
Four-value (0, 1, X, Z) logic simulation is required for all scan chains for both the first class and second class cost calculation processes, so as to obtain captured test responses. And the second-class cost calculation also needs to update and calculate the first logic probability through test response and COP algorithm on the basis of obtaining the four-value logic simulation, so as to obtain the second logic probability of the candidate scanning unit.
S33, changing the suspicious bit again according to the assumed output value of the fault type in the unloading process, and unloading the fault scan chain.
The unloading process is used for front-to-back comparison calculation, and similar to the process of loading the fault scan chain, one type of cost calculation process sets the suspicious bit corresponding to the candidate scan unit and the adjacent bit thereof as an output value which is supposed to have faults after unloading, and the values captured by other normal chains are unchanged, so that the fault scan chain is unloaded.
And the second-class cost calculation process continuously updates the second logic probability according to the output and probability calculation method according to the test response after the fault scan chain is unloaded, so as to obtain the third logic probability of each candidate scan unit.
The update process is calculated according to the following formula:
Wherein, Is the logical probability of the occurrence of a "0" for the ith candidate scan cell,/>Logical probability of occurrence of "1" for ith candidate scan cell,/>Logical probability of the i+1 candidate scan cell appearing "0"/>The logical probability of the i+1 candidate scan cell having a "1", pr, is the probability that the fault is triggered. The logical probability value is known to consist of the impact of the occurrence and non-occurrence of 0,1 transitions, respectively, and whether a fault has occurred.
S34, obtaining logic probability of updating the candidate scanning units according to simulation response and fault circuit response of the candidate scanning units in the loading and unloading processes, and calculating cost loss factors of the fault scanning chains according to the logic probability and the number of fault bits.
A class of cost penalty factors: calculating a matching score Match according to the ratio of the number of the explained fault bits to the total number of the fault bits after the fault injection is accumulated; and calculating Mismatch score Mismatch according to the ratio of the number of the good values of the accumulated errors to the total number of the good values in the test mode.
Wherein the match score is obtained based on the historical simulated response and the observed fault circuit response, and the total match score is the sum of all match scores for each fault cell. Whereas Mismatch score Mismatch is a measure of the difference between the simulated value and the good value observed in the event of an injected fault, which is the ratio of the number of false good values to the total number of good values in this pattern.
And calculating a cost loss factor CL 1 according to the matching score and the non-matching score, wherein the formula is as follows:
CL1＝K1*Match+K2*Mismatch
Where K 1 and K 2 are correlation coefficients, and K 1 is negative and K 2 is positive.
And calculating the second class cost loss factor, namely after calculating the corresponding logic probability in the first three steps, judging by a calculation method according to the two mismatch probabilities. Assuming a "0" ("1") was observed at i, the mismatch score was P i 1(Pi 0), the corresponding type A mismatch score was UF 1, and the type B mismatch score was UF 2. The type a mismatch score is obtained according to the calculation of the period when the fault is detected in the history period process, the type B mismatch score UF 2 is calculated in the period when the fault is not detected, after the summary and update of logic probabilities are performed for a plurality of times, the two types of scores are added to obtain the type two cost loss factors CL 2, and the calculation logic schematic diagram is shown in fig. 4, and the formula is as follows:
CL2＝L1*UF1+L2*UF2
Wherein, L 1 and L 2 are positive values, and the two mismatch scores are judged according to the two mismatch probabilities.
Through the steps, two types of cost loss factors of each candidate scanning unit can be calculated in a polling mode, and the target fault point is determined according to the size of the cost loss factors. The method specifically comprises the following steps:
a, obtaining one type of cost loss factors and two types of cost loss factors of all candidate scanning units in a suspicious range, and sorting the one type of cost loss factors in ascending order.
And b, when only one lowest cost loss factor exists, determining the corresponding candidate scanning unit as a target fault point of the fault scanning chain.
And c, when at least two identical lowest cost loss factors exist, comparing the two kinds of cost loss factors of the plurality of uncertain points, and determining the uncertain point with the smaller two kinds of cost loss factors as a target fault point.
The process is to find out the lowest cost loss factor of the first class, when the parallel condition exists, the existence of at least two uncertain points is indicated, and at the moment, the two cost loss factors of the second class are started for comparison, and the lower cost loss factor is taken as the target fault point.
S4, modifying the target fault point location, and comparing the total cost loss factor accumulated in the current period with the total cost loss factor accumulated in the previous period; if the total cost loss factor of the current period is not less than the total cost loss factor of the previous period, determining all fault points and ending the fault diagnosis of the chip.
The method specifically comprises the following steps:
a, after determining a target fault point of the x-th period, the fault is injected and modified, and then the sum of the first class cost loss factor and the second class cost loss factor corresponding to the scanning unit is recalculated, so that a total cost loss factor CL x in the x-th period is obtained, and is expressed as follows:
CL x＝CLx1+CLx2 where CL 1x represents a class of cost penalty factors for the x-th period and CL 2x represents a class of cost penalty factors for the x-th period.
And b, when the CL x≥CLx-1 is adopted, indicating that the total cost loss factor in the x-th period is not smaller than the total cost loss factor in the x-1-th period, namely, the loss factor is larger relative to the last query modification result, indicating that all fault points are found, and ending the chip fault diagnosis without modification.
And c, when the CL x≤CLx-1 is adopted, indicating that the total cost loss factor in the x-th period is not greater than the total cost loss factor in the x-1-th period, removing the current scanning point, redefining the suspicious range and searching the next fault point, and determining the rest target fault points by traversing all scanning units until all fault points are queried and modified.
It should be noted that, when there is only one fault point on one fault scan chain, the process is directly finished, and the next fault scan chain is entered to continue to execute the above steps.
FIG. 5 is an algorithm flow chart of a scan chain and combinational logic fault diagnosis method based on cost penalty factors, comprising the steps of:
determining the fault type of a fault scanning chain machine;
Determining the scannable range of the scannable unit, i.e. determining the upper and lower limits;
Injecting corresponding faults into the ith candidate scanning unit;
Changing suspicious bits and loading a fault scan chain;
performing four-value logic simulation on the test unit, capturing test response and calculating logic probability of the candidate scanning unit;
changing suspicious bits, unloading the fault scan chain and updating logic probability;
calculating one class and two classes of cost loss factors according to the calculation and test processes;
After all the candidate scanning units in the suspicious range are tested, determining a target fault point by comparing two types of cost loss factors and the total cost loss factors and modifying the target fault point;
If the total cost loss factor of the current period is larger than that of the previous period, finding all fault points, ending diagnosis, otherwise, removing the determined target fault points, re-determining the suspicious range, and circularly executing the process until the conditions are met.
In summary, the scheme uses the matching degree cost loss factor calculation to perform fault diagnosis, combines two types of cost loss calculation methods to perform algorithms simultaneously, improves the decision accuracy, and reduces the traditional fault diagnosis time. Through carrying out corresponding operation by utilizing the known fault type judgment in the loading and unloading process, the influence of faults on other good point positions is avoided, the method has good effect on accurate fault point position judgment of multiple fault situations, the peripheral hardware cost can be saved, the fault points on each fault scanning chain can be accurately positioned, and the diagnosis efficiency and the detection precision are improved.
The scheme is to compare in a scan chain to be tested with 147000 scan units, and if the algorithm provided by the scheme is not adopted, the traditional physical and hardware methods need to compare each scan unit one by one, so that the number is too large, and the comprehensive detection of faults is difficult to complete. And in the actual situation, in the 147000 scanning units, more than one fault exists, and the existing algorithm cannot accurately judge the fault points. When the cost calculation method algorithm is adopted, the running time is only about 1 hour, the design 3 is 5 hours, and the diagnosis resolution is higher, and the artificial silicon debugging of the large design usually takes several months. In contrast, a great deal of labor time and time cost are saved, and meanwhile, the detection precision is improved.
The foregoing describes preferred embodiments of the present invention; it is to be understood that the invention is not limited to the specific embodiments described above, wherein devices and structures not described in detail are to be understood as being implemented in a manner common in the art; any person skilled in the art will make many possible variations and modifications, or adaptations to equivalent embodiments without departing from the technical solution of the present invention, which do not affect the essential content of the present invention; therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (6)
1. A scan chain and combinational logic fault diagnosis method based on a cost loss factor, the method comprising:
s1, finding out all fault scan chains by detecting a chip to be detected and judging fault types;
S2, determining suspicious ranges of suspicious scanning units in the fault scanning chain by using an ATPG test mode set corresponding to the scanning chain;
s3, sequentially injecting faults of the same type as the fault scanning chain into each candidate scanning unit in the suspicious range, calculating cost loss factors of the fault scanning chain by comparing simulation responses of the candidate scanning units and fault circuit responses, and determining target fault points of the fault scanning chain; the method specifically comprises the following steps:
S31, sequentially injecting the selected candidate scanning units into faults of the same type as the fault scanning chain, changing the suspicious bit values of the candidate scanning units according to the fault types in the loading process, and loading the fault scanning chain; the method specifically comprises the following steps: setting suspicious bits corresponding to the candidate scanning units and adjacent bits thereof as output values which are subjected to fault after loading; calculating first logic probabilities of all the candidate scanning units loaded in the suspicious range through the position of fault injection and the probability that the fault is triggered;
S32, performing four-value logic simulation on the loaded fault scanning chain, capturing test response, and calculating a logic probability value of the test response; the method specifically comprises the following steps: capturing a test response of the four-value logic simulation; updating and calculating the first logic probability based on a test response and a COP algorithm to obtain a second logic probability of the candidate scanning unit;
S33, changing the suspicious bit again according to the assumed output value of the fault type in the unloading process, and unloading the fault scanning chain; the method specifically comprises the following steps: setting suspicious bits corresponding to the candidate scanning units and adjacent bits thereof as output values with faults after unloading, wherein the values captured by other normal chains are unchanged, and unloading the fault scanning chains; updating and calculating a third logic probability of the candidate scanning unit after unloading through the following formula;
Wherein, Is the logical probability of the occurrence of a "0" for the ith candidate scan cell,/>Logical probability of occurrence of "1" for ith candidate scan cell,/>Logical probability of the i+1 candidate scan cell appearing "0"/>Logic probability of occurrence of 1 in the (i+1) th candidate scanning unit, pr is probability of triggering faults; wherein/>Is the logical probability of the occurrence of a "0" for the ith candidate scan cell,/>Logical probability of occurrence of "1" for ith candidate scan cell,/>Logical probability of the i+1 candidate scan cell appearing "0"/>Logic probability of occurrence of 1 in the (i+1) th candidate scanning unit, pr is probability of triggering faults;
s34, acquiring logic probability of updating the candidate scanning unit according to the simulation response and fault circuit response of the candidate scanning unit in the loading and unloading processes, and calculating the cost loss factor of the fault scanning chain according to the logic probability and the number of fault bits; the method specifically comprises the following steps: calculating a matching score Match according to the ratio of the number of the explained fault bits to the total number of the fault bits after the fault injection is accumulated; wherein the matching score is obtained based on historical simulated responses and observed fault circuit responses;
calculating Mismatch scores Mismatch according to the ratio of the number of the good values of the accumulated errors to the total number of the good values in the test mode; the mismatch score is used to describe the difference between the simulated and good values observed in the event of an injection fault;
calculating a cost loss factor CL 1 according to the matching score and the unmatched score; the formula is as follows:
CL1＝K1*Match+K2*Mismatch
Wherein, K 1 and K 2 are correlation coefficients, and K 1 is a negative value and K 2 is a positive value;
Obtaining a type A unmatched score UF 1 calculated when a fault is detected in a history period and a type B unmatched score UF 2 calculated when the fault is not detected, and calculating a type II cost loss factor CL 2 according to the two types of unmatched scores; the formula is as follows:
CL2＝L1*UF1+L2*UF2
Wherein, L 1 and L 2 are positive values, and the two types of mismatch scores are judged according to the two mismatch probabilities;
determining the target fault point according to the one type of cost loss factors and the two types of cost loss factors;
S4, modifying the target fault point location, and comparing the total cost loss factor accumulated in the current period with the total cost loss factor accumulated in the previous period; if the total cost loss factor of the current period is not less than the total cost loss factor of the previous period, determining all fault points and ending the fault diagnosis of the chip.
2. The cost-penalty factor-based scan chain and combinational logic fault diagnosis method of claim 1, wherein determining the target fault point process comprises:
acquiring the one type of cost loss factors and the two types of cost loss factors of all the candidate scanning units in the suspicious range, and sorting the one type of cost loss factors in ascending order;
When only one lowest cost loss factor exists, determining the corresponding candidate scanning unit as the target fault point of the fault scanning chain; and when at least two identical lowest cost loss factors exist, comparing the two kinds of cost loss factors of a plurality of uncertain points, and determining the uncertain point with the smallest two kinds of cost loss factors as the target fault point.
3. The scan chain and combinational logic fault diagnosis method based on cost loss factor according to claim 1, wherein S2 comprises:
Based on the fault type loading and unloading value characteristics, the modified ATPG test mode is used for covering the influence of a fault unit on the result obtained after the scanning process, and the upper bound and the lower bound of the suspicious range are identified by comparing the analog value obtained in the test process with the value observed in the fault circuit response.
4. The scan chain and combinational logic fault diagnosis method based on cost loss factor according to claim 1, wherein S4 comprises:
After the target fault point of the x-th period is determined, the fault is injected and the sum of the first class cost loss factor and the second class cost loss factor corresponding to the scanning unit is recalculated after modification, and the total cost loss factor CL x in the x-th period is obtained and is expressed as follows:
CLx＝CLx1+CLx2
Wherein CL x1 represents a class of cost penalty factors for the x-th period, and CL x2 represents a class of cost penalty factors for the x-th period;
And when the CL x≥CLx-1 is adopted, indicating that the total cost loss factor in the x-th period is not less than the total cost loss factor in the x-1 th period, indicating that all fault points are found, and ending the chip fault diagnosis.
5. The scan chain and combinational logic fault diagnosis method based on cost penalty factors according to claim 4, wherein when CL x<CLx-1, indicating that the total cost penalty factor in the x-th period is not greater than the total cost penalty factor in the x-1 th period, removing the current scan point and redefining the suspicious range and finding the next fault point, determining the rest of target fault points by traversing all scan units until all fault points are queried.
6. The method for diagnosing a fault of a scan chain and combinational logic based on a cost penalty factor according to claim 1, wherein the faulty scan chain is identified by a flushing pattern of several chains, and a fault result different from a predetermined result occurs according to a fault occurring in a part of units of the scan chain or combinational logic during loading or unloading.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1531046A (en) * | 2003-03-14 | 2004-09-22 | 矽统科技股份有限公司 | Fault positioning method for scanning link of logic integrated circuit |
| CN101285871A (en) * | 2008-05-09 | 2008-10-15 | 中国科学院计算技术研究所 | Scanning chain diagnosis vector generation method and device and scanning chain diagnosis method |
| CN101315412A (en) * | 2008-06-12 | 2008-12-03 | 中国科学院计算技术研究所 | Scanning chain fault diagnosis method and system |
| CN101320078A (en) * | 2008-07-04 | 2008-12-10 | 中国科学院计算技术研究所 | Scanning chain fault diagnosis system and method, and diagnosis vector generation apparatus |
| CN101911491A (en) * | 2007-10-31 | 2010-12-08 | 惠瑞捷（新加坡）私人有限公司 | Be used for the number of retention time fault of analyzing scan chains and definite scan chain or the method for position |
| CN102129031A (en) * | 2006-02-17 | 2011-07-20 | 明导公司 | Multi-stage test response compactors |
| CN102221671A (en) * | 2011-03-30 | 2011-10-19 | 中国科学院计算技术研究所 | Signal stability detector and time delay tester |
| JP2013036903A (en) * | 2011-08-09 | 2013-02-21 | Renesas Electronics Corp | Fault spot estimation system, fault spot estimation method and program for fault spot estimation |
| JP2017062222A (en) * | 2015-09-24 | 2017-03-30 | ルネサスエレクトロニクス株式会社 | Test point circuit, scan flip-flop for sequential test, semiconductor device and design device |
| KR101837899B1 (en) * | 2017-04-18 | 2018-03-13 | 연세대학교 산학협력단 | Apparatus and method for diagnosing failure of scan chain |
| CN109444727A (en) * | 2018-09-20 | 2019-03-08 | 北京工业大学 | A kind of low-power consumption LFSR replay kind test compression method towards Scan Design |
| CN111650499A (en) * | 2020-05-29 | 2020-09-11 | Oppo广东移动通信有限公司 | Scanning chain fault diagnosis method and device, test equipment and storage medium |
| CN113454471A (en) * | 2019-03-13 | 2021-09-28 | 美商新思科技有限公司 | Single pass diagnosis for multiple strand defects |
| CN114398848A (en) * | 2022-02-23 | 2022-04-26 | 无锡玖熠半导体科技有限公司 | Test vector generation method and device and storage medium |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7788561B2 (en) * | 2006-08-14 | 2010-08-31 | Yu Huang | Diagnosing mixed scan chain and system logic defects |
-
2023
- 2023-02-10 CN CN202310100980.1A patent/CN116106729B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1531046A (en) * | 2003-03-14 | 2004-09-22 | 矽统科技股份有限公司 | Fault positioning method for scanning link of logic integrated circuit |
| CN102129031A (en) * | 2006-02-17 | 2011-07-20 | 明导公司 | Multi-stage test response compactors |
| CN101911491A (en) * | 2007-10-31 | 2010-12-08 | 惠瑞捷（新加坡）私人有限公司 | Be used for the number of retention time fault of analyzing scan chains and definite scan chain or the method for position |
| CN101285871A (en) * | 2008-05-09 | 2008-10-15 | 中国科学院计算技术研究所 | Scanning chain diagnosis vector generation method and device and scanning chain diagnosis method |
| CN101315412A (en) * | 2008-06-12 | 2008-12-03 | 中国科学院计算技术研究所 | Scanning chain fault diagnosis method and system |
| CN101320078A (en) * | 2008-07-04 | 2008-12-10 | 中国科学院计算技术研究所 | Scanning chain fault diagnosis system and method, and diagnosis vector generation apparatus |
| CN102221671A (en) * | 2011-03-30 | 2011-10-19 | 中国科学院计算技术研究所 | Signal stability detector and time delay tester |
| JP2013036903A (en) * | 2011-08-09 | 2013-02-21 | Renesas Electronics Corp | Fault spot estimation system, fault spot estimation method and program for fault spot estimation |
| JP2017062222A (en) * | 2015-09-24 | 2017-03-30 | ルネサスエレクトロニクス株式会社 | Test point circuit, scan flip-flop for sequential test, semiconductor device and design device |
| KR101837899B1 (en) * | 2017-04-18 | 2018-03-13 | 연세대학교 산학협력단 | Apparatus and method for diagnosing failure of scan chain |
| CN109444727A (en) * | 2018-09-20 | 2019-03-08 | 北京工业大学 | A kind of low-power consumption LFSR replay kind test compression method towards Scan Design |
| CN113454471A (en) * | 2019-03-13 | 2021-09-28 | 美商新思科技有限公司 | Single pass diagnosis for multiple strand defects |
| CN111650499A (en) * | 2020-05-29 | 2020-09-11 | Oppo广东移动通信有限公司 | Scanning chain fault diagnosis method and device, test equipment and storage medium |
| CN114398848A (en) * | 2022-02-23 | 2022-04-26 | 无锡玖熠半导体科技有限公司 | Test vector generation method and device and storage medium |
Non-Patent Citations (2)
| Title |
|---|
| 扫描链故障确定性诊断向量生成算法;王飞 等;《计算机辅助设计与图形学学报》;20090131;第21卷(第1期);6-12 * |
| 王飞 等.扫描链故障确定性诊断向量生成算法.《计算机辅助设计与图形学学报》.2009,第21卷(第1期),6-12. * |
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