CN116093018A - Method for forming metal interconnection structure - Google Patents

Method for forming metal interconnection structure Download PDF

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Publication number
CN116093018A
CN116093018A CN202211431188.6A CN202211431188A CN116093018A CN 116093018 A CN116093018 A CN 116093018A CN 202211431188 A CN202211431188 A CN 202211431188A CN 116093018 A CN116093018 A CN 116093018A
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China
Prior art keywords
copper
forming
layer
copper seed
groove
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Pending
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CN202211431188.6A
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Chinese (zh)
Inventor
董佳莹
谭艳琼
蒙飞
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
Hua Hong Semiconductor Wuxi Co Ltd
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Hua Hong Semiconductor Wuxi Co Ltd
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Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp, Hua Hong Semiconductor Wuxi Co Ltd filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN202211431188.6A priority Critical patent/CN116093018A/en
Publication of CN116093018A publication Critical patent/CN116093018A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application discloses a method for forming a metal interconnection structure, which comprises the following steps: forming a groove in an interlayer dielectric layer, wherein the interlayer dielectric layer is formed on a wafer, and a semiconductor device is integrated on the wafer; forming a barrier layer on the exposed surfaces of the interlayer dielectric layer and the groove; forming a copper seed crystal on the barrier layer; performing heat treatment in a vacuum environment to convert the crystal orientation of copper in the copper seed crystal into [111]; electroplating a copper layer on the copper seed crystal, wherein the copper layer fills the groove; and flattening and removing the barrier layer, the copper seed crystal and the copper layer outside the groove. According to the method, after the groove of the contact through hole is formed in the forming process of the metal interconnection structure, the barrier layer and the copper seed crystal are sequentially formed, and heat treatment is carried out in a vacuum environment, so that the crystal orientation of copper in the copper seed crystal is changed into [111], the grain size of a large copper crystal grain is increased, the square resistance of the large copper crystal grain is reduced, the subsequent filling of an electroplating process is facilitated, and the reliability of a device is improved to a certain extent.

Description

Method for forming metal interconnection structure
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a method for forming a metal interconnection structure.
Background
Currently, the conduction between different metal layers of a semiconductor device is achieved by forming an inter-layer dielectric (ILD) layer between the two metal layers to form a trench filled with a conductive material (e.g., copper (Cu)) and forming a contact hole (via) for conducting the two metal layers. The contact hole technology leads out each electrode of various devices on the substrate to the dielectric layer, and the electrodes of the integrated circuit are led out by utilizing the multilayer metal interconnection so as to facilitate the subsequent encapsulation.
In the related art, a contact hole (for example, a copper (Cu) contact hole) in a metal interconnection structure may be formed by: forming a groove in the interlayer dielectric layer, forming a barrier layer (barrier layer) on the surfaces of the interlayer dielectric layer and the groove, forming a copper seed (Cu seed) on the barrier layer, electroplating the copper seed to form a copper layer to fill the groove, flattening, removing the barrier layer, the copper seed and the copper layer outside the groove, and forming a contact hole by the copper layer in the groove.
Copper seed is typically formed by a physical vapor deposition (physical vapor deposition) process, among other things. However, particles (grain) of copper seed crystals grown by the conventional PVD process cannot sufficiently grow, and sheet resistance (R s ) Higher, thereby influencing the subsequent electroplating process, the reliability of the device is not high.
Disclosure of Invention
The application provides a method for forming a metal interconnection structure, which can solve the problem of low reliability of a device caused by forming a copper seed crystal through a conventional PVD (physical vapor deposition) process in the related art, and comprises the following steps:
forming a groove in an interlayer dielectric layer, wherein the interlayer dielectric layer is formed on a wafer, and a semiconductor device is integrated on the wafer;
forming a barrier layer on the surfaces of the interlayer dielectric layer and the exposed surface of the groove;
forming a copper seed on the barrier layer;
performing heat treatment in a vacuum environment to convert the crystal orientation of copper in the copper seed crystal into [111];
electroplating to form a copper layer on the copper seed crystal, wherein the copper layer fills the groove;
and flattening and removing the barrier layer, the copper seed crystal and the copper layer outside the groove.
In some embodiments, the forming a copper seed on the barrier layer includes:
and forming a copper seed crystal on the barrier layer through a PVD process in a PVD machine.
In some embodiments, the performing the heat treatment in a vacuum environment comprises:
after the copper seed crystal is formed, the wafer is transferred to a gas removal chamber of the PVD machine, and the heat treatment is performed in a vacuum environment.
In some embodiments, the temperature of the heat treatment is 120 degrees celsius to 220 degrees celsius.
In some embodiments, the heat treatment time is 10 seconds to 60 seconds.
In some embodiments, the barrier layer comprises tantalum nitride and/or titanium nitride.
In some embodiments, the copper seed has a thickness greater than 30 nanometers.
The technical scheme of the application at least comprises the following advantages:
in the forming process of the metal interconnection structure, after the groove of the contact through hole is formed, a barrier layer and a copper seed crystal are sequentially formed, and heat treatment is carried out in a vacuum environment, so that the crystal orientation of copper in the copper seed crystal is changed into [111], the grain size of a large copper crystal grain is increased, the square resistance of the copper crystal grain is reduced, the filling of a subsequent electroplating process is facilitated, and the reliability of a device is improved to a certain extent.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method of forming a metal interconnect structure provided in one exemplary embodiment of the present application;
fig. 2 to 7 are schematic diagrams illustrating formation of a metal interconnection structure according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
The crystal orientation of the copper seed crystal grain grown by PVD process is mainly Cu 111, cu 200 and Cu 311, wherein Cu 111 is the crystal lattice direction most favorable for electron migration. Cu 200 and Cu 311 are treated at high temperature to convert into Cu 111 crystal orientation; the high temperature can also enable copper particles to fully grow, the grain boundary is reduced, the square resistance is reduced, and the electroplating process is facilitated; in addition, the particle distribution of the whole copper film layer has obvious correlation with the particles of the copper seed layer, and in view of this, the embodiment of the present application provides a method for forming a metal interconnection structure, which can increase the particle size of large copper grains and reduce the square resistance thereof by heat treatment after the formation of copper seed, and specifically comprises the following steps:
referring to fig. 1, a flowchart illustrating a method for forming a metal interconnection structure according to an exemplary embodiment of the present application is shown, and as shown in fig. 1, the method includes:
step S1, forming a groove in an interlayer dielectric layer, wherein the interlayer dielectric layer is formed on a wafer, and a semiconductor device is integrated on the wafer.
Referring to fig. 2, a schematic cross-sectional view is shown after forming a trench in an interlayer dielectric layer. Illustratively, as shown in fig. 2, an interlayer dielectric layer (including a first interlayer dielectric layer 210 and a second interlayer dielectric layer 220, in which a metal layer 310 is formed) is formed on a wafer (not shown in fig. 2), a semiconductor device (not shown in fig. 2) is integrated on the wafer, etching may be performed through a photolithography process, a trench 201 is formed in the interlayer dielectric layer, and the metal layer 310 at the bottom of the trench 201 is exposed. Wherein the interlayer dielectric layer includes an oxide layer, and the metal layer 310 may include a copper layer.
In fig. 2, a contact hole is formed in the metal layer 310, or may be formed in the semiconductor device, and if a contact hole is formed in the semiconductor device, the bottom of the trench 201 is exposed to be an electrode (for example, a source, a drain, a gate, etc. of the semiconductor device) that needs to be led out of the semiconductor device, and in fig. 2, two trenches 201 are formed to be illustrated as an example, and may actually be one or more than two trenches, which is not limited herein.
And S2, forming a barrier layer on the exposed surfaces of the interlayer dielectric layer and the groove.
Referring to fig. 3, a schematic cross-sectional view is shown after forming a barrier layer. For example, as shown in fig. 3, the barrier layer 321 may include tantalum nitride and/or titanium nitride, and the tantalum nitride layer and/or the titanium nitride layer may be formed by a PVD process to constitute the barrier layer 321.
And S3, forming a copper seed crystal on the barrier layer.
Referring to fig. 4, a schematic cross-sectional view of forming a copper seed is shown. Illustratively, as shown in FIG. 4, a copper seed 322 may be formed on the barrier layer 321 by a PVD process in a PVD station. Wherein the copper seed 322 has a thickness greater than 30 nanometers (nm).
And S4, performing heat treatment in a vacuum environment to convert the crystal orientation of copper in the copper seed crystal into [111].
Referring to fig. 5, a schematic cross-sectional view after heat treatment in a vacuum environment is shown. Illustratively, as shown in FIG. 5, after the copper seed 322 is formed, the wafer is transferred to a gas removal (degus) chamber of a PVD tool and heat treated in a vacuum environment to convert the copper crystal orientation of the copper seed to [111], resulting in a copper seed 3221 having an increased particle size and a reduced sheet resistance. Wherein the temperature of the heat treatment is 120 ℃ to 220 ℃, and the time of the heat treatment is 10 seconds to 60 seconds. As described above, cu 200 and Cu 311 in the copper seed crystal 322 can be converted to Cu 111 crystal orientation by high temperature treatment, and copper particles can be sufficiently grown at high temperature, the grain boundary is reduced, and the sheet resistance is reduced.
And S5, electroplating on the copper seed crystal to form a copper layer, wherein the copper layer fills the groove.
Referring to fig. 6, a schematic cross-sectional view of an electroplated copper layer is shown. Illustratively, as shown in fig. 6, copper layer 323 fills trench 301.
And S6, flattening and removing the barrier layer, the copper seed crystal and the copper layer outside the groove.
Referring to fig. 7, a schematic cross-sectional view is shown after planarization. Illustratively, as shown in fig. 7, planarization may be performed by a chemical mechanical polishing (chemical mechanical polishing, CMP) process to remove the barrier layer 321, copper seed 3221 and copper layer 323 outside of the trench 201, the copper layer 323 within the trench 201 constituting the contact hole.
In summary, in the embodiment of the application, after the trench of the contact through hole is formed in the forming process of the metal interconnection structure, the barrier layer and the copper seed crystal are sequentially formed, and the heat treatment is performed in the vacuum environment, so that the crystal orientation of copper in the copper seed crystal is changed to [111], the grain size of the large copper crystal grain is increased, the square resistance of the large copper crystal grain is reduced, the filling of the subsequent electroplating process is facilitated, and the reliability of the device is improved to a certain extent.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.

Claims (7)

1. A method of forming a metal interconnect structure, comprising:
forming a groove in an interlayer dielectric layer, wherein the interlayer dielectric layer is formed on a wafer, and a semiconductor device is integrated on the wafer;
forming a barrier layer on the surfaces of the interlayer dielectric layer and the exposed surface of the groove;
forming a copper seed on the barrier layer;
performing heat treatment in a vacuum environment to convert the crystal orientation of copper in the copper seed crystal into [111];
electroplating to form a copper layer on the copper seed crystal, wherein the copper layer fills the groove;
and flattening and removing the barrier layer, the copper seed crystal and the copper layer outside the groove.
2. The method of claim 1, wherein forming a copper seed on the barrier layer comprises:
and forming a copper seed crystal on the barrier layer through a PVD process in a PVD machine.
3. The method of claim 2, wherein the performing the heat treatment in a vacuum environment comprises:
after the copper seed crystal is formed, the wafer is transferred to a gas removal chamber of the PVD machine, and the heat treatment is performed in a vacuum environment.
4. A method according to claim 3, wherein the temperature of the heat treatment is 120 degrees celsius to 220 degrees celsius.
5. The method of claim 4, wherein the heat treatment is for a time period of 10 seconds to 60 seconds.
6. The method according to any one of claims 1 to 5, wherein the barrier layer comprises tantalum nitride and/or titanium nitride.
7. The method of claim 6, wherein the copper seed has a thickness greater than 30 nanometers.
CN202211431188.6A 2022-11-14 2022-11-14 Method for forming metal interconnection structure Pending CN116093018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211431188.6A CN116093018A (en) 2022-11-14 2022-11-14 Method for forming metal interconnection structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211431188.6A CN116093018A (en) 2022-11-14 2022-11-14 Method for forming metal interconnection structure

Publications (1)

Publication Number Publication Date
CN116093018A true CN116093018A (en) 2023-05-09

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