CN116092444A - Gate driving circuit, driving method thereof and display panel - Google Patents

Abstract

The invention provides a gate driving circuit, a driving method thereof and a display panel, relates to the technical field of display, and aims to improve the use yield of a transistor and further prolong the service life of the gate driving circuit. The gate driving circuit includes: n rows of shift register units, a frame start signal line, k clock signal lines, and x control sub-circuits; the mth control sub-circuit is respectively coupled with the input end of the mth row shift register unit, the frame start signal line and the mth clock signal line; the m-th clock signal line is coupled to the m-th shift register unit, and a rising edge of a frame start signal transmitted by the frame start signal line is in the same period as a start rising edge of a clock signal transmitted by the first clock signal line, and a falling edge of the frame start signal is in the same period as a falling edge of a first pulse of the clock signal transmitted by the k-th clock signal line.

Description

Gate driving circuit, driving method thereof and display panel

Technical Field

The present invention relates to the field of display technologies, and in particular, to a gate driving circuit, a driving method thereof, and a display panel.

Background

The Gate on Array technology has become the mainstream of the liquid crystal display industry, and can not only improve the utilization rate of the frame, but also reduce the cost to a certain extent. In the display product adopting the technology, the number of the thin film transistors in the layout area of the grid driving circuit is large, different thin film transistors realize different functions, and the functions complement each other, if one or a plurality of thin film transistors are abnormal, the output signal is abnormal, the service life of the grid driving circuit is reduced, the abnormal display of pictures is caused, and the customer satisfaction is influenced.

Therefore, how to improve the usage yield of the transistor and further prolong the service life of the gate driving circuit is a technical problem to be solved.

Disclosure of Invention

The invention aims to provide a gate driving circuit, a driving method thereof and a display panel, which are used for improving the use yield of a transistor and further prolonging the service life of the gate driving circuit.

In order to achieve the above object, the present invention provides the following technical solutions:

a first aspect of the present invention provides a gate driving circuit comprising: n rows of shift register units, n > 4; a frame start signal line, k clock signal lines, k satisfying 4.ltoreq.k < n, and k being an even number; and x control sub-circuits, x=k/2;

the mth control sub-circuit is coupled to the input end of the mth row shift register unit, the frame start signal line and the mth clock signal line, respectively, and is used for: under the control of the frame start signal line, controlling to connect or disconnect the electrical connection between the input end of the m-th row shift register unit and the m-th clock signal line; and/or, under the control of the mth clock signal line, controlling to switch on or off the electrical connection between the input end of the mth row shift register unit and the frame start signal line; m is more than or equal to 1 and less than or equal to x;

The mth clock signal line is coupled to the mth row shift register unit, and a rising edge of a frame start signal transmitted by the frame start signal line is in the same period as a start rising edge of a clock signal transmitted by the first clock signal line, and a falling edge of the frame start signal is in the same period as a falling edge of a first pulse of the clock signal transmitted by the kth clock signal line.

Optionally, the mth control sub-circuit includes: a first control unit and/or a second control unit;

the control end of the first control unit is coupled with the frame start signal line, the input end of the first control unit is coupled with the mth clock signal line, and the output end of the first control unit is coupled with the input end of the mth row shift register unit; for the purpose of: under the control of the frame start signal line, controlling to connect or disconnect the electrical connection between the input end of the m-th row shift register unit and the m-th clock signal line;

the control end of the second control unit is coupled with the mth clock signal line, the input end of the second control unit is coupled with the frame start signal line, and the output end of the second control unit is coupled with the input end of the mth row shift register unit; for the purpose of: and under the control of the m-th clock signal line, controlling to conduct or break the electrical connection between the input end of the m-th row shift register unit and the frame start signal line.

Optionally, the first control unit includes a first transistor, a gate of the first transistor is coupled to the frame start signal line, a first pole of the first transistor is coupled to the mth clock signal line, and a second pole of the first transistor is coupled to an input terminal of the mth row shift register unit.

Optionally, the second control unit includes a second transistor, a gate of the second transistor is coupled to the mth clock signal line, a first pole of the second transistor is coupled to the frame start signal line, and a second pole of the second transistor is coupled to an input terminal of the mth row shift register unit.

Optionally, the mth row shift register unit includes: an input transistor, a pull-up node, an output transistor, a bootstrap capacitor, a first reset transistor and a second reset transistor;

the gate of the input transistor is coupled with the first pole of the input transistor, the first pole of the input transistor is used as the input end of the m-th row shift register unit, and the second pole of the input transistor is coupled with the pull-up node;

the grid electrode of the output transistor is coupled with the pull-up node, the first electrode of the output transistor is coupled with the mth clock signal line, and the second electrode of the output transistor is coupled with the output end of the mth row shift register unit;

The first end of the bootstrap capacitor is coupled with the pull-up node, and the second end of the bootstrap capacitor is coupled with the output end of the m-th row shift register unit;

the grid electrode of the first reset transistor is coupled with the reset signal input end, the first pole of the first reset transistor is coupled with the pull-up node, and the second pole of the first reset transistor is coupled with the first level signal input end;

the grid electrode of the second reset transistor is coupled with the reset signal input end, the first electrode of the second reset transistor is coupled with the output end of the m-th row shift register unit, and the second electrode of the second reset transistor is coupled with the first level signal input end.

Based on the technical scheme of the gate driving circuit, a second aspect of the invention provides a display panel, which comprises the gate driving circuit.

Optionally, the display panel includes: the display device comprises a display area and a peripheral area, wherein the peripheral area comprises a first frame area, a second frame area and a third frame area, the first frame area and the second frame area are oppositely arranged, and the third frame area is positioned on the same side of the first frame area and the second frame area; the display area is positioned between the first frame area and the second frame area;

In the first frame area and/or the second frame area, a first part of a frame start signal line, k clock signal lines and a shift register unit are sequentially arranged along a first direction, and the shift register unit is nearest to the display area;

the second portion of the frame start signal line is located in the third frame region, and the second portion includes at least a portion extending along the first direction.

Optionally, the control sub-circuit included in the gate driving circuit is located between the orthographic projection of the clock signal line on the substrate and the orthographic projection of the shift register unit on the substrate.

Optionally, the gate driving circuit includes a control sub-circuit that is disposed between an orthographic projection of the second portion on the substrate and an orthographic projection of the shift register unit on the substrate.

Optionally, the display panel further includes a signal line group, and the signal line group includes: a clock signal line, a reset signal line, a first level signal line, and a second level signal line;

The gate driving circuit comprises a control sub-circuit which is in orthographic projection on a substrate of the display panel and is positioned between orthographic projection of the second part on the substrate and orthographic projection of the signal line group on the substrate.

Based on the technical scheme of the gate driving circuit, a third aspect of the present invention provides a driving method of the gate driving circuit, for driving the gate driving circuit, the driving method includes:

in the output period of the m-th row shift register unit: the mth control sub-circuit controls and conducts the electric connection between the input end of the mth row shift register unit and the mth clock signal line under the control of the frame start signal line; and/or, the mth control sub-circuit controls and conducts the electric connection between the input end of the mth row shift register unit and the frame start signal line under the control of the mth clock signal line.

Optionally, the mth control sub-circuit includes: a first control unit and/or a second control unit;

in the output period of the m-th row shift register unit:

the first control unit controls and conducts the electric connection between the input end of the m-th row shift register unit and the m-th clock signal line under the control of the frame start signal line; and/or the second control unit controls and conducts the electric connection between the input end of the m-th row shift register unit and the frame start signal line under the control of the m-th clock signal line.

Optionally, the first control unit includes a first transistor, and the second control unit includes a second transistor;

in the output period of the m-th row shift register unit: the first transistor is turned on and/or the second transistor is turned on.

In the technical scheme provided by the invention, the rising edge of the frame start signal transmitted by the frame start signal line is set to be in the same period as the initial rising edge of the clock signal transmitted by the first clock signal line, and the falling edge of the frame start signal is set to be in the same period as the falling edge of the first pulse of the clock signal transmitted by the k/2 clock signal line; so that the start pulse included in the first clock signal line to the k/2 clock signal line can be in the active level period of the frame start signal.

The frame start signal line and the mth clock signal line are respectively coupled with the input end of the mth row shift register unit by arranging the mth control sub-circuit; the mth row shift register unit can be controlled to write the frame start signal and output the gate driving signal only during a period when the frame start signal is at an active level and the clock signal transmitted by the mth clock signal line is at an active level. Therefore, the problem that the pull-up node is high in level for a long time due to the fact that the frame start signal is written in for a long time can not occur in the m-th row shift register unit, the fact that the electrode of the transistor coupled with the pull-up node is in a high-voltage state for a long time is avoided, the use yield of the transistor is improved, and the service life of the grid driving circuit is prolonged.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

FIG. 1 is a circuit diagram of a shift register unit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a layout position of a control sub-circuit according to an embodiment of the present invention;

FIG. 3 is a driving timing diagram of a gate driving circuit corresponding to four clock signal lines in the related art;

FIG. 4 is a driving timing diagram of a gate driving circuit corresponding to ten clock signal lines in the related art;

fig. 5 is a schematic circuit diagram of a control sub-circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating connection of five-element shift register units corresponding to four clock signal lines on a single side according to an embodiment of the present invention;

fig. 7 is a driving timing diagram of a gate driving circuit corresponding to one-side four clock signal lines according to an embodiment of the present invention;

fig. 8 is a driving timing diagram of a gate driving circuit corresponding to ten clock signal lines on a single side according to an embodiment of the present invention;

fig. 9 is a diagram showing a comparison between a transfer curve of a first reset transistor in a normal shift register unit and a transfer curve of a first reset transistor in an abnormal shift register unit according to an embodiment of the present invention.

Detailed Description

In order to further explain the gate driving circuit, the driving method thereof and the display panel provided by the embodiment of the invention, the following detailed description is given with reference to the accompanying drawings.

Based on the technical problems existing in the background technology, the research discovers that:

in the display product adopting the Gate on Array technology, the frame start signal line is directly and electrically connected with the input ends of the first rows of shift register units.

As shown in fig. 1 and 3, taking a single-sided 4 clock signal line as an example, the input ends of the first row shift register unit and the second row shift register unit are both coupled to the frame start signal line, in the shift register unit, the second pole of the input transistor M1 is coupled to the pull-up node PU, and the pull-up node PU is coupled to not only the first pole of the first reset transistor M2 but also the gate of the output transistor M3, to provide the turn-on voltage for the output transistor M3, and the output end of the first row shift register unit, that is, the second pole of the output transistor is coupled to the input end of the third row shift register unit, and the output end of the second row shift register unit is coupled to the input end of the fourth row shift register unit. When the first row shift register unit stops outputting, the first reset transistor M2 in the first row shift register unit discharges the pull-up node PU, and the second reset transistor M4 in the first row shift register unit discharges the output terminal of the first row shift register unit. And by analogy, each level shift register unit can work normally, and the normal display of pictures is ensured.

As shown in fig. 3, when the pull-up node PU in the first row shift register unit is at a high level, the pull-up node PU in the second row shift register unit is also at a high level, but when the first row shift register unit is turned off, the pull-up node PU in the second row shift register unit is still at a high level, the pull-up node PU in the second row shift register unit is kept at a high level longer than the pull-up node PU in the first row shift register unit, and the drain electrode of the first reset transistor M2 in the second row shift register unit is coupled with the pull-up node PU, so that the first reset transistor M2 in the second row shift register unit is under the high voltage signal of the pull-up node PU for a long time, which results in that the device is more easily damaged, greatly reduces the lifetime of the first reset transistor M2, and easily causes related abnormal display. Meanwhile, as the number of single-side clock signal lines of a display product increases, the time that the pull-up node PU of the first few rows of shift register units directly connected with the frame start signal line STV is in a high level is longer, and related problems are more likely to occur.

As shown in fig. 3, the total high voltage holding time of the frame start signal transmitted by the frame start signal line STV is 3H, the total high voltage duration of the clock signals transmitted by the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 in one period is 2H, the duty ratio is 50%, and the frame start signal is advanced by 2H time from the high voltage level of the first clock signal. The frame start signal line STV directly connects the input terminals of the first row shift register unit and the input terminals of the second row shift register unit. Before the high voltage level of the clock signal received by the first row of shift register units arrives, the primary lifting time of the high voltage of the pull-up node PU1 of the first row of shift register units is 2H, and after the high voltage level of the clock signal received by the first row of shift register units arrives, the duration of the secondary lifting of the high voltage of the pull-up node PU1 is 2H (the high voltage duration of the clock signal) due to the bootstrap capacitor C1, namely the total high voltage duration of the pull-up node PU1 of the first row of shift register units is 4H.

Before the high voltage level of the clock signal received by the second row shift register unit arrives, the primary high voltage lifting time of the pull-up node PU2 of the second row shift register unit is 3H, and after the high voltage level of the clock signal received by the second row shift register unit arrives, the duration of the secondary high voltage lifting of the pull-up node PU is 2H (while the high voltage duration of the clock signal) due to the bootstrap capacitor C1, that is, the total high voltage duration of the pull-up node PU2 of the second row shift register unit is 5H.

The first row shift register unit and the second row shift register unit have outputs only when the accessed clock signals are high, so that the output signals (such as Gout1 and Gout 2) are the same as the received clock signals, and the total duration of the high voltages is 2H. The outputs of the first and second shift register units are respectively used as the inputs of the input transistors M1 in the third and fourth shift register units, when the outputs of the first and fourth shift register units are at high level, the pull-up nodes (e.g., PU3 and PU 4) in the third and fourth shift register units maintain the total time of one high-voltage lifting to be 2H, when the clock signal accessed by the line is at high level, the pull-up node maintains the time of two high-voltage lifting to be 2H, i.e., the pull-up node PU3 in the third and the pull-up node PU4 in the fourth shift register unit maintain the high-voltage time to be 4H in total, and the output signals (e.g., gout3 and Gout 4) in the first two lines are only output at high level for 2H.

As shown in fig. 3, when the clock signal transmitted by the first clock signal line CLK1 coupled to the first row shift register unit is at a high level, the clock signal transmitted by the second clock signal line CLK2 coupled to the second row shift register unit is at a low level, but at this time, the pull-up node PU2 in the second row shift register unit is at a high level, and the second row shift register unit does not start to operate until the clock signal transmitted by the second clock signal line CLK2 is at a high level, during this period, the pull-up node PU2 in the second row shift register unit is also always at a high voltage signal, i.e., the drain high voltage time of the first reset transistor M2 in the second row shift register unit is 5H, and the time actually required for operation is 4H. Similarly, as the number of single-side clock signal lines increases, the high voltage time of the pull-up node PU in the last row of shift register units directly connected to the start signal line STV is longer than the high voltage time of the pull-up node PU1 in the first row of shift register units.

If 6 clock signal lines are provided on one side, the pull-up node in the second row shift register unit is higher than the pull-up node in the first row shift register unit by 1H time. The pull-up node in the third row of shift register cells is higher than the pull-up node in the first row of shift register cells by a high level of 2H time.

If 8 clock signal lines are provided on one side, the pull-up node in the second row shift register unit is higher than the pull-up node in the first row shift register unit by 1H time. The pull-up node in the third row of shift register cells is higher than the pull-up node in the first row of shift register cells by a high level of 2H time. The pull-up node in the fourth row of shift register cells is higher than the pull-up node in the first row of shift register cells by a high level of 3H time.

As shown in fig. 4, in the case of setting 10 clock signal lines on a single side, the total high level duration of the frame start signal is 9H, which is 5H on earlier than the high level of the first clock signal line CLK1, the first row of shift register units include the pull-up node PU1 which maintains the high level duration for 10H (the first high voltage lift-up and the 5H high voltage secondary lift-up), the second row of shift register units have the pull-up node PU2 which maintains the high level duration for 11H, the third row of shift register units have the pull-up node PU3 which maintains the high level duration for 12H, the fourth row of shift register units have the pull-up node PU4 which maintains the high level duration for 13H, and the fifth row of shift register units have the pull-up node PU5 which maintains the high level duration for 14H, i.e., the pull-up nodes PU1 of the next rows of shift register units which are directly connected with the frame start signal line STV have the high voltage maintaining times 1 more than the pull-up nodes PU1 by 1H, 2H, 3H, and 4H, respectively, and the times are all in the first high voltage lift-up stage of the pull-up node. However, the high voltage durations of the output signals of the next and previous lines are not different, and only the difference occurs in the frame start signal. Note that, also illustrated in fig. 4 are the timing of the clock signal transmitted by the second clock signal line CLK2, the timing of the clock signal transmitted by the third clock signal line CLK3, the timing of the clock signal transmitted by the fourth clock signal line CLK4, and the timing of the clock signal transmitted by the fifth clock signal line CLK 5.

Because the pull-up node PU is coupled to the drain of the first reset transistor M2, the drain of the first reset transistor M2 in the last several rows of shift register units directly connected to the frame start signal line STV will keep the high voltage signal for a longer time, however, other shift register units in the corresponding row in this stage are not yet turned on, and the service life of the shift register unit to which the first reset transistor M2 belongs will be reduced when the drain keeps the high voltage signal for a long time, which results in abnormal display or cross-stripes easily occurring in the module or reliability experiment process, resulting in yield loss or new product evaluation period growth, and seriously affecting the quality and customer satisfaction of the product.

Taking 17.3QHD Oxide display product as an example, the display product is provided with 10 clock signal lines on a single side, the defect of the display product appears as a regular horizontal stripe (NG line: fifth line/tenth line …) in gray scale, the input of the tenth line is the output of the fifth line, so as to push the foregoing, the fifth line/tenth line … are defects caused by the abnormal output of the fifth line, the waveform confirms that the pull-up node PU and the output signal of the fifth line are both multiple outputs (error charge), and the characteristic abnormality of the first reset transistor M2 in the shift register unit suspected of discharging the pull-up node PU in the line leads to multiple outputs of the pull-up node PU.

As shown in fig. 9, in the same display product, in the OK line shift register unit (L1 curve in the figure)/NG line, that is, in the fifth line shift register unit (L2 curve in the figure), the transfer curve of the first reset transistor M2 is compared, so that it is seen that the NG line is normal when the curve is formed by vg= -30-2.6V, but in the process of vg=2.6-30V, the curve is abnormal and there is a mutation and Drop, ion of the first reset transistor M2 is far smaller than that of the OK line, so that the first reset transistor M2 of the NG line (the fifth line) cannot be normally turned on when the pull-up node PU is discharged, multiple outputs are generated by the pull-up node and the output signal, and cross lines appear. Note that Vg represents the gate voltage of the first reset transistor M2, and Id represents the current of the first reset transistor M2.

For a display product with 10 clock signal lines arranged on one side, the input ends of the first row shift register unit, the second row shift register unit, the third row shift register unit, the fourth row shift register unit and the fifth row shift register unit are all directly connected with the frame start signal line STV, and the time for maintaining the high voltage at the pull-up node PU point of the fifth row shift register unit is longest, so that the risk is highest. Meanwhile, with the continuous upgrading of the product specification, the products with higher resolution and higher refresh rate are more and more, the number of single-side clock signal lines of the products is increased, the time for maintaining high voltage at the pull-up node PU of the first rows of shift register units directly connected with the frame start signal line STV is longer and longer, and the risk of occurrence of transverse stripes is increased.

Solving the above problems is mainly done from two aspects: 1. the high voltage resistance or the large voltage resistance of the shift register unit is improved; 2. the problem that the frame start signal line STV is directly connected with the input ends of a plurality of shift register units is optimized and improved from the aspect of product design. The high voltage resistance or the large voltage resistance of the shift register unit is improved mainly from the aspect of process, and the interface between the film layers, the defects of the film layers and the like are improved, but other problems, such as the reduction of breakdown voltage between the film layers, the left shift of a characteristic curve and other yield or reliability problems, are easy to occur while the high voltage resistance of the shift register unit is often improved. With the mass production of large-scale oxide products, optimization is an optimal choice from the aspect of product design, and the optimization of the design level has smaller requirements on the process Margin.

Referring to fig. 5 to 8, an embodiment of the present invention provides a gate driving circuit, which includes: n rows of shift register units, n > 4; a frame start signal line, k clock signal lines, k satisfying 4.ltoreq.k < n, and k being an even number; and x control sub-circuits 10, x=k/2;

the mth control sub-circuit 10 is coupled to the input terminal IN of the mth row shift register unit, the frame start signal line and the mth clock signal line, respectively, for: under the control of the frame start signal line, controlling to connect or disconnect the electrical connection between the input end IN of the m-th row shift register unit and the m-th clock signal line; and/or, under the control of the mth clock signal line, controlling to turn on or off the electrical connection between the input terminal IN of the mth row shift register unit and the frame start signal line; m is more than or equal to 1 and less than or equal to x;

The mth clock signal line is coupled to the mth row shift register unit, and a rising edge of a frame start signal transmitted by the frame start signal line is in the same period as a start rising edge of a clock signal transmitted by the first clock signal line, and a falling edge of the frame start signal is in the same period as a falling edge of a first pulse of a clock signal transmitted by the kth/2 clock signal line.

The gate driving circuit is applied to a display panel, and the display panel comprises a plurality of rows of sub-pixels, and each row of shift register units is respectively coupled with at least one corresponding row of sub-pixels.

Illustratively, k=4, x=2, and m takes the values 1,2.

Illustratively, k=10, x=5, and m takes the values 1,2,3,4,5.

Notably, n, k, x, m are positive integers.

In the output period of the m-th row shift register unit: the mth control sub-circuit 10 controls and conducts the electric connection between the input end IN of the mth row shift register unit and the mth clock signal line under the control of the frame start signal line; and/or, the mth control sub-circuit 10 controls and turns on the electrical connection between the input terminal IN of the mth row shift register unit and the frame start signal line under the control of the mth clock signal line.

In one mode, in the non-output period of the mth row shift register unit: the mth control sub-circuit 10 controls to disconnect the electrical connection between the input end IN of the mth row shift register unit and the mth clock signal line under the control of the frame start signal line; and/or, the mth control sub-circuit 10 controls to disconnect the electrical connection between the input terminal IN of the mth row shift register unit and the frame start signal line under the control of the mth clock signal line.

In another manner, in the non-output period of the mth row shift register unit: the mth control sub-circuit 10 controls and turns on the electrical connection between the input terminal IN of the mth row shift register unit and the mth clock signal line under the control of the frame start signal line, but at this time, the signal transmitted by the mth clock signal line is at an inactive level, such as a low level; alternatively, the mth control sub-circuit 10 controls and turns on the electrical connection between the input terminal IN of the mth row shift register unit and the frame start signal line under the control of the mth clock signal line, but at this time, the signal transmitted by the frame start signal line is at an inactive level, such as a low level.

Taking k=4 as an example, the first clock signal line is coupled to the first row shift register unit, the second clock signal line is coupled to the second row shift register unit, the third clock signal line is coupled to the third row shift register unit, and the fourth clock signal line is coupled to the fourth row shift register unit. The first clock signal line is coupled to the fifth row of shift register cells, the second clock signal line is coupled to the sixth row of shift register cells, and so on.

Illustratively, the mth row shift register unit is a shift register unit directly connected to the frame start signal line. The inputs of the x+1-th row shift register cell to the n-th row shift register cell are provided by the outputs of the shift register cells preceding them.

Illustratively, the high voltage of the frame start signal and the clock signal are Vgh and the low voltage is Vgl.

It should be noted that the side of the display panel where the data line is coupled to the chip is referred to as DP side, and the side opposite to DP is referred to as DPO side. The mth row shift register cells may be distributed on the DPO side.

It should be noted that, as shown IN fig. 5 and 6, the frame start signal transmitted by the frame start signal line STV is provided by the driving chip IN the display panel, and the control sub-circuit 10 finally outputs a new frame start signal STV' to the input terminal IN of the shift register unit.

According to the specific structure of the gate driving circuit, in the gate driving circuit provided by the embodiment of the invention, by setting the rising edge of the frame start signal transmitted by the frame start signal line, the rising edge of the frame start signal is in the same period as the rising edge of the clock signal transmitted by the first clock signal line, and the falling edge of the frame start signal is in the same period as the falling edge of the first pulse of the clock signal transmitted by the k/2 clock signal line; so that the start pulse included in the first clock signal line to the k/2 clock signal line can be in the active level period of the frame start signal.

The mth control sub-circuit 10 is respectively coupled with the input end IN of the mth row shift register unit, the frame start signal line and the mth clock signal line; the mth row shift register unit can be controlled to write the frame start signal and output the gate driving signal only during a period when the frame start signal is at an active level and the clock signal transmitted by the mth clock signal line is at an active level. Therefore, the problem that the pull-up node is high in level for a long time due to the fact that the frame start signal is written in for a long time can not occur in the m-th row shift register unit, the fact that the electrode of the transistor coupled with the pull-up node is in a high-voltage state for a long time is avoided, the use yield of the transistor is improved, and the service life of the grid driving circuit is prolonged.

As shown in fig. 5 and 6, in some embodiments, the mth control sub-circuit 10 includes: a first control unit 101 and/or a second control unit 102;

the control end of the first control unit 101 is coupled to the frame start signal line STV, the input end of the first control unit 101 is coupled to the mth clock signal line CLK, and the output end of the first control unit 101 is coupled to the input end IN of the mth row shift register unit; for the purpose of: under the control of the frame start signal line, controlling to connect or disconnect the electrical connection between the input end IN of the m-th row shift register unit and the m-th clock signal line;

the control end of the second control unit 102 is coupled to the mth clock signal line CLK, the input end of the second control unit 102 is coupled to the frame start signal line STV, and the output end of the second control unit 102 is coupled to the input end IN of the mth row shift register unit; for the purpose of: under the control of the mth clock signal line, the electrical connection between the input terminal IN of the mth row shift register unit and the frame start signal line is controlled to be turned on or off.

In the output period of the m-th row shift register unit:

The first control unit 101 controls and turns on the electrical connection between the input terminal IN of the mth row shift register unit and the mth clock signal line under the control of the frame start signal line; and/or, the second control unit 102 controls and turns on the electrical connection between the input terminal IN of the mth row shift register unit and the frame start signal line under the control of the mth clock signal line.

As shown IN fig. 5 and 6, IN some embodiments, the first control unit 101 includes a first transistor T1, a gate of the first transistor T1 is coupled to the frame start signal line STV, a first pole of the first transistor T1 is coupled to the mth clock signal line CLK, and a second pole of the first transistor T1 is coupled to the input terminal IN of the mth row shift register unit.

IN some embodiments, the second control unit 102 includes a second transistor T2, a gate of the second transistor T2 is coupled to the mth clock signal line CLK, a first pole of the second transistor T2 is coupled to the start of frame signal line STV, and a second pole of the second transistor T2 is coupled to the input terminal IN of the mth row shift register unit.

In the output period of the m-th row shift register unit: the first transistor T1 is turned on and the second transistor T2 is turned on.

As shown in fig. 1, in some embodiments, the mth row shift register cell includes: an input transistor M1, a pull-up node, an output transistor M3, a bootstrap capacitor C1, a first reset transistor M2 and a second reset transistor M4;

the gate of the input transistor M1 is coupled to the first pole of the input transistor M1, the first pole of the input transistor M1 is used as the input terminal IN of the M-th row shift register unit, and the second pole of the input transistor M1 is coupled to the pull-up node;

the gate of the output transistor M3 is coupled to the pull-up node PU, the first pole of the output transistor M3 is coupled to the mth clock signal line CLK, and the second pole of the output transistor M3 is coupled to the output terminal Out of the mth row shift register unit;

the first end of the bootstrap capacitor C1 is coupled with the pull-up node, and the second end of the bootstrap capacitor C1 is coupled with the output end Out of the m-th row shift register unit;

the gate of the first Reset transistor M2 is coupled to the Reset signal input terminal Reset, the first pole of the first Reset transistor M2 is coupled to the pull-up node, and the second pole of the first Reset transistor M2 is coupled to the first level signal input terminal Vss;

The gate of the second Reset transistor M4 is coupled to the Reset signal input terminal Reset, the first pole of the second Reset transistor M4 is coupled to the output terminal Out of the mth row shift register unit, and the second pole of the second Reset transistor M4 is coupled to the first level signal input terminal Vss.

It is noted that the shift register unit is not limited to the above-described structure, and may include a pull-up unit, a pull-down unit, and a plurality of reset units in the related art.

IN more detail, as shown IN fig. 5 and 6, the gate of the first transistor T1 receives a frame start signal, the drain receives a clock signal, the gate of the second transistor T2 receives a clock signal, the drain receives a frame start signal, and the sources of the first transistor T1 and the second transistor T2 provide an input signal to the input terminal IN of the shift register unit. For example, when the frame start signal is at a high level, the first transistor T1 is turned on and the second transistor T2 is turned off, but the clock signal received by the drain of the first transistor T1 is at a low level, and both the first transistor T1 and the second transistor T2 output a low level; when the frame start signal and the clock signal are both at high level, the first transistor T1 and the second transistor T2 are both turned on, and the first transistor T1 and the second transistor T2 both output high level; when the frame start signal is at a low level and the clock signal is at a high level, the first transistor T1 is turned off, the second transistor T2 is turned on, but the drain of the second transistor T2 is at a low level, and the first transistor T1 and the second transistor T2 are output at a low level; when the frame start signal and the clock signal are both low, the first transistor T1 and the second transistor T2 are both turned off.

As shown in fig. 5 and 6, the black dots in fig. 6 indicate that the traces are electrically connected. In fig. 6, taking a product with 4 clock signal lines on a single side as an example, for the first row shift register unit and the second row shift register unit, a new frame start signal STV' is output as an input of the input transistor M1 by the actions of the frame start signal and the clock signal through the first transistor T1 and the second transistor T2, the clock signal is output as the drain of the output transistor M3 to ensure the output of the shift register unit, and the output of the first row shift register unit and the output of the second row shift register unit can be respectively input as the third row shift register unit and the fourth row shift register unit, thereby enabling the display panel to display normally.

It should be noted that fig. 6 illustrates a cascade connection of five-row shift register units GOA, where the Reset signal input Reset of the third row GOA is coupled to the output of the sixth row shift register unit, and receives the output signal Gout of the sixth row shift register unit. The Reset signal input terminal Reset of the fourth row GOA receives the output signal Gout of the seventh row shift register unit. The Reset signal input terminal Reset of the fifth row GOA receives the output signal Gout of the eighth row shift register unit.

As shown in fig. 7, the frame start signal in the related art is designed to be a high level of 3H (as in the related art STV), and the frame start signal is turned on high in advance of the time of the high level 2H of the clock signal transmitted by the first clock signal line CLK 1; the high level time of the frame start signal and the related technology in the invention are kept unchanged and are all 3H time (such as STV in the invention), but the high level starting time sequence is delayed by 2H time compared with the related technology, namely, the high level of the frame start signal and the high level of the clock signal transmitted by the first clock signal line CLK1 are started simultaneously; since the clock signal transmitted by the first clock signal line CLK1 and the clock signal transmitted by the second clock signal line CLK2 have a high level duration of 2H and overlap of the 1H time high voltage signal, the clock signal high voltage transmitted by the second clock signal line CLK2 and the frame start signal high voltage end at the same time.

As shown IN fig. 7, the signal (e.g., STV 1) received at the input terminal IN of the first row shift register unit is at a high level only during the first period of the clock signal transmitted by the first clock signal line CLK1, and the rest of the time is at a low level; the signal (e.g., STV 2) received at the input IN of the second row shift register unit is at a high level only during the first period of the clock signal transmitted by the second clock signal line CLK2, and the rest of the time is at a low level. Compared with the related art, the waveforms of the signals received by the input end IN of the first row shift register unit and the signals received by the input end IN of the second row shift register unit only keep the high voltage signal 2H time, namely the high voltage signal time of the pull-up node is only 2H time (such as PU1 and PU2 of the invention), which is far lower than the high voltage signal time 4H/5H time of the pull-up node IN the first row shift register unit and the pull-up node IN the second row shift register unit (such as PU1 and PU2 of the related art), the embodiment of the invention has the advantages that the high voltage time of the pull-up node IN the first row shift register unit accounts for 50%, the high voltage time of the pull-up node IN the second row shift register unit accounts for 40%, the load pressure of the first reset transistor M2 is far reduced, and the service life of the first reset transistor M2 is greatly prolonged.

Meanwhile, the actual gate driving signal output waveforms of the first row shift register unit and the second row shift register unit have no obvious difference from the related art, in addition, the tube of the input transistor M1 is relatively small, the Ion level is better, ion normalization is more than 10 microamps, the threshold voltages of the input transistor M1 and the output transistor M3 are small, and only between 1V and 3V are needed for opening, namely, the opening and filling time is short, the abnormal problem of the gate driving signal waveform output caused by insufficient pre-filling time is avoided, and the picture can be normally displayed.

As shown in fig. 8, the frame start signal in the related art is designed to be at a high level of 9H (e.g., the related art STV), and is turned on at a high level in advance of the time of the high level 5H of the clock signal supplied from the first clock signal line CLK 1; in the embodiment of the invention, the high level time of the frame start signal is 9H (as STV of the invention) as same as that of the related art, but the high level start time sequence is delayed by 5H time compared with that of the related art, namely, the high level of the frame start signal and the high level of the clock signal transmitted by the first clock signal line CLK1 are started simultaneously; since the clock signal transmitted by the second clock signal line CLK2 lags the timing of the clock signal transmitted by the first clock signal line by 1H time, the clock signal transmitted by the third clock signal line CLK3 lags the timing of the clock signal transmitted by the second clock signal line CLK2 by 1H time, the clock signal transmitted by the fourth clock signal line CLK4 lags the timing of the clock signal transmitted by the third clock signal line CLK3 by 1H time, and the clock signal transmitted by the fifth clock signal line CLK5 lags the timing of the clock signal transmitted by the first clock signal line CLK1 by 4H time, the total duration of the high voltage of the frame start signal is 9H, so the high voltage of the clock signal transmitted by the fifth clock signal line CLK5 and the high voltage of the frame start signal (e.g., STV) are ended simultaneously.

The waveforms of the input signals received by the first five-row shift register units are kept for 5H time (such as STV1 to STV5 of the invention), namely, in the first five-row shift register units, the high voltage signal time of the pull-up node is 5H time (such as PU1 to PU5 of the invention) which is far lower than the high voltage signal time of 10H/11H/12H/13H/14H of the pull-up node in each shift register unit in the related art, the high voltage time of the pull-up node in the first row shift register unit is only half of the high voltage time before, the high voltage time of the pull-up node in the fifth row shift register unit is only 36 percent before, the high voltage time ratio of the pull-up node in other row shift register units is between the two (between 36 and 50 percent), the load pressure of the first reset transistor M2 is greatly reduced, and the service life of the first reset transistor M2 is greatly prolonged. Meanwhile, as the number of single-side clock signal lines is increased, the high-voltage time duty ratio of the pull-up node is lower, the load capacity of the first reset transistor M2 unit is smaller, the risk of the service life of the shift register unit is reduced, the product quality and the yield are improved, and the product market competitiveness is also enhanced.

It should be noted that, in the technical scheme provided by the invention, the control sub-circuit 10 is controlled and output by adding the control sub-circuit 10 and skillfully utilizing the frame start signal and the clock signal, and the time sequence of the frame start signal is adjusted, so that when each row of shift register units starts to work, only the input signal and the pull-up node of the row of shift register units are high level, the input signal and the pull-up node of other row of shift register units are low level, and the high level time of the pull-up node of each row of shift register units is obviously shortened (the front-back ratio is 36% -50%) compared with the related art, thereby improving the service life reduction condition of devices caused by long-time high level of the pull-up node, improving the product yield and the satisfaction degree of market clients, and improving the product quality and the market competitiveness.

In the gate driving circuit provided in the embodiment of the present invention, the number of the first control unit 101 and the second control unit 102 is not limited, and may be one or more.

In addition, in the gate driving circuit provided by the embodiment of the invention, the high voltage of the pull-up node is mainly mentioned for a long time, the service life of the first reset transistor M2 is reduced, but the pull-up node is also used as the drain electrode of other noise reduction units for the shift register unit architecture model of different products, so that the service life of a certain transistor (such as the first reset transistor M2) is not limited to be prolonged, the high voltage time of the pull-up node is essentially reduced, and the loss of the shift register unit is reduced.

The embodiment of the invention also provides a display panel, which comprises the grid driving circuit provided by the embodiment.

The display panel can be applied to a display device, and the display device can be: any product or component with display function such as a television, a display, a digital photo frame, a mobile phone, a tablet personal computer and the like, wherein the display device further comprises a flexible circuit board, a printed circuit board, a backboard and the like.

In the gate driving circuit provided in the above embodiment, by setting the rising edge of the frame start signal transmitted by the frame start signal line, the rising edge of the frame start signal is in the same period as the initial rising edge of the clock signal transmitted by the first clock signal line, and the falling edge of the frame start signal is in the same period as the falling edge of the first pulse of the clock signal transmitted by the kth/2 clock signal line; so that the start pulse included in the first clock signal line to the k/2 clock signal line can be in the active level period of the frame start signal. The mth control sub-circuit 10 is respectively coupled with the input end IN of the mth row shift register unit, the frame start signal line and the mth clock signal line; the mth row shift register unit can be controlled to write the frame start signal and output the gate driving signal only during a period when the frame start signal is at an active level and the clock signal transmitted by the mth clock signal line is at an active level. Therefore, the problem that the pull-up node is high in level for a long time due to the fact that the frame start signal is written in for a long time can not occur in the m-th row shift register unit, the fact that the electrode of the transistor coupled with the pull-up node is in a high-voltage state for a long time is avoided, the use yield of the transistor is improved, and the service life of the grid driving circuit is prolonged.

The display panel provided by the embodiment of the invention has the same beneficial effects when the gate driving circuit is included, and the description is omitted here.

As shown in fig. 2, in some embodiments, the display panel includes: a display area and a peripheral area, wherein the peripheral area comprises a first frame area 21 and a second frame area which are oppositely arranged, and a third frame area 23 positioned on the same side of the first frame area 21 and the second frame area; the display area is located between the first frame area 21 and the second frame area;

in the first frame area 21 and/or the second frame area, a first portion 31 of a frame start signal line, k clock signal lines and a shift register unit are sequentially arranged along a first direction, the shift register unit being closest to the display area;

the second portion 32 of the frame start signal line is located in the third frame area 23, and the second portion 32 includes at least a portion extending along the first direction.

Illustratively, the peripheral area surrounds the display area, the peripheral area includes a first frame area 21, a second frame area, a third frame area 23, and a fourth frame area, the first frame area 21 includes a left frame of the display panel, the second frame area includes a right frame of the display panel, the third frame area 23 includes an upper frame of the display panel, and the fourth frame includes a lower frame of the display panel.

For example, the display panel is provided with a single-side gate driving circuit or a double-side gate driving circuit, and when double-side gate driving is provided, the gate driving circuits are provided on both the left frame and the right frame of the display substrate.

Illustratively, the frame initiation signal line includes a first portion 31 and a second portion 32 coupled together, at least a portion of the first portion 31 extending in a second direction, at least a portion of the second portion 32 extending in a first direction, the first direction intersecting the second direction. Illustratively, the first direction includes a transverse direction and the second direction includes a longitudinal direction, but is not limited thereto.

Illustratively, the first portion 31 is disposed in a different layer than the second portion 32.

By adopting the layout mode, the layout space can be occupied minimally, and the layout difficulty can be reduced.

As shown in fig. 2, in some embodiments, the gate driving circuit includes a control sub-circuit 10 that is disposed between the front projection of the clock signal line on the substrate and the front projection of the shift register unit GOA on the substrate (e.g., A2 region).

The clock signal line and the shift register unit GOA have a larger layout space therebetween, and the above arrangement can reduce the layout difficulty of the control sub-circuit 10. Furthermore, the control sub-circuit 10 needs to be coupled to the frame start signal line, the clock signal line and the shift register unit GOA, which is advantageous for better electrical connection.

As shown in fig. 2, in some embodiments, the gate driving circuit includes a control sub-circuit 10 that is disposed between an orthographic projection of the second portion 32 on the substrate and an orthographic projection of the shift register unit GOA on the substrate (e.g., A3 region).

The second portion 32 and the shift register unit GOA have a larger layout space therebetween, and the above arrangement can reduce the layout difficulty of the control sub-circuit 10. Furthermore, the control sub-circuit 10 needs to be coupled to the frame start signal line, the clock signal line and the shift register unit GOA, which is advantageous for better electrical connection.

As shown in fig. 2, in some embodiments, the display panel further includes a signal line group 40, and the signal line group 40 includes: a clock signal line, a reset signal line, a first level signal line, and a second level signal line;

the gate drive circuit includes a control sub-circuit 10 that is in front of the display panel on the substrate, between the front projection of the second portion 32 on the substrate and the front projection of the signal line group 40 on the substrate (e.g., area A1).

Illustratively, the first level signal line includes a VGH line and the second level signal line includes a VGL line, but is not limited thereto.

The second portion 32 and the signal line group 40 have a larger layout space therebetween, and the above arrangement can reduce the layout difficulty of the control sub-circuit 10. Furthermore, the control sub-circuit 10 needs to be coupled to the frame start signal line, the clock signal line and the shift register unit, which is advantageous for better electrical connection.

In the display panel, the layout of the control sub-circuit 10 uses the existing layout space, and does not affect the frame of the display panel.

The embodiment of the invention also provides a driving method of the gate driving circuit, which is used for driving the gate driving circuit provided by the embodiment, and comprises the following steps:

in the output period of the m-th row shift register unit: the mth control sub-circuit controls and conducts the electric connection between the input end of the mth row shift register unit and the mth clock signal line under the control of the frame start signal line; and/or, the mth control sub-circuit controls and conducts the electric connection between the input end of the mth row shift register unit and the frame start signal line under the control of the mth clock signal line.

By adopting the driving method provided by the embodiment of the invention to drive the grid driving circuit, the m-th row shift register unit can be controlled to write the frame start signal and output the grid driving signal only in the period that the frame start signal is in an effective level and the clock signal transmitted by the m-th clock signal line is in an effective period. Therefore, the problem that the pull-up node is high in level for a long time due to the fact that the frame start signal is written in for a long time can not occur in the m-th row shift register unit, the fact that the electrode of the transistor coupled with the pull-up node is in a high-voltage state for a long time is avoided, the use yield of the transistor is improved, and the service life of the grid driving circuit is prolonged.

In some embodiments, the mth control sub-circuit includes: a first control unit and/or a second control unit;

in the output period of the m-th row shift register unit:

the first control unit controls and conducts the electric connection between the input end of the m-th row shift register unit and the m-th clock signal line under the control of the frame start signal line; and/or the second control unit controls and conducts the electric connection between the input end of the m-th row shift register unit and the frame start signal line under the control of the m-th clock signal line.

In some embodiments, the first control unit comprises a first transistor and the second control unit comprises a second transistor;

in the output period of the m-th row shift register unit: the first transistor is turned on and/or the second transistor is turned on.

The signal line extending in a certain direction means that: the signal line includes a main portion and a sub portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends in a certain direction, and a length of the main portion extending in the certain direction is greater than a length of the sub portion extending in other directions.

In the method embodiments of the present invention, the serial numbers of the steps are not used to define the sequence of the steps, and it is within the scope of the present invention for those skilled in the art to change the sequence of the steps without performing any creative effort.

In this specification, all embodiments are described in a progressive manner, and identical and similar parts of the embodiments are all referred to each other, and each embodiment is mainly described in a different way from other embodiments. In particular, for the method embodiments, since they are substantially similar to the product embodiments, the description is relatively simple, and reference is made to the section of the product embodiments for relevant points.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected," "coupled," or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

In the description of the above embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (13)

1. A gate driving circuit, comprising: n rows of shift register units, n > 4; a frame start signal line, k clock signal lines, k satisfying 4.ltoreq.k < n, and k being an even number; and x control sub-circuits, x=k/2;

the mth control sub-circuit is coupled to the input end of the mth row shift register unit, the frame start signal line and the mth clock signal line, respectively, and is used for: under the control of the frame start signal line, controlling to connect or disconnect the electrical connection between the input end of the m-th row shift register unit and the m-th clock signal line; and/or, under the control of the mth clock signal line, controlling to switch on or off the electrical connection between the input end of the mth row shift register unit and the frame start signal line; m is more than or equal to 1 and less than or equal to x;

The mth clock signal line is coupled to the mth row shift register unit, and a rising edge of a frame start signal transmitted by the frame start signal line is in the same period as a start rising edge of a clock signal transmitted by the first clock signal line, and a falling edge of the frame start signal is in the same period as a falling edge of a first pulse of the clock signal transmitted by the kth clock signal line.

2. The gate drive circuit of claim 1, wherein the mth control sub-circuit comprises: a first control unit and/or a second control unit;

the control end of the first control unit is coupled with the frame start signal line, the input end of the first control unit is coupled with the mth clock signal line, and the output end of the first control unit is coupled with the input end of the mth row shift register unit; for the purpose of: under the control of the frame start signal line, controlling to connect or disconnect the electrical connection between the input end of the m-th row shift register unit and the m-th clock signal line;

the control end of the second control unit is coupled with the mth clock signal line, the input end of the second control unit is coupled with the frame start signal line, and the output end of the second control unit is coupled with the input end of the mth row shift register unit; for the purpose of: and under the control of the m-th clock signal line, controlling to conduct or break the electrical connection between the input end of the m-th row shift register unit and the frame start signal line.

3. The gate driving circuit according to claim 2, wherein the first control unit comprises a first transistor, a gate of the first transistor is coupled to the frame start signal line, a first pole of the first transistor is coupled to the mth clock signal line, and a second pole of the first transistor is coupled to an input terminal of the mth row shift register unit.

4. The gate driving circuit according to claim 2, wherein the second control unit includes a second transistor, a gate of the second transistor is coupled to an mth clock signal line, a first pole of the second transistor is coupled to the frame start signal line, and a second pole of the second transistor is coupled to an input terminal of an mth row shift register unit.

5. The gate driving circuit according to any one of claims 1 to 4, wherein the mth row shift register unit includes: an input transistor, a pull-up node, an output transistor, a bootstrap capacitor, a first reset transistor and a second reset transistor;

the gate of the input transistor is coupled with the first pole of the input transistor, the first pole of the input transistor is used as the input end of the m-th row shift register unit, and the second pole of the input transistor is coupled with the pull-up node;

The grid electrode of the output transistor is coupled with the pull-up node, the first electrode of the output transistor is coupled with the mth clock signal line, and the second electrode of the output transistor is coupled with the output end of the mth row shift register unit;

the first end of the bootstrap capacitor is coupled with the pull-up node, and the second end of the bootstrap capacitor is coupled with the output end of the m-th row shift register unit;

the grid electrode of the first reset transistor is coupled with the reset signal input end, the first pole of the first reset transistor is coupled with the pull-up node, and the second pole of the first reset transistor is coupled with the first level signal input end;

the grid electrode of the second reset transistor is coupled with the reset signal input end, the first electrode of the second reset transistor is coupled with the output end of the m-th row shift register unit, and the second electrode of the second reset transistor is coupled with the first level signal input end.

6. A display panel comprising the gate driving circuit according to any one of claims 1 to 5.

7. The display panel of claim 6, wherein the display panel comprises: the display device comprises a display area and a peripheral area, wherein the peripheral area comprises a first frame area, a second frame area and a third frame area, the first frame area and the second frame area are oppositely arranged, and the third frame area is positioned on the same side of the first frame area and the second frame area; the display area is positioned between the first frame area and the second frame area;

In the first frame area and/or the second frame area, a first part of a frame start signal line, k clock signal lines and a shift register unit are sequentially arranged along a first direction, and the shift register unit is nearest to the display area;

the second portion of the frame start signal line is located in the third frame region, and the second portion includes at least a portion extending along the first direction.

8. The display panel of claim 7, wherein the gate drive circuit includes a control sub-circuit that is forward projected onto a substrate of the display panel between a forward projection of the clock signal line onto the substrate and a forward projection of the shift register unit onto the substrate.

9. The display panel of claim 7, wherein the gate drive circuit comprises a control sub-circuit that is in front of a projection of the second portion onto a substrate of the display panel, between a front projection of the second portion onto the substrate, and a front projection of the shift register unit onto the substrate.

10. The display panel of claim 7, further comprising a signal line group, the signal line group comprising: a clock signal line, a reset signal line, a first level signal line, and a second level signal line;

The gate driving circuit comprises a control sub-circuit which is in orthographic projection on a substrate of the display panel and is positioned between orthographic projection of the second part on the substrate and orthographic projection of the signal line group on the substrate.

11. A driving method of a gate driving circuit, characterized by being used for driving the gate driving circuit according to any one of claims 1 to 5, comprising:

in the output period of the m-th row shift register unit: the mth control sub-circuit controls and conducts the electric connection between the input end of the mth row shift register unit and the mth clock signal line under the control of the frame start signal line; and/or, the mth control sub-circuit controls and conducts the electric connection between the input end of the mth row shift register unit and the frame start signal line under the control of the mth clock signal line.

12. The driving method of the gate driving circuit according to claim 11, wherein the mth control sub-circuit includes: a first control unit and/or a second control unit;

in the output period of the m-th row shift register unit:

the first control unit controls and conducts the electric connection between the input end of the m-th row shift register unit and the m-th clock signal line under the control of the frame start signal line; and/or the second control unit controls and conducts the electric connection between the input end of the m-th row shift register unit and the frame start signal line under the control of the m-th clock signal line.

13. The method according to claim 12, wherein the first control unit includes a first transistor, and wherein the second control unit includes a second transistor;

in the output period of the m-th row shift register unit: the first transistor is turned on and/or the second transistor is turned on.

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