CN116088289A

CN116088289A - System clock calibration method, device, equipment and storage medium

Info

Publication number: CN116088289A
Application number: CN202211387467.7A
Authority: CN
Inventors: 贾杨洁
Original assignee: Shanghai Pudong Development Bank Co Ltd
Current assignee: Shanghai Pudong Development Bank Co Ltd
Priority date: 2022-11-07
Filing date: 2022-11-07
Publication date: 2023-05-09

Abstract

The invention discloses a system clock calibration method, a device, equipment and a storage medium. The method comprises the following steps: acquiring time sequence frequency difference data of a system clock in a locking state; wherein the lock state is a state in which a satellite reference clock signal is received; the time sequence frequency difference data consists of a plurality of frequency differences related to time; training a set prediction model based on the time sequence frequency difference data; calibrating the system clock in a holding state based on the trained set prediction model; wherein the hold state is a state in which the satellite reference clock signal is not received. By the technical scheme of the invention, the system clock in the holding state can be calibrated, and the accuracy of the system clock is ensured.

Description

System clock calibration method, device, equipment and storage medium

Technical Field

The embodiment of the invention relates to the technical field of clock calibration, in particular to a system clock calibration method, device, equipment and storage medium.

Background

The financial business transaction is various, complex and frequent, the ecologically stable and strict operation of the information system is ensured, the technical loopholes and the possible business disputes caused by the time inconsistency in the information flow process are avoided, and the high-precision time synchronization is an effective guarantee for the operation of the banking system.

The global navigation satellite system (Global Navigation Satellite System, GNSS) time service technology and clock equipment provide powerful guarantee for time unification, standardization and automation of the financial industry, especially for remote off-site situations. The constant-temperature crystal oscillator (Oven Controlled Crystal Oscillator, OCXO) serving as a common clock source cannot be independently applied to the fields of high-precision time service, time keeping, navigation positioning and the like. The taming and maintaining of the oven controlled crystal oscillator by using Global Navigation Satellite System (GNSS) signals is a main approach to solve this problem. However, the satellite signal is affected by electromagnetic interference, climate, etc. during transmission, so that the receiver cannot receive the satellite signal, and once the satellite signal is lost, the OCXO in a non-calibration state can only drift along with its own characteristics, and the accuracy of the crystal oscillator cannot be ensured.

Disclosure of Invention

The embodiment of the invention provides a system clock calibration method, a device, equipment and a storage medium, which can calibrate a system clock in a holding state and ensure the accuracy of the system clock.

According to an aspect of the present invention, there is provided a system clock calibration method, including:

acquiring time sequence frequency difference data of a system clock in a locking state; wherein the lock state is a state in which a satellite reference clock signal is received; the time sequence frequency difference data consists of a plurality of frequency differences related to time;

Training a set prediction model based on the time sequence frequency difference data;

calibrating the system clock in a holding state based on the trained set prediction model; wherein the hold state is a state in which the satellite reference clock signal is not received.

Optionally, acquiring timing frequency difference data of the system clock in a locked state includes:

acquiring a satellite clock reference signal and a corresponding system clock signal to be tested;

determining a time interval between the satellite clock reference signal and the system clock signal under test;

and determining the frequency difference based on the time interval, and obtaining time sequence frequency difference data.

Optionally, training the set prediction model based on the time sequence frequency difference data includes:

filtering the time sequence frequency difference data;

normalizing the time sequence frequency difference data after the filtering treatment;

training the set prediction model based on the time sequence frequency difference data of the normalization processing.

splitting the time sequence frequency difference data into training data and test data;

respectively inputting the first time sequences corresponding to the training data into a set prediction model, and outputting first prediction time sequence data;

Training the set prediction model based on the first prediction timing data and the training data;

and verifying the trained set prediction model based on the test data.

Optionally, verifying the trained set prediction model based on the test data includes:

respectively inputting the second time sequences corresponding to the test data into a trained set prediction model, and outputting second prediction time sequence data;

determining a verification coefficient between the second predicted timing data and the test data;

and verifying the trained set prediction model according to the verification coefficient.

Optionally, calibrating the system clock in the hold state based on the trained set prediction model includes:

acquiring time information in a holding state;

inputting the time information into the set prediction model, and outputting a prediction frequency difference;

and calibrating the system clock according to the predicted frequency difference.

According to another aspect of the present invention, there is provided a system clock calibration apparatus, comprising:

the time sequence frequency difference data acquisition module is used for acquiring time sequence frequency difference data of the system clock in a locking state; wherein the lock state is a state in which a satellite reference clock signal is received; the time sequence frequency difference data consists of a plurality of frequency differences related to time;

The model training module is used for training a set prediction model based on the time sequence frequency difference data;

the clock calibration module is used for calibrating the system clock in the holding state based on the trained set prediction model; wherein the hold state is a state in which the satellite reference clock signal is not received.

According to another aspect of the present invention, there is provided an electronic apparatus including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the system clock calibration method of any one of the embodiments of the present invention.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute a system clock calibration method according to any embodiment of the present invention.

The invention obtains the time sequence frequency difference data of the system clock in the locking state; wherein the lock state is a state in which a satellite reference clock signal is received; the time sequence frequency difference data consists of a plurality of frequency differences related to time; training a set prediction model based on the time sequence frequency difference data; calibrating the system clock in a holding state based on the trained set prediction model; wherein the hold state is a state in which the satellite reference clock signal is not received. By the technical scheme of the invention, the system clock in the holding state can be calibrated, and the accuracy of the system clock is ensured.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a system clock calibration method according to a first embodiment of the present invention;

fig. 2 is an exemplary diagram of a filtering result obtained by filtering time-frequency difference data according to the first embodiment of the present invention;

FIG. 3 is a flowchart of a system clock calibration method according to a second embodiment of the present invention;

FIG. 4 is a graph showing an exemplary aging trend of time-series frequency difference data according to a second embodiment of the present invention;

FIG. 5 is a diagram illustrating a comparison of predicted output and expected output according to a second embodiment of the present invention;

fig. 6 is an exemplary diagram of a variation curve of frequency accuracy of an OCXO provided according to the second embodiment of the present invention in an out-of-lock state and without using a holding technique;

fig. 7 is an exemplary graph of a variation curve of OCXO frequency accuracy when a hold technique is used for a crystal oscillator according to the second embodiment of the present invention;

FIG. 8 is a schematic diagram of a system clock calibration device according to a third embodiment of the present invention;

fig. 9 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example 1

Fig. 1 is a flowchart of a system clock calibration method according to an embodiment of the present invention, where the method is applicable to calibration of a system clock of a financial service, and the method may be performed by a system clock calibration device, and specifically includes the following steps:

step 110, acquiring time sequence frequency difference data of the system clock in a locked state.

Wherein the lock state may be a state in which a satellite reference clock signal is received; the timing frequency offset data may be composed of a plurality of frequency offsets related to time. The satellite reference clock signal may be understood as a signal from a global navigation satellite system (PPS). The global navigation satellite system in this embodiment may be a satellite reference clock signal transmitted at a set frequency. In this embodiment, the Beidou receiver may receive a 1PPS signal with high long-term average accuracy and stability, that is, a satellite reference clock signal, as a base reference source of the system. The state in which the satellite reference clock signal can be normally received in this embodiment may be referred to as a lock state. The system clock in this embodiment may be a bank information system clock. The time-series frequency difference data may be understood as time-series frequency difference data having a chronological order. In this embodiment, a timing frequency difference signal of the system clock in a locked state may be obtained.

In this embodiment, optionally, acquiring timing frequency difference data of the system clock in the locked state includes: acquiring a satellite clock reference signal and a corresponding system clock signal to be tested; determining a time interval between the satellite clock reference signal and the system clock signal under test; and determining the frequency difference based on the time interval, and obtaining time sequence frequency difference data.

The system clock signal to be tested can be understood as a clock signal obtained by testing the clock source of the oven controlled crystal oscillator (Oven Controlled Crystal Oscillator, OCXO). The system clock signal under test in this embodiment may correspond to a satellite clock reference signal. The time interval may be the time interval between the satellite clock reference signal and the system clock signal under test. The frequency offset may be determined from the time interval. The frequency difference is determined based on the time interval in the embodiment, and can be obtained through the existing calculation mode.

Under the effective condition of the second pulse signal, a high-precision time interval measurement technology can be adopted to compare the reference source 1PPS signal with the OCXO signal of the measured source, the time interval between the two signals is measured, the time interval data is converted into a voltage value for controlling the frequency output of the OCXO through a series of calculations, the OCXO is output near the reference source, the state is a locking state, frequency difference data are required to be saved when the time interval is converted into frequency difference, so that a plurality of frequency difference data, namely time sequence frequency difference data, can be obtained, then the time sequence frequency history data in the locking state can be analyzed, an OCXO aging relation model can be established, the time sequence frequency aging characteristic is estimated and compensated, and accordingly, the holding capability can be automatically realized when the reference signal is lost, namely, the frequency value of the crystal oscillator can be correspondingly and automatically adjusted.

In this embodiment, a satellite clock reference signal and a corresponding system clock signal to be tested may be obtained, a time interval between the satellite clock reference signal and the system clock signal to be tested may be determined, and then a frequency difference may be determined based on the time interval, so as to obtain timing frequency difference data. By the arrangement, time sequence frequency difference data can be acquired, and training of a set prediction model can be facilitated.

And step 120, training a set prediction model based on the time sequence frequency difference data.

The set prediction model may be a neural network model that is preset to predict data. In this embodiment, the set prediction model may be used to predict the frequency difference data corresponding to the time point in the time-series frequency difference data. In this embodiment, the set prediction model may be trained based on the time-series frequency difference data.

In this embodiment, optionally, training the set prediction model based on the time-series frequency difference data includes: filtering the time sequence frequency difference data; normalizing the time sequence frequency difference data after the filtering treatment; training the set prediction model based on the time sequence frequency difference data of the normalization processing.

The filtering processing can process the time sequence frequency difference data by adopting the existing filtering function processing mode. In this embodiment, noise interference caused by short-term instability exists in an aging drift curve of the constant-temperature crystal oscillator frequency formed by connecting time sequence frequency difference data, so that curve fluctuation is large, and therefore, data needs to be filtered in advance, and a filtering algorithm is adopted to filter out the influence of high-frequency noise, so as to smooth the frequency aging curve.

An exemplary diagram of a filtering result obtained by filtering time-frequency difference data in this embodiment is shown in fig. 2, where the horizontal axis is time, the unit may be minutes, and the vertical axis may be frequency difference data. In this embodiment, the crystal oscillator frequency difference data may be filtered by invoking a Savitzky-Golay filter in Origin software to filter the influence of noise on crystal oscillator aging, where the window function size may be set to be 5, as shown in fig. 2, and one of the curves is a filtered result curve.

The normalization processing may be performed on the time-series frequency difference data after the filtering processing. Specifically, the normalization process may be understood as a process of converting the time-series frequency difference data after the filtering process to between 0 and 1, and eliminating the order-of-magnitude difference. In this embodiment, the set prediction model may be trained based on the time-series frequency difference data of the normalization process.

In this embodiment, filtering processing may be performed on the time-series frequency difference data, normalization processing may be performed on the time-series frequency difference data after the filtering processing, and then training may be performed on the set prediction model based on the time-series frequency difference data after the normalization processing. Through the arrangement, the data can be subjected to filtering processing and normalization processing, noise interference can be eliminated, order-of-magnitude difference can be eliminated, and the estimation accuracy of the training model is improved.

And 130, calibrating the system clock in a holding state based on the trained set prediction model.

Wherein the hold state may be a state in which the satellite reference clock signal is not received. The state in which the satellite reference clock signal is not received in this embodiment may be referred to as a hold state. Calibration may be understood as calibrating a system clock. In this embodiment, the system clock in the hold state may be calibrated based on the trained set prediction model.

In this embodiment, optionally, calibrating the system clock in the hold state based on the trained set prediction model includes: acquiring time information in a holding state; inputting the time information into the set prediction model, and outputting a prediction frequency difference; and calibrating the system clock according to the predicted frequency difference.

The time information may be understood as time information of the current system clock in a state where the satellite reference clock signal is not received. The prediction frequency difference may be data that sets the prediction model output. In this embodiment, the time information may be input to the set prediction model, so that the predicted frequency difference data may be output.

In this embodiment, the system clock may be calibrated according to the predicted frequency difference by calculating a voltage value that controls the frequency output of the system clock signal according to the frequency difference, and then controlling the output data of the system clock according to the calculated voltage value, so as to calibrate the system clock.

In this embodiment, time information in a holding state may be acquired, and the time information may be input into a set prediction model to output a prediction frequency difference, and then the system clock may be calibrated according to the prediction frequency difference. By the arrangement, when the satellite reference clock signal is not received, the system clock can be calibrated according to the output data of the set prediction model, so that the accuracy of the system clock is ensured.

Example two

Fig. 3 is a flowchart of a system clock calibration method according to a second embodiment of the present invention, which is optimized based on the above embodiment. The concrete optimization is as follows: training a set prediction model based on the timing frequency difference data, including: splitting the time sequence frequency difference data into training data and test data; respectively inputting the first time sequences corresponding to the training data into a set prediction model, and outputting first prediction time sequence data; training the set prediction model based on the first prediction timing data and the training data; and verifying the trained set prediction model based on the test data. As shown in fig. 3, the method of this embodiment specifically includes the following steps:

step 310, acquiring time sequence frequency difference data of the system clock in a locked state.

Wherein the lock state may be a state in which a satellite reference clock signal is received; the timing frequency offset data may be composed of a plurality of frequency offsets related to time.

Step 320, splitting the time sequence frequency difference data into training data and test data.

Wherein the training data may be used for training data for setting a predictive model. The test data may be used for testing data for setting the predictive model. When the test data is input in this embodiment, the predicted value and the expected value may be output. In this embodiment, the time sequence frequency difference data may be split into training data and test data.

Step 330, the first time sequences corresponding to the training data are respectively input into a set prediction model, and the first prediction time sequence data are output.

The first time series corresponding to the training data can be input into a set prediction model for output by the first prediction time series data. The training data in this embodiment may include a plurality of time series data.

In this embodiment, the first time series corresponding to the training data may be input into the set prediction model, so as to output the first prediction time series data.

Step 340, training the set prediction model based on the first prediction time sequence data and the training data.

In this embodiment, the set prediction model may be trained on the training data pair based on the first prediction timing data.

Illustratively, the set prediction model may be a BP neural network model. In order to facilitate data processing, the BP neural network model in this embodiment may use the first point of each crystal oscillator frequency data as a reference frequency value of the crystal oscillator, and then subtract the first data from each frequency value to obtain frequency difference data, where the initial frequency difference is always 0. And sending the processed data into a BP neural network model, fitting crystal oscillator aging data by using the BP neural network, selecting time as an independent variable and frequency difference as a dependent variable, dividing the original time sequence frequency difference data into training data and test data, wherein the training data is used for training the network model, and the test data can output a predicted value and an expected value, so that whether the fitting result of the test network meets the requirement is judged.

In this embodiment, the processed time sequence frequency difference data may be split into training data and test data. Before the predictive neural network model is set for training, the input and output data are required to be put in the same magnitude for training, namely normalization processing is carried out, both training data and pre-estimated data are required to be converted into 0 and 1 so as to eliminate magnitude difference, and the BP neural network construction stage is carried out after the data normalization processing. According to the embodiment, the number of nodes of each layer of a network can be determined according to the characteristics of fitted frequency data, the network structure is determined according to the characteristics of time sequence frequency difference data of the constant-temperature crystal oscillator, because the data to be fitted is the time-varying relation of the constant-temperature crystal oscillator frequency, the time sequence data is determined as input, the data is output as the predicted OCXO frequency difference data, the established BP network structure is 1 input node, 1 output node and a single layer is selected by a hidden layer, and the training speed is slow and the phenomenon of overfitting is caused by too many layers. The hidden layer node of the model may be determined by the data point, for example, the number of the current node is 3, if the training data is increased, the hidden layer node may be further increased, and the weight and the threshold are initialized by using random numbers. The excitation function of the hidden layer of the BP neural network is usually a Sigmoid function, and the transfer function adopted by the hidden layer in this embodiment is a tanh function. In this embodiment, training the BP neural network with training data after the model construction is completed, estimating the output result of the test data with the trained model after the training is completed, inversely normalizing the output data into normal data, comparing the normal data with the expected output, and judging whether the verification model is good or bad by calculating the judgment coefficient.

And 350, verifying the trained set prediction model based on the test data.

The verification may be a verification step performed on the test data input by the trained set prediction model. In this embodiment, the trained set prediction model may be validated based on the test data.

In this embodiment, optionally, verifying the trained set prediction model based on the test data includes: respectively inputting the second time sequences corresponding to the test data into a trained set prediction model, and outputting second prediction time sequence data; determining a verification coefficient between the second predicted timing data and the test data; and verifying the trained set prediction model according to the verification coefficient.

The second prediction time series data may be data obtained by inputting a second time series corresponding to the test data into the trained set prediction model. The verification coefficient may be a verification coefficient between the second predicted time series data and the test data. The verification coefficients may include at least one of a residual sum of squares coefficient, a correlation coefficient, and a chi-square coefficient. If the verification coefficient is adopted, the judgment condition for the model can be as follows: when the verification coefficient is the residual square sum coefficient and the chi-square coefficient, the difference value between the residual square sum coefficient and the chi-square coefficient and 0 is smaller than a first set threshold value; when the verification coefficient is the correlation coefficient, the difference between the correlation system and 1 can be judged to be smaller than a second set threshold value; the first set threshold and the second set threshold can be set according to actual requirements.

In this embodiment, a constant temperature crystal oscillator may be selected, the collected frequency difference data is divided into two parts of training data and test data, a prediction model, such as a BP neural network model, is set for fitting and predicting, and the predicted result is compared with the actual data, where an example of the aging trend of the OCXO of the time-series frequency difference data is shown in fig. 4, and an example of the comparison of the predicted output and the expected output of the prediction model is shown in fig. 5. In this embodiment, the BP neural network model may be determined by a verification system, for example, a residual square sum coefficient, a correlation coefficient and a chi-square coefficient, and specifically, the closer the residual square sum and the chi-square coefficient are to 0, the closer the correlation coefficient is to 1, which indicates that the fitting value is closer to the measured value, and the determination coefficient result of the crystal oscillator is as shown in table 1 below.

TABLE 1 determination results of BP neural network model

In this embodiment, the second time sequences corresponding to the test data may be respectively input into the trained set prediction model to output the second prediction time sequence data, and then the verification coefficient between the second prediction time sequence data and the test data is determined, and the trained set prediction model may be verified according to the verification coefficient. Through the arrangement, the model can be verified through the verification coefficient, so that whether the model meets the requirement or not can be judged, and the accuracy of setting the prediction model can be conveniently determined.

And step 360, calibrating the system clock in the holding state based on the trained set prediction model.

Wherein the hold state may be a state in which the satellite reference clock signal is not received.

By way of example, in the technical scheme in this embodiment, when determining that the beidou 1PPS signal is lost, at this time, the OCXO does not have a reference clock to perform tame and calibration, the output frequency may drift with time increase and temperature change, the accuracy of the constant-temperature crystal oscillator frequency may decrease, a hold mode is started, the frequency drift model of the constant-temperature crystal oscillator is estimated based on the OCXO frequency trained by the historical data accumulated in the tame state, the frequency output variation trend of the constant-temperature crystal oscillator is estimated, the actual output frequency is compensated by using the estimated value, and the frequency accuracy of the OCXO is improved. And after the satellite second pulse signal is recovered, restarting the disciplining mode, performing disciplining on the constant-temperature crystal oscillator again, and repeating the two processes to ensure that the accuracy of the output frequency of the OCXO in the disciplining mode and the maintaining mode can be within a certain range. In the test process, after the OCXO is tamed by the Beidou 1PPS signal for a period of time and OCXO frequency data enough to train a model are stored, an antenna device of a receiver is pulled out, the system judges that the 1PPS signal is lost, a holding mode is started, and the data are compensated by adopting a holding technology, namely, the data of a system clock are calibrated by adopting the technical scheme of the embodiment.

FIG. 6 is a graph showing an example of a change in frequency accuracy of an OCXO in an out-of-lock state without using a hold technique, with the hold time on the horizontal axis and the hold mode entered at 0s, and the vertical axisThe axis is the frequency accuracy of the OCXO, and the frequency enters a stable state because the OCXO is already operated for 100 hours, but the frequency accuracy of the OCXO is still continuously and slowly reduced at the moment, and the worst frequency accuracy reaches 5 multiplied by 10 ^-11 And there is a large fluctuation. FIG. 7 is a graph showing an example of a change in OCXO frequency accuracy when the hold technique is used 3 days after taming a crystal oscillator, with significantly improved output frequency accuracy over the hold, and with a constant temperature crystal oscillator frequency accuracy maintained at 1.5X10 during the first 8 hours after 1PPS signal loss ^-11 The frequency accuracy gradually worsens with the increase of time, but the overall can meet the index that the time keeping precision reaches +/-1.728 mu s within 24 hours after the tame.

In this embodiment, for the situation after the satellite signal is lost, the set prediction model is adopted to complete fitting on the aging drift of the OCXOs, and the frequency output is estimated according to the fitting result, so that the estimation precision of the crystal oscillator is improved, the corresponding model is not required to be built for each OCXO, the problem of better fitting on the constant-temperature crystal oscillator with irregular drift trend is solved, and the time precision of the financial system is effectively improved. In addition, the system of the embodiment also constructs a network delay calculation module. Specifically, after the time of the clock source is acquired, the time synchronization server is required to synchronize the acquired standard time to the user terminal, and a certain time delay is generated in the process. The network delay calculation module can solve the problem, acquire standard time from the time service module, reduce time delay and provide accurate time service for users. The network delay calculation module in the system calculates the time difference between the network and the user, and calculates the delay value of each system after substituting each delay value, and dynamically adjusts the bandwidth, so that the time difference of the information received by each system is smaller. And the system of the embodiment can also construct a fault handling fault tolerant module. Wherein the fault may be in hardware, a timer, or a software design. In the embodiment, the key components of the system all adopt a double-machine hot backup technology, when the host machine fails, the equipment can be automatically switched to the standby machine in a short time, and the standby machine temporarily replaces the host machine to work, so that the high reliability of the system is ensured. Faults are classified as permanent (hard) or temporary faults. The permanent fault can be solved by replacing hardware, if the system has temporary fault, when the standby machine works, the system needs to allocate more networks to store resources and incline to the fault point, so that the fault of the system is solved.

The invention obtains the time sequence frequency difference data of the system clock in the locking state; wherein the lock state is a state in which a satellite reference clock signal is received; the time sequence frequency difference data consists of a plurality of frequency differences related to time; splitting the time sequence frequency difference data into training data and test data; respectively inputting the first time sequences corresponding to the training data into a set prediction model, and outputting first prediction time sequence data; training the set prediction model based on the first prediction timing data and the training data; verifying the trained set prediction model based on the test data; calibrating the system clock in a holding state based on the trained set prediction model; wherein the hold state is a state in which the satellite reference clock signal is not received. By the technical scheme of the invention, the system clock in the holding state can be calibrated, and the accuracy of the system clock is ensured.

Example III

Fig. 8 is a schematic structural diagram of a system clock calibration device according to a third embodiment of the present invention, where the device can execute the system clock calibration method according to any embodiment of the present invention, and the device has functional modules and beneficial effects corresponding to the execution method. As shown in fig. 8, the apparatus includes:

A timing frequency difference data acquisition module 810, configured to acquire timing frequency difference data of the system clock in a locked state; wherein the lock state is a state in which a satellite reference clock signal is received; the time sequence frequency difference data consists of a plurality of frequency differences related to time;

a model training module 820 for training a set prediction model based on the time-series frequency difference data;

a clock calibration module 830, configured to calibrate the system clock in the hold state based on the trained set prediction model; wherein the hold state is a state in which the satellite reference clock signal is not received.

Optionally, the timing frequency difference data acquisition module is specifically configured to:

Optionally, the model training module 820 is specifically configured to:

filtering the time sequence frequency difference data;

Optionally, the model training module 820 includes:

the data splitting unit is used for splitting the time sequence frequency difference data into training data and test data;

the first prediction time sequence data output unit is used for respectively inputting the first time sequences corresponding to the training data into a set prediction model and outputting first prediction time sequence data;

the model training unit is used for training the set prediction model based on the first prediction time sequence data and the training data;

and the model verification unit is used for verifying the trained set prediction model based on the test data.

Optionally, the model verification unit is configured to:

Optionally, the clock calibration module 830 is configured to:

acquiring time information in a holding state;

The device can execute the method provided by all the embodiments of the invention, and has the corresponding functional modules and beneficial effects of executing the method. Technical details not described in detail in this embodiment can be found in the methods provided in all the foregoing embodiments of the invention.

Example IV

Fig. 9 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention. The electronic device 10 is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 9, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 may also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the system clock calibration method.

In some embodiments, the system clock calibration method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. One or more of the steps of the system clock calibration method described above may be performed when the computer program is loaded into RAM 13 and executed by processor 11. Alternatively, in other embodiments, the processor 11 may be configured to perform the system clock calibration method in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A system clock calibration method, comprising:

2. The method of claim 1, wherein obtaining timing frequency offset data of the system clock in the locked state comprises:

3. The method of claim 1, wherein training a set prediction model based on the timing frequency difference data comprises:

filtering the time sequence frequency difference data;

4. A method according to claim 1 or 3, wherein training a set prediction model based on the timing frequency difference data comprises:

And verifying the trained set prediction model based on the test data.

5. The method of claim 4, wherein validating the trained set prediction model based on the test data comprises:

6. The method of claim 1, wherein calibrating the system clock in a hold state based on the trained set prediction model comprises:

acquiring time information in a holding state;

7. A system clock calibration device, comprising:

8. The apparatus of claim 7, wherein the timing frequency offset data acquisition module is specifically configured to:

9. An electronic device, the electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the system clock calibration method of any one of claims 1-6.

10. A computer readable storage medium storing computer instructions for causing a processor to perform the system clock calibration method of any one of claims 1-6.