CN116072174A - VCMA-STT MTJ memory cell and memory method - Google Patents

VCMA-STT MTJ memory cell and memory method Download PDF

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Publication number
CN116072174A
CN116072174A CN202211656274.7A CN202211656274A CN116072174A CN 116072174 A CN116072174 A CN 116072174A CN 202211656274 A CN202211656274 A CN 202211656274A CN 116072174 A CN116072174 A CN 116072174A
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China
Prior art keywords
vcma
layer
voltage
mtj
free layer
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CN202211656274.7A
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Chinese (zh)
Inventor
崔岩
罗军
杨美音
许静
贺晓东
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North Ic Technology Innovation Center Beijing Co ltd
Institute of Microelectronics of CAS
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North Ic Technology Innovation Center Beijing Co ltd
Institute of Microelectronics of CAS
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Priority to CN202211656274.7A priority Critical patent/CN116072174A/en
Publication of CN116072174A publication Critical patent/CN116072174A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention relates to a memory cell and a memory method of a VCMA-STT MTJ, wherein the memory cell of the VCMA-STT MTJ comprises: a plurality of VCMA-STT MTJ devices; a drive circuit configured to apply a voltage to the device, including applying a first voltage to regulate a critical switching current of a free layer of the MTJ; and applying a second voltage to regulate and control the magnetic moment direction of the MTJ free layer. According to the invention, the switching of the device in VCMA and STT modes is realized through voltage regulation, the gating switch and the storage function of the storage device are realized, a 1T-1R storage structure in the prior art is replaced, the process complexity of integration with CMOS is avoided, and the method has a larger scientific research use value in the realization of a specific small-scale prototype storage array.

Description

VCMA-STT MTJ memory cell and memory method
Technical Field
The invention relates to the field of semiconductors, in particular to a memory cell and a memory method of a VCMA-STT MTJ.
Background
The memory is one of core chips in the field of integrated circuits, and is an indispensable module in various electronic products.
Magnetic Random Access Memory (MRAM) is a promising memory technology due to its nonvolatile data storage, fast read and write speeds, and low power consumption. The nonvolatile memory function of MRAM devices is provided by Magnetic Tunnel Junction (MTJ) devices. The memory cell of the MRAM is a transistor and a magnetic tunnel junction (1T-1R). The magnetic tunnel junction structure may include a free layer, a tunnel barrier isolation layer, and a pinned layer. The magnetization state of the pinned layer is fixed by the pinning layer. The magnetization direction of the free layer can be switched relative to the pinned layer between two different directions, which generally correspond to a magnetic "parallel" state and a magnetic "anti-parallel" state, respectively. The relative orientation of the magnetizations of the pinned and free layers determines the current resistance of the MTJ device. MTJ devices may exhibit lower resistance when the free layers are in a parallel state and higher resistance when the free layers are in an anti-parallel state. The Tunnel Magnetoresistance Ratio (TMR) is a measure of the MTJ resistance difference between the parallel and anti-parallel states.
The voltage-controlled magnetic anisotropic magnetic random access memory (voltage controlled magnetic anisotropy magnetic random accessmemory, VCMA-MRAM) can quickly control the magnetization direction by changing an external voltage, namely an electric field, so that ohmic loss caused by current is effectively reduced, and the voltage-controlled magnetic anisotropic magnetic random access memory has the remarkable characteristics of high writing speed and low writing power consumption, and is expected to become a main flow nonvolatile memory of the next generation. The magnetization direction of the MTJ free layer is regulated and controlled through voltage, so that data storage is realized.
The MTJ employed by the mainstream MeRAM today is erased by utilizing its spin transfer torque STT (spin transfer torque) characteristic. In such a MeRAM array, programming of the MTJ is mainly achieved by means of the polarity of the voltage applied across the positive and negative electrodes of the MTJ. As shown in fig. 2, when a positive voltage is applied, the resistance of the MTJ may be reduced, and when a negative voltage is applied, the MTJ resistance may be increased. When the stored data is read, the method converts the resistance distinction into voltage or current distinction by utilizing the characteristic that MTJs in different states have different resistance values. The difference between the resistance of the reference resistor and the resistance of the MTJ is converted into voltage or current signal difference through a reading circuit by reasonably designing the resistance of the reference resistor, and then the voltage or current signal difference is compared with the corresponding storage value through a sense amplifier.
There is a new type of MeRAM technology based on voltage controlled magnetic anisotropy VCMA (Voltage Controlled Magnetic Anisotropy) effect MTJ fabrication. It differs from STT primarily in that it uses pulses through the MTJ voltage instead of polarity to change the resistance characteristics of the MTJ. Specifically, after a voltage pulse is applied to the MTJ for a certain period of time, the resistance characteristics of the MTJ change, i.e., the original high resistance changes to low resistance, and the original low resistance changes to high resistance. VCMA has the advantages of effectively reducing programming time and improving the working speed of the memory. The programming modes are different, so the design modes of the peripheral control circuits are also different
However, all memory cells of the current memory adopt a structure of a transistor-memory element (1T-1R), wherein the transistor mainly acts as a gating switch, so that the memory element can be independently controlled, and the crosstalk problem in the access process, particularly the erroneous writing caused by the crosstalk in the writing process, is avoided. The structure integration needs to use the front-path and back-path integration technologies of CMOS respectively, and the process steps are complex; and the structure is compatible with three-dimensional integration and cannot be expanded to the technical field of 3D-ICs in the future.
Disclosure of Invention
Aiming at the technical problems, the invention discloses a VCMA-STT MTJ device structure as a storage element, which is a novel nonvolatile magnetic random access memory based on VCMA effect, wherein the STT-MRAM is used for realizing information writing through spin current, replaces a storage unit with a 1T-1R structure in the prior art, enables a VCMA-STT MTJ device to be switched between VCMA and STT modes through voltage regulation, and is equivalent to a gating switch when the device works in the VCMA mode, namely the vertical anisotropy of an MTJ free layer CoFeB can be regulated by the voltage; when the device works in the STT mode, the data writing of the free layer can be realized through current; when the two electrodes are used simultaneously, V1 modulates the perpendicular anisotropic energy of the free layer CoFeB through the action of an electric field, and V2 realizes the information writing of STT.
The invention adopts the following technical scheme:
a memory cell of a VCMA-STT MTJ, comprising:
a plurality of VCMA-STT MTJ memory devices;
a drive circuit configured to apply a voltage to the memory device, including applying a first voltage to regulate a critical switching current of a free layer of the MTJ; and applying a second voltage to regulate and control the magnetic moment direction of the MTJ free layer.
The storage method of the storage unit comprises the following specific steps:
a. memory device switch gating
Through voltage regulation and control of one bit line, by applying different bias voltages, when a high bias voltage is applied, the magnetization flip current of the free layer is increased, and when a low bias voltage is applied, the magnetization flip current of the free layer is reduced, namely the memory device is in a VCMA mode, so that the gating switching function of the magnetic memory device is realized;
b. storage information writing
Through voltage regulation of another bit line, the magnetic moment direction of the free layer is regulated to regulate the resistance value of the magnetic tunnel junction, namely the storage device is in STT mode, so that writing of storage information is realized.
Compared with the prior art, the invention has the beneficial technical effects that: according to the invention, the switching of the device in VCMA and STT modes is realized through voltage regulation, the gating switch and the storage function of the storage device are realized, a 1T-1R storage structure in the prior art is replaced, the process complexity of integration with CMOS is avoided, and the method has a larger scientific research use value in the realization of a specific small-scale prototype storage array.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures.
FIG. 1 is a process flow diagram of the fabrication of a device structure of the VCMA-STT MTJ of the present invention.
FIG. 2 is a schematic diagram of a memory cell of the VCMA-STT MTJ of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.
Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
In the present embodiment, a memory cell and a memory method of a VCMA-STT MTJ are provided, the memory cell is composed of a plurality of memory devices and a driving circuit, see FIG. 2. FIG. 1 is a schematic diagram of a manufacturing process of a memory device of the VCMA-STT MTJ of the present invention, the memory device of the VCMA-STT MTJ specifically includes:
depositing a pinned layer 101-1 by using magnetron sputtering to deposit a core-magnetic tunnel junction 101 of an MRAM memory device, wherein the pinned layer 101-1 adopts CoFeB with a thickness ranging from 1nm to 1.5nm in one embodiment; then depositing an isolation layer 101-2, wherein in one embodiment the isolation layer 101-2 is MgO, and has a thickness in the range of 0.8-1nm; finally, the free layer 101-3 is deposited, and in one embodiment the free layer 101-3 is formed using CoFeB in a thickness range of 1-1.5nm.
And growing a dielectric layer 102 above the free layer 101-3 by magnetron sputtering, wherein the dielectric layer is made of MgO and has a thickness ranging from 2 nm to 5nm.
And processing the formed CoFeB/MgO/CoFeB/MgO structure into a plurality of cylinders with the diameter of 100nm through exposure and etching processes to form a memory device array.
An exposure overlay is performed on the dielectric layer 102 of each memory device, and the top layer of the dielectric layer 102 is exposed to form a photoresist region 103 with a diameter of 50 nm. The dielectric layer 102 is etched using the photoresist region 103 as a mask, and the dielectric layer 102 is etched into a region having a diameter of 50 nm. The photoresist region 103 is then etched away. An insulating dielectric fill is then performed around dielectric layer 102 to form insulating layer 104 such that insulating layer 104 completely surrounds dielectric layer 102, the insulating dielectric being SiN or SiO in one embodiment 2 。
Through a perforation technique, a perforation is performed from the top down on the insulating layer 105, the perforation connects the dielectric layer 102 and the free layer 101-3, respectively, and a conductive metal is deposited in the perforation, and in this embodiment, au is used as the conductive metal to form the electrode one 105-1 and the electrode two 105-2, respectively.
Thus, the preparation of the VCMA-STT MTJ memory device is completed.
The plurality of VCMA-STT MTJ memory devices are connected to a drive circuit, which may include a plurality of bit lines and a plurality of word lines. Each memory device is connected between a corresponding two bit lines and a word line, wherein electrode one 105-1 and electrode two 105-2 of the VCMA-STT MTJ memory device are respectively connected to the two bit lines, electrode one 105-1 is connected to voltage V1, electrode two 105-2 is connected to voltage V2, the pinned layer 101-1 is connected to the word line, and the word line is typically grounded. In this way, a single memory device for reading and writing is selected by controlling the word line voltage.
The mechanism of action of voltage-modulated magnetic anisotropy (VCMA) is that an electric field applied across the MTJ causes accumulation of electron charges, resulting in changes in interface atomic orbitals and density of states, and thus changes in interface magnetic anisotropy. When current flows through the pinned layer, the current will be polarized to form spin polarized current, when the polarized current flows through the very thin isolation layer, to ensure high polarization (i.e. the thickness of the isolation layer must be less than the spin coherence length λsd, ensuring that the original spin polarization direction can be maintained after electrons pass through the isolation layer, the spin coherence length being the distance the spin electrons travel before the spin direction is reversed, during coherent transmission, the spin electrons will undergo N collisions of variable momentum whose average distance of momentum coherent collisions is λ, whose magnitude is estimated by the fermi speed of the spin electrons and the spin reversal time), the spin polarized electrons can transfer their spin angular momentum to the free layer, changing the magnetization equilibrium state of the free layer.
Spin electrons transfer spin momentum to the magnetic moment of the free layer, causing the magnetic moment of the spin magnetic layer to change direction after gaining spin momentum, a process known as spin transfer torque. The magnetic moment of the free layer is inverted by inputting current into the free layer, so that the resistance state of the magnetic tunnel junction is changed, and data writing is realized.
VCMA is used for carrying out structural adjustment on a magnetic memory device in the process of magnetization inversion of a free layer caused by normal current, and applying different bias voltages in the process of inversion, when a high bias voltage is applied, the magnetization inversion current of the free layer is increased, when a low bias voltage is applied, the magnetization inversion current of the free layer is reduced, in other words, the gating switching effect of the magnetic memory device can be realized through VCMA, meanwhile, the current density required by magnetization inversion can be obviously reduced while the magnetic memory device is realized, the size of the device is further reduced, and meanwhile, the writing power consumption is greatly reduced.
The driving circuit may be configured to:
when a voltage V1 is applied between the electrode one 105-1 and the pinned layer 101-1 of any one memory device, the device operates in VCMA mode by controlling the duration of the voltage V1 through the word line and the amplitude of the voltage V1 through the bit line, i.e., the vertical anisotropy energy of CoFeB in the MTJ free layer 101-3 is voltage controlled, regulating the critical switching current of the MTJ free layer 101-3. When a high bias voltage is applied, the magnetization switching current of the free layer is increased, and when a low bias voltage is applied, the magnetization switching current of the free layer is reduced, namely the effect of a gating switch is realized.
When a voltage V2 is applied between the electrode two 105-2 and the pinned layer 101-1 of any memory device, the device operates in STT mode by controlling the duration of the voltage V2 through the word line and the amplitude of the voltage V2 pulse through the bit line, and when a current flows through the pinned layer 101-1, the current will be polarized to form a spin-polarized current, which flows through the very thin isolation layer 101-2 to ensure a high degree of polarization, the spin-polarized electrons can transfer their spin angular momentum to the free layer 101-3, changing the magnetization equilibrium state of the free layer. Spin electrons transfer spin momentum to the magnetic moment of the free layer, causing the magnetic moment of the spin magnetic layer to change direction after gaining spin momentum, a process known as spin transfer torque. The magnetic moment of the free layer is inverted by inputting current into the free layer, so that the resistance state of the magnetic tunnel junction is changed, and data writing is realized.
The resistance value of the magnetic tunnel junction depends on the magnetization directions of the free layer 101-3 and the pinned layer 101-1, and if the magnetization directions of the free layer 101-3 and the pinned layer 101-1 are identical, the resistance value of the magnetic tunnel junction is small and the magnetic tunnel junction is in a low resistance state. Conversely, if the magnetization directions of the free layer 101-3 and the pinned layer 101-1 are opposite, the resistance value of the magnetic tunnel junction is large, and the magnetic tunnel junction is in a high resistance state. Wherein the magnetization direction of the pinned layer 101-1 is preset to a fixed magnetization direction, for example, the magnetization direction of the pinned layer may be fixed by using a synthetic antiferromagnetic layer, and the magnetization direction of the free layer 101-3 may be changed by writing. In the later data reading, the data stored in the memory can be determined by determining the resistance state of the magnetic tunnel junction through the reading circuit.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present invention are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims (6)

1. A memory cell of a VCMA-STT MTJ, characterized by: it comprises the following steps:
a plurality of VCMA-STT MTJ memory devices;
a drive circuit configured to apply a voltage to the memory device, including applying a first voltage to regulate a critical switching current of a free layer of the MTJ; and applying a second voltage to regulate and control the magnetic moment direction of the MTJ free layer.
2. The memory cell of claim 1, wherein:
the VCMA-STT MTJ storage device comprises, in order from bottom to top: the magnetic tunnel junction comprises a magnetic tunnel junction, a dielectric layer and a magnetic tunnel junction pinned layer/isolation layer/free layer, wherein the magnetic tunnel junction pinned layer/isolation layer/free layer is specifically CoFeB/MgO/CoFeB, the dielectric layer is MgO, and the dielectric layer is in contact with the free layer.
3. The memory cell of claim 1, wherein: the magnetic tunnel junction is formed by the thickness of MgO in CoFeB/MgO/CoFeB of 0.8-1nm, and the dielectric layer is formed by the thickness of MgO of 2-5nm.
4. The memory cell of claim 1, wherein: a first voltage of the driving circuit is applied between the dielectric layer and the pinned layer, and a second voltage is applied between the free layer and the pinned layer.
5. The memory cell of claim 2, wherein: the driving circuit includes: each VCMA-STT MTJ device is connected with two bit lines and one word line, wherein the two bit lines are respectively connected with a dielectric layer and a free layer of the VCMA-STT MTJ device, and the one word line is connected with a pinned layer of the VCMA-STT MTJ device.
6. A storage method of a storage unit according to claim 5, characterized in that:
a. memory device switch gating
Through voltage regulation and control of one bit line, by applying different bias voltages, when a high bias voltage is applied, the magnetization flip current of the free layer is increased, and when a low bias voltage is applied, the magnetization flip current of the free layer is reduced, namely the memory device is in a VCMA mode, so that the gating switching function of the magnetic memory device is realized;
b. storage information writing
Through voltage regulation of another bit line, the magnetic moment direction of the free layer is regulated to regulate the resistance value of the magnetic tunnel junction, namely the storage device is in STT mode, so that writing of storage information is realized.
CN202211656274.7A 2022-12-22 2022-12-22 VCMA-STT MTJ memory cell and memory method Pending CN116072174A (en)

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CN202211656274.7A CN116072174A (en) 2022-12-22 2022-12-22 VCMA-STT MTJ memory cell and memory method

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