CN116056558B - Manufacturing method of semiconductor structure and structure thereof - Google Patents
Manufacturing method of semiconductor structure and structure thereof Download PDFInfo
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- CN116056558B CN116056558B CN202310311824.XA CN202310311824A CN116056558B CN 116056558 B CN116056558 B CN 116056558B CN 202310311824 A CN202310311824 A CN 202310311824A CN 116056558 B CN116056558 B CN 116056558B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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Abstract
The embodiment of the disclosure relates to the field of semiconductors, and provides a manufacturing method of a semiconductor structure and the structure thereof, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming a plurality of lower electrode layers which are arranged at intervals, wherein each lower electrode layer is positioned on the surface of the substrate; forming a capacitance dielectric layer, wherein the capacitance dielectric layer covers the surface of each lower electrode layer; forming an upper electrode layer, wherein the upper electrode layer covers the surface of the capacitor dielectric layer, and the upper electrode layer between the adjacent lower electrode layers surrounds a groove; forming a seed crystal layer, wherein the seed crystal layer covers the surface of the upper electrode layer, the seed crystal layer is not filled with the groove, and the seed crystal layer contains a fourth main group element; and growing a semiconductor conductive layer along the surface of the seed crystal layer, wherein the semiconductor conductive layer covers the surface of the seed crystal layer and fills the groove. The performance of the formed semiconductor structure may be improved.
Description
Technical Field
The embodiment of the disclosure relates to the field of semiconductors, in particular to a manufacturing method of a semiconductor structure and the structure thereof.
Background
The memory is a memory means for storing programs and various data information. Random Access Memory (Random Access Memory, RAM) used in a typical computer system can be divided into dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) and Static Random Access Memory (SRAM), which are semiconductor Memory devices commonly used in computers and are composed of a plurality of repeated Memory cells.
The memory cell typically includes a capacitor having a drain connected to a bit line and a source connected to the capacitor, the capacitor including a capacitive contact structure and a capacitance, and a transistor having a word line capable of controlling the switching on or off of a channel region of the transistor, thereby reading data information stored in the capacitor through the bit line or writing data information into the capacitor through the bit line for storage.
However, there is a need to improve the performance of the fabricated capacitor structure.
Disclosure of Invention
The embodiment of the disclosure provides a manufacturing method of a semiconductor structure and the structure thereof, which can at least improve the performance of a formed capacitor structure.
According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming a plurality of lower electrode layers arranged at intervals, wherein each of the plurality of lower electrode layers is positioned on the surface of the substrate; forming a capacitance dielectric layer, wherein the capacitance dielectric layer covers the surface of each lower electrode layer; forming an upper electrode layer, wherein the upper electrode layer covers the surface of the capacitance medium layer, and grooves are formed by surrounding the upper electrode layers between the adjacent lower electrode layers; forming a seed layer covering the surface of the upper electrode layer, the seed layer not filling the trench and containing a fourth main group element within the seed layer; and growing a semiconductor conductive layer along the surface of the seed crystal layer, wherein the semiconductor conductive layer covers the surface of the seed crystal layer and fills the groove.
In some embodiments, the seed layer is formed using a pressure vapor deposition process at a pressure of 1-0.01 torr, and the process temperature for forming the seed layer is less than or equal to 400 ℃.
In some embodiments, the fourth main group element is germanium, and the method of forming the seed layer includes: a germanium source gas is provided as a reactive gas to form the seed layer.
In some embodiments, the gas flow of the germanium source gas is gradually reduced during the process step of forming the seed layer.
In some embodiments, the semiconductor conductive layer is a layer of polycrystalline material doped with the fourth main group element, and a concentration of the fourth main group element within the semiconductor conductive layer is less than a concentration of the fourth main group element within the seed layer.
In some embodiments, the semiconductor conductive layer is formed using a pressure vapor deposition process at 1-0.01 torr, and the process temperature for forming the semiconductor conductive layer is less than or equal to 420 ℃.
In some embodiments, the semiconductor conductive layer is a germanium-doped polysilicon layer, and the method of forming the semiconductor conductive layer includes: providing a silicon source gas and a germanium source gas to grow a polysilicon layer doped with germanium along the surface of the seed crystal layer, wherein the ratio of the gas flow rate of the silicon source gas to the gas flow rate of the germanium source gas is in the range of 0.5-5.
In some embodiments, a method of forming the upper electrode layer includes: forming a sacrificial layer and a supporting layer which are alternately stacked on the substrate, wherein the top layer is formed by the supporting layer; etching the sacrificial layer and the supporting layer to form a plurality of capacitor holes penetrating through the sacrificial layer and the supporting layer; forming a lower electrode layer within each of the plurality of capacitor holes; forming a capacitor opening on the top layer, removing the sacrificial layer along the capacitor opening, and supporting the lower electrode layer by the rest supporting layer; performing first wet cleaning on the lower electrode layer; forming a capacitance medium layer on the surface of the cleaned lower electrode layer; forming an initial upper electrode layer on the surface of the capacitance dielectric layer; and performing second wet cleaning on the initial upper electrode layer to form the upper electrode layer, and then forming the seed crystal layer on the surface of the upper electrode layer, wherein the solutions of the first wet cleaning and the second wet cleaning are different.
In some embodiments, the aspect ratio of the capacitor hole is greater than or equal to 20:1.
in some embodiments, the electrode material of the lower electrode layer and/or the upper electrode layer is titanium nitride and/or titanium silicide nitride.
In some embodiments, the first wet cleaning uses a hydrofluoric acid solution with an amount concentration of 0.1% -1%, and the second wet cleaning uses a hydrofluoric acid solution with an amount concentration of 1% -5%.
According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a semiconductor structure, including: a substrate; a plurality of lower electrode layers arranged at intervals, each of the plurality of lower electrode layers being located on the surface of the substrate; the capacitor dielectric layer covers the surface of each lower electrode layer; the upper electrode layer covers the surface of the capacitance medium layer, and grooves are formed by surrounding the upper electrode layers between the adjacent lower electrode layers; a seed layer covering a surface of the upper electrode layer, the seed layer not filling the trench, and the seed layer containing a fourth main group element; and the semiconductor conductive layer covers the surface of the seed crystal layer and fills the groove.
In some embodiments, the fourth main group element is germanium and the seed layer is a germanium seed layer.
In some embodiments, the seed layer has a thickness of 0.1-3 nm in a direction perpendicular to the substrate surface.
In some embodiments, the semiconductor conductive layer is a layer of polycrystalline material doped with the fourth main group element, and a concentration of the fourth main group element within the semiconductor conductive layer is less than a concentration of the fourth main group element within the seed layer.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages: the capacitor structure is formed by forming the lower electrode layer to define a capacitor structure which is arranged at intervals, forming the capacitor dielectric layer and the upper electrode layer, then forming the seed crystal layer and forming the semiconductor conducting layer on the surface of the seed crystal layer, wherein the seed crystal layer contains fourth main group elements, on one hand, the fourth main group elements have small resistance and small atomic radius, and further the crystal grain size of the seed crystal layer is small, so that the seed crystal layer can be diffused into the capacitor structure with very small holes and very high depth, the concentration of the fourth main group elements of the whole body of the seed crystal layer and the semiconductor conducting layer is improved, the resistance of the whole capacitor structure is further reduced, on the other hand, the seed crystal layer and the semiconductor conducting layer formed subsequently can be filled into the capacitor structure more uniformly and compactly, the purpose of improving gap filling is achieved, the effect of supporting the lower electrode layer, the capacitor dielectric layer and the upper electrode layer can be achieved through the formed semiconductor conducting layer filled into grooves, and the performance of the formed capacitor structure can be improved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a schematic diagram of a step of providing a substrate and forming an initial bottom electrode layer according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a step of forming a bottom electrode layer according to an embodiment of the disclosure;
FIG. 3 is a top view of a step of forming a bottom electrode layer according to one embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a step of forming a capacitor dielectric layer and an initial upper electrode layer according to an embodiment of the present disclosure;
FIG. 5 is a top view of a step of forming a capacitor dielectric layer and an initial upper electrode layer according to one embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a step of forming an upper electrode layer according to an embodiment of the disclosure;
FIG. 7 is a top view of a step of forming an upper electrode layer according to one embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a step of forming a seed layer and a semiconductor conductive layer according to an embodiment of the present disclosure;
fig. 9 is a top view of a step of forming a seed layer and a semiconductor conductive layer according to an embodiment of the present disclosure;
FIG. 10 is a schematic diagram of a structure corresponding to a step of providing a substrate and forming a sacrificial layer according to an embodiment of the disclosure;
FIG. 11 is a schematic diagram of a structure corresponding to a step of etching a sacrificial layer according to an embodiment of the disclosure;
FIG. 12 is a schematic diagram of a second step of forming a bottom electrode layer according to an embodiment of the present disclosure;
FIG. 13 is a schematic diagram of a structure corresponding to a step of providing a substrate with alternately arranged sacrificial layers and supporting layers according to an embodiment of the present disclosure;
FIG. 14 is a schematic diagram of a structure corresponding to the steps of etching a sacrificial layer and a supporting layer according to an embodiment of the disclosure;
fig. 15 is a schematic structural diagram corresponding to a third step of forming a bottom electrode layer according to an embodiment of the disclosure;
fig. 16 is a schematic structural diagram corresponding to a second step of forming a capacitor dielectric layer and an initial upper electrode layer according to an embodiment of the present disclosure;
Fig. 17 is a schematic diagram of a second step of forming an upper electrode layer, a seed layer and a semiconductor conductive layer according to an embodiment of the present disclosure.
Detailed Description
As known from the background art, in the process of forming the capacitor structure, the aspect ratio of the capacitor structure is increased, the space between adjacent capacitor structures is reduced, the morphology of the formed seed layer is poor, and the capability of covering the whole surface of the upper electrode layer is poor.
The implementation of the present disclosure provides a method for manufacturing a semiconductor structure, which forms a capacitor structure by forming a lower electrode layer to define capacitor structures arranged at intervals, and forms a capacitor dielectric layer and an upper electrode layer to form the capacitor structure, then forms a seed crystal layer and forms a semiconductor conductive layer on the surface of the seed crystal layer, and by arranging a fourth main group element in the seed crystal layer, on the one hand, the fourth main group element has small resistance and small atomic radius, and further, the seed crystal layer has smaller grain size, so that the seed crystal layer can diffuse into a capacitor structure with very small holes and very high depth, the concentration of the fourth main group element of the whole seed crystal layer and the semiconductor conductive layer is improved, and further, the resistance of the whole capacitor structure is reduced, on the other hand, the seed crystal layer and the semiconductor conductive layer formed subsequently can fill the capacitor structure more uniformly and compactly, so that the purpose of improving the filling of gaps is achieved.
Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Referring to fig. 1 to 12, fig. 1 to 12 are schematic structural views corresponding to each step of forming a columnar capacitor structure according to an embodiment of the disclosure; fig. 13 to 17 are schematic structural views corresponding to each step of forming a cylindrical capacitor structure according to an embodiment of the disclosure.
The manufacturing method of the semiconductor structure provided by the embodiment of the disclosure comprises the following steps: providing a substrate 100; forming a plurality of lower electrode layers 110 arranged at intervals, each of the plurality of lower electrode layers 110 being located on the surface of the substrate 100; forming a capacitance dielectric layer 120, wherein the capacitance dielectric layer 120 covers the surface of each lower electrode layer 110; forming an upper electrode layer 140, wherein the upper electrode layer 140 covers the surface of the capacitor dielectric layer 120, and the upper electrode layer 140 between adjacent lower electrode layers 110 encloses a trench 150; forming a seed layer 160, wherein the seed layer 160 covers the surface of the upper electrode layer 140, the seed layer 160 is not filled with the trench 150, and the seed layer 160 contains a fourth main group element; a semiconductor conductive layer 170 is formed, the semiconductor conductive layer 170 covering the surface of the seed layer 160 and filling the trench 150.
The lower electrode layer 110 is formed to define capacitor structures which are arranged at intervals, the capacitor dielectric layer 120 and the upper electrode layer 140 are formed as capacitor structures, then the seed layer 160 is formed, the semiconductor conductive layer 170 is formed on the surface of the seed layer to fill the capacitor structures, the seed layer 160 is provided with a fourth main group element, the resistance of the fourth main group element is small, the atomic radius is small, and further the crystal grain size of the seed layer 160 is small, so that the seed layer 160 can be diffused into the capacitor structures with extremely small holes and extremely high depth (for example, the depth-to-width ratio of the capacitor structures is larger than or equal to 20:1), the concentration of the fourth main group element is improved, the resistance of the semiconductor conductive layer is effectively reduced, the resistance of the whole capacitor structures is further reduced, and in addition, the formed semiconductor conductive layer 170 is filled with the grooves 150 to support the lower electrode layer 110, the capacitor dielectric layer 120 and the upper electrode layer 140, and the performance of the formed capacitor structures can be improved.
Referring to fig. 1 and 10, fig. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the disclosure, and fig. 10 is a cross-sectional view of another semiconductor structure according to an embodiment of the disclosure. A substrate 100 is provided.
In some embodiments, the material of the substrate 100 may be a semiconductor material such as silicon.
Referring to fig. 2 and 3, fig. 11 and 12, or fig. 13 to 15, fig. 2 and 3 or fig. 11 and 12 are schematic structural views corresponding to the process steps of forming a columnar capacitor according to an embodiment of the present disclosure, fig. 13 and 14 are schematic structural views corresponding to the process steps of forming a columnar capacitor according to an embodiment of the present disclosure, fig. 2 is a schematic structural view of forming a bottom electrode layer 110 according to an embodiment of the present disclosure, fig. 3 is a top view of fig. 2, fig. 2 is a cross-sectional view along a dotted line direction of fig. 3, fig. 12 is a schematic structural view of forming a bottom electrode layer 110 according to a second embodiment of the present disclosure, fig. 12 is a top view of fig. 11, fig. 11 is a cross-sectional view along a dotted line direction of fig. 12, fig. 13 is a schematic structural view of providing a substrate, fig. 14 is a schematic structural view of etching a support layer and a sacrificial layer on the basis of fig. 13, and fig. 15 is a schematic structural view of forming a bottom electrode layer.
A plurality of lower electrode layers 110 are formed.
In some embodiments, before forming the lower electrode layer 110, a word line structure, a bit line structure, and/or a gate structure may be formed on the substrate 100, and in some embodiments, a word line structure, a bit line structure, and/or a gate structure may be formed after forming a capacitor structure on the substrate 100, that is, after forming a semiconductor conductive layer, a word line structure, a bit line structure, and/or a gate structure may be formed.
Referring to fig. 1 to 3, in some embodiments, the lower electrode layer 110 may be formed by depositing a material of the lower electrode layer 110 on the entire surface of the substrate 100 to form an initial lower electrode layer 111, and then patterning the lower electrode layer 110 to be spaced apart from each other.
Referring to fig. 1, a substrate 100 is provided, and an initial lower electrode layer 111 is formed on a surface of the substrate 100.
Referring to fig. 2 and 3, the initial lower electrode layer 111 is etched to form lower electrode layers 110 arranged at intervals.
Referring to fig. 10 to 12, in some embodiments, the method of forming the lower electrode layer 110 may further include forming a sacrificial layer 180 on the surface of the substrate 100, and patterning the sacrificial layer 180 to form grooves for subsequent material filling the lower electrode layer 110 to form the lower electrode layer 110 arranged at intervals.
Referring to fig. 10, a substrate 100 is provided, and a sacrificial layer 180 is formed on a surface of the substrate 100.
Referring to fig. 11, the sacrificial layer 180 is etched to form grooves arranged at intervals, which expose the top surface of the substrate 100.
Referring to fig. 12, a lower electrode layer 110 is formed, the lower electrode layer 110 is filled with grooves, and the sacrificial layer 180 (refer to fig. 11) is removed after the lower electrode layer 110 is formed.
Referring to fig. 13 to 15, in some embodiments, referring to fig. 13, sacrificial layers 180 and support layers 190 are formed alternately stacked on a substrate 100, with a top layer being composed of the support layers 190; referring to fig. 14, the sacrificial layer 180 and the support layer 190 are etched to form a plurality of capacitor holes 200 penetrating the sacrificial layer 180 and the support layer 190; referring to fig. 15, a lower electrode layer 110 is formed in each of the plurality of capacitor holes 200.
Referring to fig. 13, taking the support layer 190 as 3 layers and the sacrificial layer 180 as two layers as an example, the support layer 190 is defined as a first support layer 191, a second support layer 192, and a third support layer 193 from the direction close to the substrate 100 toward the direction far from the substrate 100, and the sacrificial layer 180 is defined as a first sacrificial layer 181 and a second sacrificial layer 182.
In some embodiments, the materials of the first support layer 191, the second support layer 192, and the third support layer 193 may be the same, and may be titanium nitride, and the materials of the first sacrificial layer 181 and the second sacrificial layer 182 may be the same, and may be silicon oxide, or the like.
It is appreciated that the aspect ratio of the subsequently formed capacitor holes and capacitor structures may be controlled by controlling the number of layers and/or thicknesses of the support layer 190 and the sacrificial layer 180.
Referring to fig. 14, the support layer 190 and the sacrificial layer 180 are etched to form a capacitor hole 200.
In some embodiments, the aspect ratio of the capacitor hole 200 is greater than or equal to 20:1, for example, the opening size is 50nm or less, the depth is 1000nm or greater, and further, may be less than or equal to 50:1, for example, the opening size is 20nm or more and the depth is 1000nm or more, it is understood that the larger the aspect ratio of the capacitor hole 200, the higher the requirements on the morphology and performance control capability of the formed seed layer 160, so that the grain size of the seed layer 160 can be reduced by using the material of the fourth main group element when the seed layer 160 is formed later, so that the formed seed layer 160 covers the bottom wall of the trench 150, and the morphology and performance of the seed layer 160 are improved.
Referring to fig. 15, a lower electrode layer 110 is formed.
In some embodiments, an impurity layer is further formed on the surface of the lower electrode layer 110 in the process of forming the lower electrode layer 110, where the impurity layer is used as a byproduct of forming the lower electrode layer 110, impurities, bubbles and the like exist in the impurity layer, so that the compactness is poor, and therefore, the surface of the lower electrode layer 110 may be subjected to a first wet cleaning after the formation of the lower electrode layer 110, so as to remove the impurity layer on the surface of the lower electrode layer 110, thereby exposing the surface of the lower electrode layer 110, and then, the capacitance medium layer 120 is reformed in a subsequent process, so that the reliability of the semiconductor structure may be improved. It will be appreciated that the material of the lower electrode layer 110 is titanium nitride (TIN) or Titanium Silicide Nitride (TSN), however, in forming the lower electrode layer 110, a reactant having a halogen element is generally used, and the problem caused by using the reactant having a halogen element is: an impurity layer may be formed on the surface of the lower electrode layer 110 after the lower electrode layer 110 is formed. The impurity layer may cause poor performance of the lower electrode layer 110 and may affect the reliability of the semiconductor structure, and thus, the lower electrode layer may be subjected to a first wet cleaning after the lower electrode layer 110 is formed, and the impurity layer on the surface of the lower electrode layer 110 may be removed by the first wet cleaning, thereby improving the reliability of the semiconductor structure.
In some embodiments, the first wet cleaning may use a hydrofluoric acid solution with a mass concentration of 0.1% -1%, for example, a hydrofluoric acid solution with a mass concentration of 0.2% or a hydrofluoric acid solution with a mass concentration of 0.5%. The use of the hydrofluoric acid solution with the mass concentration of 0.1% -1% to clean the lower electrode layer 110 can well clean the surface of the lower electrode layer 110 and avoid damaging the lower electrode layer 110, thereby further improving the reliability of the formed semiconductor structure. In some embodiments, the shape of the lower electrode layer 110 may be a columnar structure as shown in fig. 1, in some embodiments, the shape of the lower electrode layer 110 may also be a U-shaped structure as shown in fig. 15, that is, a generally cylindrical structure, and by providing the shape of the lower electrode layer 110 to be U-shaped, the facing area between the lower electrode layer 110 and the subsequently formed upper electrode layer 140 may be increased, so that the performance of the formed capacitor structure may be improved.
Referring to fig. 4, fig. 5 and fig. 16, fig. 4 is a schematic structural view illustrating a step of forming the capacitor dielectric layer 120 and the initial upper electrode layer 130, fig. 4 is a cross-sectional view along a dotted line direction of fig. 5, fig. 5 is a top view of fig. 4, and fig. 16 is a schematic structural view formed on the basis of fig. 15.
Referring to fig. 4, a capacitance dielectric layer 120 and an initial upper electrode layer 130 are directly formed on the surface of the lower electrode layer 110.
Referring to fig. 16, a capacitor opening is formed in the top layer, and the sacrificial layer 180 (refer to fig. 15) is removed along the capacitor opening, and the remaining support layer 190 supports the lower electrode layer 110; performing a first wet cleaning on the lower electrode layer 110; forming a capacitance medium layer 120 on the surface of the cleaned lower electrode layer 110; an initial upper electrode layer 130 is formed on the surface of the capacitive dielectric layer 120.
In some embodiments, a method of forming the capacitive dielectric layer 120 may include: the capacitive dielectric layer 120 is formed on the exposed surface of the substrate 100 and the surface of the lower electrode layer 110 by directly depositing the material of the capacitive dielectric layer 120.
In some embodiments, the method of depositing the capacitance medium layer 120 may be to deposit the capacitance medium layer material on the surface of the lower electrode layer 110 and the surface of the substrate 100 through an atomic layer deposition process or a plasma chemical vapor deposition process.
In some embodiments, the material of the capacitive dielectric layer 120 may be a material having a relative dielectric constant greater than 7. It can be understood that the higher the relative dielectric constant, the better the insulation property of the material of the capacitance dielectric layer 120, and the better the insulation property between the lower electrode layer 110 and the subsequently formed upper electrode layer 140, and the less likely the leakage between the upper electrode layer and the lower electrode layer 110 occurs, the reliability of the formed capacitance structure can be improved by providing the material of the capacitance dielectric layer 120 with a relative dielectric constant greater than 7.
The relative dielectric constant here means: the absolute dielectric constant of free space or vacuum is considered a standard, and relative dielectric constant refers to the ratio of the absolute dielectric constant of any material to the absolute dielectric constant of free space or vacuum.
In some embodiments, the melting point of the material of the capacitance medium layer 120 may be higher than the subsequent seed growth temperature, and when the withstand temperature of the material of the capacitance medium layer 120 is lower than the seed growth temperature, then the capacitance medium layer 120 may not exist stably when the seed is formed, and a capacitor with reliable performance may not be obtained, and in some specific embodiments, the melting point of the capacitance medium layer 120 may be higher than 400 degrees.
In some embodiments, the material of the capacitive dielectric layer 120 may be any one of ZrO, alO, zrNbO, zrHfO, zrAlO or any combination thereof.
In some embodiments, the capacitor dielectric layer 120 may also be a stacked structure, for example, the capacitor dielectric layer 120 is two layers, and may be a stack of aluminum oxide and zirconium oxide, for example.
In some embodiments, the method of forming the initial upper electrode layer 130 may include: titanium tetrachloride is introduced and heated in a nitrogen gas stream to form titanium nitride and form the initial upper electrode layer 130 by vapor deposition, however, the surface of the initial upper electrode layer 130 formed by this method is easily oxidized, and during vapor deposition, there may be a part of unreacted titanium tetrachloride gas and chlorine generated by reaction, which may affect the quality of the initial upper electrode layer 130 formed, that is, may oxidize a part of the initial upper electrode layer to form the oxide layer 131, and/or there may be bubbles on the surface of the oxide layer 131, in which there may exist chlorine gas or chloride ions which corrode the conductive film layer in the initial upper electrode layer 130, may reduce the performance of the subsequently formed upper electrode layer 140, and thus the formed oxide layer 131, chlorine gas and chloride ions in the bubbles on the surface of the oxide layer 131 may be removed by a cleaning process.
It will be appreciated that, after the initial upper electrode layer 130 is formed, as the process proceeds, the initial upper electrode layer 130 exposed to air contacts oxygen, so that the initial upper electrode layer 130 is oxidized, and as an example of the material of the initial upper electrode layer 130 formed is titanium nitride, the titanium nitride contacts the oxygen in the air to be oxidized, and titanium oxide is formed on the surface of the initial upper electrode layer 130, at this time, the titanium oxide is removed by the second wet cleaning process, and as the second wet cleaning process proceeds and the titanium oxide is cleaned, chlorine gas and chloride ions in bubbles are dispersed into the air, and the chloride ions flow out along with the cleaning agent.
Specifically, the initial upper electrode layer 130 may be regarded as a two-layer structure, a main body layer 132, an oxidized oxide layer 131, and the oxide layer 131 covers the surface of the main body layer 132.
Referring to fig. 6 and 7 and 17, wherein fig. 6 is a schematic structural view of forming the upper electrode layer 140, fig. 6 is a schematic structural view formed on the basis of fig. 4, fig. 6 is a sectional view of fig. 7 in a dotted line direction, fig. 7 is a plan view of fig. 6, and fig. 17 is a schematic structural view formed on the basis of fig. 16. The initial upper electrode layer 130 is subjected to a second wet cleaning to form an upper electrode layer 140, wherein a solution used for the first wet cleaning is different from a solution used for the second wet cleaning.
In some embodiments, the electrode material of the initial upper electrode layer 130 and the upper electrode layer 140 may be titanium nitride and/or titanium silicide nitride, however, in forming the initial upper electrode layer 130 and the upper electrode layer 140, a reactant having a halogen element is generally used, however, the use of the reactant having a halogen element causes problems: an oxide layer 131 is formed on the surface of the preliminary upper electrode layer 130 after the preliminary upper electrode layer 130 is formed. The oxide layer 131 may cause poor performance of the subsequently formed upper electrode layer 140, which may affect the reliability of the semiconductor structure, and thus, the initial upper electrode layer 130 may be subjected to a second wet cleaning after the initial upper electrode layer 130 is formed, and the oxide layer 131 on the surface of the initial upper electrode layer 130 may be removed through the second wet cleaning, thereby improving the reliability of the semiconductor structure.
It can be appreciated that, due to the different thicknesses of the upper electrode layer 140 and the lower electrode layer 110, and the different structures of the surfaces of the upper electrode layer 140 and the lower electrode layer that are subsequently formed, the reliability of the semiconductor structure can be further improved by cleaning their surfaces with different cleaning solutions, for example, different concentrations of the cleaning solutions, and different cleaning durations.
When the initial upper electrode layer 130 and the lower electrode layer 110 are cleaned by using the acidic solution, the types of the acidic solutions are the same, but the concentrations and the time are different, so that the performance of the capacitor structure is ensured, when the lower electrode layer 110 is cleaned, the lower concentration (for example, the hydrofluoric acid solution with the mass concentration of 0.1% -1%) and the longer time (for example, 60 s-180 s) can be used, when the initial upper electrode layer 130 is cleaned, the higher concentration (for example, the hydrofluoric acid solution with the mass concentration of 1% -5%) and the shorter time (for example, 10 s-60 s) can be used, the purpose of cleaning the initial upper electrode layer 130 is realized, the performance of the capacitor structure is ensured, when the lower electrode layer 110 is cleaned, the impurity layer can be cleaned more fully by using the lower concentration and the longer time, when the initial upper electrode layer 130 is cleaned by using the higher concentration and the shorter time, the higher concentration and the higher concentration is more corrosive, the better initial upper electrode layer 131 is beneficial to the whole semiconductor structure is formed, and the whole surface of the semiconductor structure is beneficial to be cleaned. Further, during the second wet cleaning, the cleaning solution may be heated to form hydrofluoric acid gas, and the surface of the initial upper electrode layer 130 may be cleaned by the acid gas, and the oxidized impurities may be carried away along with volatilization of the hydrofluoric acid gas, and the halogen gas in the process of forming the initial upper electrode layer 130 may be carried away, so that synchronous removal may be achieved.
In some embodiments, the second wet clean may include: the surface of the initial upper electrode layer 130 is cleaned using an acidic solution, such as a diluted hydrofluoric acid solution, a diluted sulfuric acid solution. The oxide layer 131 on the surface of the initial upper electrode layer 130 can be cleaned by cleaning the surface of the initial upper electrode layer 130 with an acidic solution, and bubbles on the surface of the oxide layer 131 can be removed at the same time, the reliability of the formed upper electrode layer 140 can be improved by cleaning the surface of the initial upper electrode layer 130 with an acidic solution, the main body layer 132 can be directly contacted with a subsequently formed semiconductor conductive layer by removing the oxide layer 131 with an acidic solution, the connection tightness of the upper electrode layer 140 and the semiconductor conductive layer can be improved, the contact resistance between the upper electrode layer 140 and the semiconductor conductive layer 170 can be reduced, and the leakage current of the capacitor structure can be reduced.
In some embodiments, the acidic solution used in the second wet clean may include: the hydrofluoric acid solution with the mass concentration of 1% -5% is, for example, a hydrofluoric acid solution with the mass concentration of 1% or a hydrofluoric acid solution with the mass concentration of 2%, etc., and it is understood that the reason for using the hydrofluoric acid solution is as follows: the combination capability of the hydrogen atoms and the fluorine atoms is relatively strong, and hydrogen bonds exist among hydrogen fluoride molecules in the aqueous solution, so that hydrofluoric acid cannot be completely ionized in water, therefore, the corrosion effect of the acidic solution on the initial upper electrode layer 130 can be reduced by adopting the acidic solution as the hydrofluoric acid solution, and damage to the initial upper electrode layer 130 which is not oxidized is avoided.
It can be understood that the hydrofluoric acid solution has weak acidity due to hydrogen bonds when the solute mass percentage is low, but when the solute mass percentage of the hydrofluoric acid solution is high, self-coupling ionization occurs in the hydrofluoric acid solution, the acidity of the hydrofluoric acid with the self-coupling ionization is strong, and the corrosiveness of the hydrofluoric acid solution can be greatly improved, so that the solution with the solute mass percentage of 1% -5% can have a certain acidity to realize cleaning of the surface of the initial upper electrode layer 130, and meanwhile, the excessive corrosion of the initial upper electrode layer 130 due to the too strong acidity of the hydrofluoric acid solution is avoided.
It can be understood that when the mass percentage of the solute of the hydrofluoric acid solution is less than 1%, the effect of the hydrofluoric acid solution to clean the initial upper electrode layer 130 is poor and it is difficult to completely remove the oxide layer 131 under a predetermined cleaning period; when the mass percentage of the solute of the hydrofluoric acid solution exceeds 5%, the acidity of the hydrofluoric acid solution is too strong, which may cause corrosion of the portion of the initial upper electrode layer 130 that needs to be preserved after the oxide layer 131 is removed for a predetermined cleaning period.
In some embodiments, the purpose of synchronous removal can be achieved by using the acid solution as hydrofluoric acid, evaporating the hydrofluoric acid by heating, and taking away oxidized impurities along with volatilization of the acid gas of the hydrofluoric acid, and taking away halogen gas in the process of forming the initial upper electrode layer 130.
In some embodiments, the environmental temperature of the acidic solution may be 15 ℃ to 100 ℃, for example, 20 ℃, 40 ℃ or 60 ℃, and further, the cleaning may be performed in a gradient temperature rising manner, taking the acidic solution as hydrofluoric acid as an example, at a lower temperature, for example, 15 ℃ to 20 ℃, the hydrofluoric acid solution is liquid, the acidic solution is improved to sufficiently clean the surface of the initial upper electrode layer 130, the cleaning effect is ensured, and then the cleaning temperature is increased, for example, at 60 ℃ to 100 ℃, the boiling point of the hydrofluoric acid solution is reached, so that acidic gas is formed, and oxidized impurities and halogen gas are taken away.
In other embodiments, in some embodiments, the cleaning process may include: and introducing inert gas or nitrogen gas into the surface of the initial upper electrode layer. It is understood that the inert gas or nitrogen may be introduced alone or after the second wet cleaning. The surface of the initial upper electrode layer 130 may form a plurality of bubbles due to the manufacturing process, and chlorine gas or chloride ions may remain in the bubbles, and may corrode the initial upper electrode layer 130, and may be removed by introducing inert gas into the surface of the initial upper electrode layer 130, thereby improving the reliability of the formed upper electrode layer 140.
In some embodiments, the upper electrode layer 140 may be shared by multiple capacitor structures, that is, the initial upper electrode layer 130 not only covers the surface of the capacitor dielectric layer 120 but also is located on the top surface of the substrate 100 during the formation of the upper electrode layer 140; in some embodiments, the plurality of capacitor structures may not share the upper electrode layer 140, that is, the upper electrode layers 140 may be formed to be spaced apart from each other.
It is understood that the relative area between the bottom electrode layer 110 and the top electrode layer 140, the distance between the bottom electrode layer 110 and the top electrode layer 140, and the material of the capacitor dielectric layer 120 may affect the capacity of the capacitor structure, so the relative area between the bottom electrode layer 110 and the top electrode layer 140, the distance between the bottom electrode layer 110 and the top electrode layer 140, and the material of the capacitor dielectric layer 120 may be set according to practical requirements.
Referring to fig. 8 and 9 and 17, fig. 8 is a schematic structural view formed on the basis of fig. 6, fig. 8 is a sectional view of fig. 9 in a direction of a broken line, fig. 9 is a top view of fig. 8, and fig. 17 is a schematic structural view formed on the basis of fig. 16. A seed layer 160 and a semiconductor conductive layer 170 are formed.
In some embodiments, the formation of the seed layer 160 provides a process basis for forming the semiconductor conductive layer 170, and the formation of the semiconductor conductive layer 170 connects the upper electrode layer 140 into a whole, and may fill the space between the lower electrode layers 110, thereby also avoiding deformation of the lower electrode layers 110 and the capacitor dielectric layer 120.
In some embodiments, the seed layer 160 is formed by using a pressure vapor deposition process at 1-0.01 torr, and the process temperature for forming the seed layer 160 is less than or equal to 400 ℃, such as 400 ℃, 390 ℃, 380 ℃, and 350 ℃, the method for forming the seed layer 160 is generally by performing diffusion growth through a furnace tube, so as to form the seed layer 160 on the surface of the capacitance medium layer 120, and by controlling the ambient temperature for forming the seed layer 160 to be less than 400 ℃, not only the withstand temperature of the upper electrode layer 140, the lower electrode layer 110, and particularly the capacitance medium layer 120 can be adapted, but also the size of the grains of the seed layer 160 can be further reduced, and at the same time, the gaps between the grains of the seed layer 160 can be reduced, so that the pores between the grains of the seed layer 160 are avoided to be too large, thereby facilitating that the formed seed layer 160 can cover the bottom of the trench 150 when the capacitance structure has a high aspect ratio, and the reliability of the formed seed layer 160 can be improved.
In some embodiments, the process temperature of forming the seed layer 160 may be other temperatures, the process temperature of forming the seed layer 160 may adapt to the temperature tolerance of the capacitor dielectric layer 120, for example, the material of the capacitor dielectric layer 120 is zirconia or alumina, the process temperature of forming the seed layer 160 may not exceed 500 ℃, and when the process temperature of forming the seed layer 160 exceeds 500 ℃, the material of the capacitor dielectric layer 120 may change, and even cause leakage between the lower electrode layer 110 and the upper electrode layer 140.
It should be understood that the above-mentioned withstand temperature refers to the maximum temperature that the capacitive dielectric layer 120 can withstand, that is, the maximum temperature that the external temperature is received without itself changing.
In some embodiments, the fourth main group element is germanium, and the method of forming the seed layer 160 includes: a germanium source gas is provided as a reactive gas to form seed layer 160. The material of the seed layer 160 formed by using the germanium source gas as the reaction gas is monocrystalline germanium, and the material of the seed layer 160 is monocrystalline germanium, so that the resistance value of the seed layer 160 can be reduced to the highest value, and the performance of the formed semiconductor structure can be further improved. In some embodiments, the gas flow rate of the germanium source gas may be 200cc/min to 1000cc/min, such as 300 cc/min, 400 cc/min, or 600 cc/min.
In some embodiments, the material of the seed layer 160 is single crystal germanium, and the gas flow rate of the germanium source gas is gradually reduced during the process step of forming the seed layer 160, so as to achieve an improved deposition effect of the seed layer 160 by controlling the gas flow rate of the germanium source gas, thereby enabling the seed layer 160 to be better adhered to the surface of the upper electrode layer 140.
In some embodiments, the resistance of the germanium material is small, the atomic radius of the germanium atom is small, the germanium atom is a fourth main group element, the outermost electron has 4 electrons, which is easy to conduct electricity, and the fourth main group element is more stable and less free than the sixth main group element and the seventh main group element, so that the performance of the seed layer 160 can be further improved by selecting the material of the seed layer 160 to be germanium.
In some embodiments, a germanium source gas may be provided and a silicon source gas may be introduced to form the germanium doped silicon seed layer 160, where the ratio of the gas flow rate of the germanium source gas to the gas flow rate of the silicon source gas is in the range of 0.4-5, such as 1, 2, or 3. The higher the gas flow of the germanium source gas, the higher the content of germanium atoms in the formed seed layer 160, and the higher the transmission rate of the seed layer 160, the higher the content of germanium atoms in the seed layer 160, compared to when the seed layer 160 is monocrystalline silicon, which may further enhance the performance of the semiconductor structure.
In some embodiments, the gas flow of the germanium source gas is gradually reduced during the process step of forming the seed layer 160. That is, the closer the formed seed layer 160 is to the substrate, the higher the doped germanium ion concentration is, the closer to the semiconductor conductive layer 170, and the lower the doped germanium concentration is, which is to be understood that the doped germanium concentration in the semiconductor conductive layer 170 should not be too high, otherwise, germanium overflow may be caused during the formation of the semiconductor conductive layer 170, which affects the reliability of the semiconductor structure, and by setting the doped germanium concentration close to the semiconductor conductive layer 170 to be low, the doped germanium concentration in the semiconductor conductive layer 170 is adapted, so that the difference of the germanium content at the interface between the seed layer 160 and the semiconductor conductive layer 170 can be reduced, the lattice difference between the seed layer 160 and the semiconductor conductive layer 170 can be reduced, the interface performance can be improved, and the resistance of the semiconductor structure can be further reduced.
In some embodiments, the gas flow rate of the germanium source gas may be 200cc/min to 1000cc/min, such as 300 cc/min, 400 cc/min, or 600 cc/min.
In some embodiments, the gas flow rate of the silicon source gas may be 150 cc/min to 1500cc/min, such as 300 cc/min, 400 cc/min, or 800 cc/min.
In some embodiments, the semiconductor conductive layer 170 is a polycrystalline material layer doped with a fourth main group element, and the concentration of the fourth main group element within the semiconductor conductive layer 170 is less than the concentration of the fourth main group element within the seed layer 160. By providing the semiconductor conductive layer 170 containing the fourth main group element, the resistance value of the formed capacitor structure can be reduced while preventing the deformation of the lower electrode layer 110, the capacitor dielectric layer 120 and the upper electrode layer 140, and the fourth main group element content of the semiconductor conductive layer 170 cannot be excessively high, otherwise, the overflow of the fourth main group element is caused when the semiconductor conductive layer 170 is formed, and the reliability of the semiconductor structure is affected, so that the contents of the fourth main group element in the seed layer 160 and the semiconductor conductive layer 170 are relatively high by increasing the ion concentration of the fourth main group element in the seed layer 160, and the capability of relatively reducing the resistance value of the semiconductor structure is provided.
In some embodiments, the content of the fourth main group element in the entire seed layer 160 and the semiconductor conductive layer 170 is not less than 60%, so that the seed layer 160 and the semiconductor conductive layer 170 have better capability of reducing the resistance of the semiconductor structure.
In some embodiments, the semiconductor conductive layer is formed using a pressure vapor deposition process at 1-0.01 torr and the process temperature for forming the semiconductor conductive layer 170 is less than or equal to 420 ℃, such as 390 ℃, 400 ℃, or 410 ℃, 420 ℃. By controlling the temperature of the semiconductor conductive layer 170 to be 420 ℃ or less, the temperature is slightly higher than the formation temperature of the seed crystal layer 160, and under the condition that the seed crystal with smaller size is formed, the growth temperature is increased, so that the growth of silicon can be suitable, the semiconductor conductive layer 170 can be formed more quickly, the capacitor structure can be filled more uniformly and compactly, the purpose of improving gap filling is achieved, the connection tightness among the semiconductor conductive layer 170, the seed crystal layer 160 and the upper electrode layer 140 is improved, and the leakage condition of the capacitor structure is reduced.
In some embodiments, the semiconductor conductive layer 170 is a germanium doped polysilicon layer, and the method of forming the semiconductor conductive layer 170 includes: a silicon source gas and a germanium source gas are provided to grow a polysilicon layer doped with germanium along the surface of the seed layer 160, wherein the ratio of the gas flow rate of the silicon source gas to the gas flow rate of the germanium source gas is in the range of 0.5-5, for example, the ratio of the gas flow rate of the silicon source gas to the gas flow rate of the germanium source gas is 2 or 3, etc. In some embodiments, the flow rate of the silicon source in the subsequent semiconductor conductive layer 170 is, for example, 400-1200 cc/min, and the flow rate of the germanium source is in the range of 200-2000cc/min, and by using the germanium source gas and the silicon source gas to form the polysilicon layer doped with germanium, the movement rate of carriers can be increased by germanium, so that the resistance value of the semiconductor conductive layer 170 can be reduced, and the conductivity of the semiconductor conductive layer 170 can be improved.
The semiconductor conductive layer 170 formed by introducing the silicon source gas and the germanium source gas has conductivity, namely can be used as a part of the upper electrode layer 140 of the capacitor structure, so that the resistance of the upper electrode layer 140 of the capacitor structure can be reduced, the performance of the formed capacitor structure is improved, the formed semiconductor conductive layer 170 can be controlled to form a film with smaller crystallization granularity by controlling the volume ratio of the doping gas to the semiconductor gas to be 0.5-5, and the compactness of the formed semiconductor conductive layer 170 can be improved.
Another embodiment of the present disclosure further provides a semiconductor structure, which may be formed by using the method for manufacturing a semiconductor structure as described above, and the semiconductor structure provided in another embodiment of the present disclosure will be described with reference to the accompanying drawings, where the same or corresponding parts of the foregoing embodiments are referred to for the corresponding description of the foregoing embodiments, and the description will not be repeated.
Referring to fig. 8 and 16, the semiconductor structure includes: a substrate 100; a plurality of lower electrode layers 110 arranged at intervals, each of the plurality of lower electrode layers 110 being located on the surface of the substrate 100; a capacitance dielectric layer 120, the capacitance dielectric layer 120 covering the surface of each lower electrode layer 110; the upper electrode layer 140 covers the surface of the capacitor dielectric layer 120, and the upper electrode layer 140 between adjacent lower electrode layers 110 encloses a trench 150; a seed layer 160, the seed layer 160 covering the surface of the upper electrode layer 140, the seed layer 160 not filling the trench 150, and the seed layer 160 containing a fourth main group element; the semiconductor conductive layer 170, the semiconductor conductive layer 170 covers the surface of the seed layer 160 and fills the trench 150.
In the embodiment of the disclosure, the lower electrode layer 110 is formed to define a capacitor structure arranged at intervals, the capacitor dielectric layer 120 and the upper electrode layer 140 are formed to form a capacitor structure, then the seed crystal layer 160 is formed and the semiconductor conductive layer 170 is formed on the surface of the seed crystal layer 160, and the seed crystal layer 160 contains a fourth main group element, so that the resistance of the fourth main group element is small, the atomic radius is small, the grain size of the seed crystal layer 160 is small, the seed crystal layer 160 can be diffused into a very small hole and very high depth capacitor structure, the concentration of the fourth main group element of the whole seed crystal layer 160 and the semiconductor conductive layer 170 is improved, and the resistance of the whole capacitor structure is further reduced.
In some embodiments, the fourth main group element is germanium, the seed layer 160 is a germanium seed layer, the resistance of the germanium material is small, the atomic radius of the germanium atom is small, the germanium atom is the fourth main group element, the outermost electron has 4 electrons, which is easy to conduct electricity, and the fourth main group element is more stable and less free than the sixth main group element and the seventh main group element, so the performance of the seed layer 160 can be further improved by selecting the material of the seed layer 160 to be germanium.
In some embodiments, seed layer 160 comprises a germanium layer and/or a germanium-doped silicon layer. Compared to the material of the seed layer 160 being silicon, the provision of the seed layer 160 being a silicon layer doped with germanium may reduce the resistance of the seed layer 160, and the higher the doping concentration of germanium in the seed layer 160, the higher the resistance of the seed layer 160 may be, and the lower the resistance of the capacitor structure may be, when the seed layer 160 is a germanium layer, the higher the performance of the formed semiconductor structure may be.
In some embodiments, seed layer 160 may be a single layer structure, such as a germanium layer or a germanium-doped silicon layer; in some embodiments, the seed layer may also be a stacked structure, for example, a stacked structure of a germanium layer and a silicon layer doped with germanium, where the germanium layer covers the surface of the upper electrode layer 140, and the silicon layer doped with germanium covers the surface of the germanium layer, so that by disposing the silicon layer doped with germanium in contact with the semiconductor conductive layer 170, the difference between the interfaces of the seed layer 160 and the semiconductor conductive layer 170 can be reduced, the interface state between the seed layer 160 and the semiconductor conductive layer 170 can be reduced, and the contact resistance between the seed layer 160 and the semiconductor conductive layer 170 can be reduced.
In some embodiments, seed layer 160 is a silicon layer doped with germanium, and the germanium content within seed layer 160 gradually decreases in the direction of substrate 100 toward upper electrode layer 140. It will be appreciated that the concentration of doped germanium in the semiconductor conductive layer 170 should not be too high, which would otherwise cause germanium overflow during formation of the semiconductor conductive layer 170, affect the reliability of the semiconductor structure, and reduce the difference in germanium content at the interface between the seed layer 160 and the semiconductor conductive layer 170, reduce the lattice difference between the seed layer 160 and the semiconductor conductive layer 170, improve the interface performance, and further reduce the resistance of the semiconductor structure by providing a low concentration of germanium near the semiconductor conductive layer 170 to adapt to the doping concentration of germanium in the semiconductor conductive layer 170.
In some embodiments, the thickness of the seed layer 160 is 0.1-3 nm, e.g., 1nm, 1.5nm, in a direction perpendicular to the surface of the substrate 100. It can be appreciated that as the aspect ratio of the capacitor structure increases and the spacing distance between the capacitor structures decreases, the thicker the seed layer 160 is, the more difficult it is to form the seed layer 160, and the worse the morphology of the seed layer 160 is, the thinner the seed layer 160 is, and the worse the performance of the seed layer 160 is, so that the process difficulty of forming the seed layer 160 is reduced while the seed layer 160 has better performance by setting the thickness of the seed layer 160 to 0.1-3 nm.
In some embodiments, the semiconductor conductive layer 170 is a polycrystalline material layer doped with a fourth main group element, and the concentration of the fourth main group element in the semiconductor conductive layer 170 is smaller than that in the seed layer 160, by setting the concentration of the fourth main group element in the semiconductor conductive layer 170, the resistance value of the formed semiconductor structure can be reduced while preventing the deformation of the lower electrode layer 110, the capacitance medium layer 120 and the upper electrode layer 140, and the content of the fourth main group element in the semiconductor conductive layer 170 cannot be too high, otherwise, the overflow of the fourth main group element is caused when the semiconductor conductive layer 170 is formed, which affects the reliability of the semiconductor structure, so that the content of the fourth main group element in the seed layer 160 and the semiconductor conductive layer 170 can be higher by increasing the concentration of the fourth main group element in the seed layer 160, thereby having a better capability of reducing the resistance value of the semiconductor structure.
In some embodiments, the material of the capacitive dielectric layer 120 is a material with a relative dielectric constant greater than or equal to 7. That is, the material of the capacitor dielectric layer 120 is a high dielectric constant material, so that the insulation performance of the capacitor dielectric layer can be improved, and the direct leakage current of the lower electrode layer 110 and the upper electrode layer 140 can be reduced, so that the reliability of the semiconductor structure can be improved.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the disclosure, and the scope of the embodiments of the disclosure should be assessed accordingly to that of the appended claims.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a plurality of lower electrode layers arranged at intervals, wherein each of the plurality of lower electrode layers is positioned on the surface of the substrate;
forming a capacitance dielectric layer, wherein the capacitance dielectric layer covers the surface of each lower electrode layer;
Forming an upper electrode layer, wherein the upper electrode layer covers the surface of the capacitance medium layer, and grooves are formed by surrounding the upper electrode layers between the adjacent lower electrode layers;
forming a seed crystal layer, wherein the seed crystal layer covers the surface of the upper electrode layer, the seed crystal layer is not filled in the groove, and the seed crystal layer contains a fourth main group element, and the fourth main group element is germanium element;
a semiconductor conductive layer is formed along the surface of the seed crystal layer in a growing mode, the semiconductor conductive layer covers the surface of the seed crystal layer and fills the groove, and the semiconductor conductive layer is a polycrystalline material layer doped with the fourth main group element;
providing a germanium source gas and a silicon source gas to form a germanium-doped silicon seed layer, wherein in the process step of forming the seed layer, the gas flow rate of the germanium source gas is gradually reduced, so that the closer to one side of the substrate the seed layer is formed, the higher the doped germanium ion concentration is, the closer to one side of the semiconductor conductive layer is, and the lower the doped germanium ion concentration is;
the concentration of the fourth main group element in the semiconductor conductive layer is less than the concentration of the fourth main group element in the seed layer.
2. The method of claim 1, wherein the seed layer is formed using a pressure vapor deposition process at a pressure of 1-0.01 torr, and wherein the process temperature for forming the seed layer is less than or equal to 400 ℃.
3. The method of claim 1, wherein the semiconductor conductive layer is formed by a pressure vapor deposition process at a temperature of 1-0.01 torr, and wherein the process temperature for forming the semiconductor conductive layer is less than or equal to 420 ℃.
4. The method of claim 3, wherein the forming the semiconductor conductive layer comprises: providing a silicon source gas and a germanium source gas to grow a polysilicon layer doped with germanium along the surface of the seed crystal layer, wherein the ratio of the gas flow rate of the silicon source gas to the gas flow rate of the germanium source gas is in the range of 0.5-5.
5. The method of fabricating a semiconductor structure of claim 1, wherein the method of forming the upper electrode layer comprises:
forming a sacrificial layer and a supporting layer which are alternately stacked on the substrate, wherein the top layer is formed by the supporting layer;
etching the sacrificial layer and the supporting layer to form a plurality of capacitor holes penetrating through the sacrificial layer and the supporting layer;
Forming a lower electrode layer within each of the plurality of capacitor holes;
forming a capacitor opening on the top layer, removing the sacrificial layer along the capacitor opening, and supporting the lower electrode layer by the rest supporting layer;
performing first wet cleaning on the lower electrode layer;
forming a capacitance medium layer on the surface of the cleaned lower electrode layer;
forming an initial upper electrode layer on the surface of the capacitance dielectric layer;
and performing second wet cleaning on the initial upper electrode layer to form the upper electrode layer, and then forming the seed crystal layer on the surface of the upper electrode layer, wherein the solutions of the first wet cleaning and the second wet cleaning are different.
6. The method of claim 5, wherein the aspect ratio of the capacitor hole is 20 or more: 1.
7. the method according to claim 5 or 6, wherein the electrode material of the lower electrode layer and/or the upper electrode layer is titanium nitride and/or titanium silicide nitride.
8. The method of manufacturing a semiconductor structure according to claim 5, wherein the first wet cleaning is performed using a hydrofluoric acid solution having an amount concentration of 0.1% -1%, and the second wet cleaning is performed using a hydrofluoric acid solution having an amount concentration of 1% -5%.
9. A semiconductor structure, comprising:
a substrate;
a plurality of lower electrode layers arranged at intervals, each of the plurality of lower electrode layers being located on the surface of the substrate;
the capacitor dielectric layer covers the surface of each lower electrode layer;
the upper electrode layer covers the surface of the capacitance medium layer, and grooves are formed by surrounding the upper electrode layers between the adjacent lower electrode layers;
a seed layer covering the surface of the upper electrode layer, the seed layer not filling the trench and containing a fourth main group element, the fourth main group element being a germanium element, the seed layer being a germanium-doped silicon seed layer;
the semiconductor conductive layer covers the surface of the seed crystal layer and fills the groove, and the semiconductor conductive layer is a polycrystalline material layer doped with the fourth main group element;
wherein the closer the seed layer is to one side of the substrate, the higher the doped germanium ion concentration is, and the closer is to one side of the semiconductor conductive layer, the lower the doped germanium ion concentration is;
the concentration of the fourth main group element in the semiconductor conductive layer is less than the concentration of the fourth main group element in the seed layer.
10. The semiconductor structure of claim 9, wherein the seed layer has a thickness of 0.1-3 nm in a direction perpendicular to the substrate surface.
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| CN113851584A (en) * | 2021-10-08 | 2021-12-28 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
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