CN116056551A - Anti-ferromagnetic tunnel junction and preparation method thereof - Google Patents
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Abstract
The invention discloses an antiferromagnetic tunnel junction and a preparation method thereof, wherein an insulating oxide layer is firstly deposited on a monocrystalline silicon wafer, then a collinear antiferromagnetic pinning layer is deposited on the insulating oxide layer, then a non-collinear antiferromagnetic reference layer, a tunneling layer and a non-collinear antiferromagnetic free layer are sequentially deposited on the collinear antiferromagnetic pinning layer, and finally the total antiferromagnetic tunnel junction with the insulating oxide layer-the collinear antiferromagnetic pinning layer-the non-collinear antiferromagnetic reference layer-the tunneling layer-the non-collinear antiferromagnetic free layer is realized on the silicon wafer by combining a photoetching process.
Description
Technical Field
The application relates to the technical field of magnetic memories and microelectronic manufacturing, in particular to an antiferromagnetic tunnel junction and a preparation method thereof.
Background
With the rise of the emerging information technologies such as 5G, internet of things, big data, cloud computing, artificial intelligence and the like and the popularization of mobile equipment, information interaction between electronic products is faster and faster, data flow is larger and larger, and a traditional semiconductor memory chip gradually encounters a performance bottleneck. In this context, magnetic Random Access Memory (MRAM) has received a great deal of attention in the microelectronics field due to its advantages of fast read and write speeds, nonvolatile data storage, and the like.
In a magnetoresistive random access memory, the core of the data storage unit is a Magnetic Tunnel Junction (MTJ), and the simplest magnetic tunnel junction comprises a four-layer structure, specifically a free layer-tunneling layer-reference layer-pinning layer, wherein the free layer and the reference layer are made of ferromagnetic materials, the pinning layer is made of collinear antiferromagnetic materials, and the spin directions of the free layer and the reference layer are turned over together under the control of an external magnetic field.
Through the development of the magnetic field driving type magnetic memory (Toggle-MRAM), spin transfer torque magnetic random access memory (STT-MRAM) and spin orbit torque magnetic random access memory (SOT-MRAM) technologies, although the magnetic random access memory has the performance of a shoulder dynamic random access memory (SRAM), energy consumption, non-volatility of a flash memory and the like, the magnetic random access memory is limited by the nature of ferromagnetic coupling among spins in ferromagnetic materials, and a ferromagnetic tunnel junction cannot meet the information processing requirement of exponential growth in the future.
Antiferromagnetic materials are considered as ideal candidates for free and reference layers in next generation high speed, high density magnetic random access memories due to their near zero stray magnetic fields, high spin dynamics frequencies, and the like, as compared to ferromagnetic materials. Therefore, how to prepare an antiferromagnetic tunnel junction with excellent performance based on antiferromagnetic materials is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides an antiferromagnetic tunnel junction and a preparation method thereof, so that the antiferromagnetic tunnel junction with excellent performance is prepared based on antiferromagnetic materials.
In order to achieve the above purpose, the embodiment of the present application provides the following technical solutions:
a antiferromagnetic tunnel junction comprising:
a silicon substrate;
the device comprises a silicon substrate, an insulating oxide layer, a pinning layer, a reference layer, a tunneling layer and a free layer, wherein the insulating oxide layer, the pinning layer, the reference layer, the tunneling layer and the free layer are sequentially arranged on one side of the silicon substrate along the direction deviating from the silicon substrate, the insulating oxide layer is a single crystal film layer, the pinning layer is a collinear antiferromagnetic material layer, and the reference layer and the free layer are non-collinear antiferromagnetic material layers.
Optionally, the method further comprises:
and the metal layer is positioned on one side of the free layer away from the silicon substrate.
Optionally, the insulating oxide layer is SrTiO 3 Layer, mgAl 2 O 4 Layer, laAlO 3 A layer or MgO layer.
Optionally, the pinning layer is a MnPt layer or a MnIr layer.
Optionally, the tunneling layer is an MgO layer, mgAl 2 O 4 Layers or Al 2 O 3 A layer.
Optionally, the reference layer is Mn 3 Sn layer, mn 3 Ge layer, mn 3 Ga layer, mn 3 Pt layer, mn 3 Ir layer or Mn 3 A Rh layer;
the free layer and the reference layer are the same layer of non-collinear antiferromagnetic material.
Optionally, in a direction perpendicular to a plane of the silicon substrate, the thickness d of the free layer satisfies: d is more than or equal to 5nm and less than or equal to 20nm.
Optionally, the metal layer is an Au layer, a Pt layer, a W layer, an Ag layer or a Cu layer.
A preparation method of a antiferromagnetic tunnel junction comprises the following steps:
providing a silicon wafer;
carrying out surface treatment on the silicon wafer to obtain a monocrystalline silicon wafer;
sequentially depositing an insulating oxide layer, a pinning layer, a reference layer, a tunneling layer and a free layer along the direction deviating from the monocrystalline silicon wafer on one side of the monocrystalline silicon wafer to obtain a laminated structure, wherein the insulating oxide layer is a monocrystalline film layer, the pinning layer is a collinear antiferromagnetic material layer, and the reference layer and the free layer are both non-collinear antiferromagnetic material layers;
annealing the laminated structure in a magnetic field vacuum annealing furnace to enhance the exchange interaction between the pinning layer and the reference layer and fix the magnetic moment direction of the reference layer;
and etching the laminated structure to obtain a plurality of antiferromagnetic tunnel junctions.
Optionally, after depositing the free layer, the method further comprises:
and depositing a metal layer on one side of the free layer, which is away from the monocrystalline silicon wafer, so that the laminated structure further comprises the metal layer.
Compared with the prior art, the technical scheme has the following advantages:
the antiferromagnetic tunnel junction provided by the embodiment of the application is a total antiferromagnetic tunnel junction with a silicon substrate, an insulating oxide layer, a collinear antiferromagnetic pinning layer, a non-collinear antiferromagnetic reference layer, a tunneling layer and a non-collinear antiferromagnetic free layer, and the reference layer and the free layer are both non-collinear antiferromagnetic material layers, so that the antiferromagnetic tunnel junction has the advantages of high writing speed and high storage density; in the second aspect, the silicon substrate may be a silicon wafer, that is, the antiferromagnetic tunnel junction may be fabricated on a large scale on the silicon wafer, which facilitates integration; in the third aspect, an insulating oxide layer is added between the silicon substrate and the collinear antiferromagnetic pinning layer, and the insulating oxide layer is a monocrystalline film layer, so that the quality of the collinear antiferromagnetic pinning layer and the interface quality between the collinear antiferromagnetic pinning layer and the non-collinear antiferromagnetic reference layer are improved, the exchange bias effect between the collinear antiferromagnetic pinning layer and the non-collinear antiferromagnetic reference layer is enhanced, the magnetic moment direction of the non-collinear antiferromagnetic reference layer can be pinned by the collinear antiferromagnetic pinning layer, and the reliability of the device is improved. It can be seen that the antiferromagnetic tunnel junction is an antiferromagnetic tunnel junction with excellent performance prepared based on antiferromagnetic materials.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an antiferromagnetic tunnel junction according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of another antiferromagnetic tunnel junction according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a structure of yet another antiferromagnetic tunnel junction according to an embodiment of the present application;
FIG. 4 is a schematic flow chart of a method for fabricating an antiferromagnetic tunnel junction according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a method for forming an antiferromagnetic tunnel junction by depositing SrTiO on a monocrystalline silicon wafer 3 An X-ray diffraction pattern of the resulting semifinished product after collinear antiferromagnetic pinning layers;
fig. 6 is a schematic flow chart of another method for fabricating an antiferromagnetic tunnel junction according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the schematic drawings, wherein the cross-sectional views of the device structure are not to scale for the sake of illustration, and the schematic drawings are merely examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
As described in the background section, how to prepare an antiferromagnetic tunnel junction with excellent performance based on antiferromagnetic materials is a technical problem to be solved by those skilled in the art.
In view of this, the embodiment of the present application provides an antiferromagnetic tunnel junction, and fig. 1 shows a schematic structural diagram of the antiferromagnetic tunnel junction provided in the embodiment of the present application, and as shown in fig. 1, the antiferromagnetic tunnel junction includes:
a silicon substrate 10;
the device comprises an insulating oxide layer 20, a pinning layer 30, a reference layer 40, a tunneling layer 50 and a free layer 60 which are sequentially arranged along the direction away from the silicon substrate 10 and are positioned on one side of the silicon substrate 10, wherein the insulating oxide layer 20 is a single crystal film layer, the pinning layer 30 is a collinear antiferromagnetic material layer, and the reference layer 40 and the free layer 60 are non-collinear antiferromagnetic material layers.
Unlike the ferromagnetic material layers in the ferromagnetic tunnel junction where the reference layer and the free layer are both ferromagnetic material layers, in the present embodiment of the present application the reference layer 40 and the free layer 60 are no longer ferromagnetic material layers, but are non-collinear antiferromagnetic material layers, i.e., the reference layer 40 is a non-collinear antiferromagnetic reference layer and the free layer 60 is a non-collinear antiferromagnetic free layer.
The inventors have found that, in the past, research on the antiferromagnetic material has been focused on the collinear antiferromagnetic material, but the collinear antiferromagnetic material has almost no response to the external magnetic field due to mutual cancellation between magnetic resistances, so that the research on the antiferromagnetic tunnel junction based on the collinear antiferromagnetic material has been very slow. Non-collinear antiferromagnetic materials such as Mn, which have been newly discovered in recent years 3 Sn, etc., the magnetic lattice of which has a very small uncompensated complete magnetic moment which can be controlled by an external magnetic field or current, and lays a material and theoretical foundation for the research of an antiferromagnetic tunnel junction.
Therefore, in the antiferromagnetic tunnel junction provided in the embodiments of the present application, the reference layer 40 and the free layer 60 are both non-collinear antiferromagnetic material layers, so that after the magnetic moment direction of the non-collinear antiferromagnetic reference layer 40 is pinned by the pinning layer 30, the magnetic moment direction of the non-collinear antiferromagnetic free layer 60 can be parallel or antiparallel to the magnetic moment direction of the non-collinear antiferromagnetic reference layer 40 under the external magnetic field or current manipulation, respectively, so that the antiferromagnetic tunnel junction is in a low resistance state or a high resistance state, and a memory function is realized.
In addition, unlike ferromagnetic materials, the magnetic moments of the antiferromagnetic materials are arranged in a mode that macroscopic magnetic moments are zero, antiferromagnetic coupling is achieved, the intrinsic spin dynamics frequency can reach THz, the antiferromagnetic materials are three orders of magnitude higher than that of the ferromagnetic materials, stray magnetic fields are avoided, and the antiferromagnetic materials are insensitive to magnetic fields, so that the tunnel junction using the non-collinear antiferromagnetic materials as a storage medium provided by the embodiment of the application has the advantages of high writing speed and high storage density, and has great development potential in the field of microelectronics.
In the embodiment of the present application, the silicon substrate 10 may be a silicon wafer, that is, the antiferromagnetic tunnel junction provided in the embodiment of the present application may be fabricated on a large scale on the silicon wafer, which is beneficial for integration.
In the present embodiment, the pinning layer 30 is a collinear antiferromagnetic material layer, i.e., the pinning layer 30 is a collinear antiferromagnetic pinning layer.
The inventor further researches and discovers that for the existing ferromagnetic tunnel junction, the pinning layer is a collinear antiferromagnetic material layer, namely a collinear antiferromagnetic pinning layer, and the reference layer is a ferromagnetic material layer, namely a ferromagnetic reference layer, at the moment, because the interaction between the collinear antiferromagnetic pinning layer and the ferromagnetic reference layer is stronger, the magnetic moment direction of the ferromagnetic reference layer can be pinned by the collinear antiferromagnetic pinning layer.
With the antiferromagnetic tunnel junction provided in the embodiments of the present application, after both the reference layer 40 and the free layer 60 are made of non-collinear antiferromagnetic material layers, the magnetic moment direction of the non-collinear antiferromagnetic reference layer 40 is difficult to be pinned by the collinear antiferromagnetic pinning layer 30 due to the strong correlation between the coupling effect between the antiferromagnetic materials and the interface quality, which can seriously affect device performance when the quality of the collinear antiferromagnetic pinning layer 30 or the interface quality between the collinear antiferromagnetic pinning layer 30 and the non-collinear antiferromagnetic reference layer 40 is poor.
This is because there is an interface difference between the silicon substrate 10 and the collinear antiferromagnetic pinning layer 30, which makes the quality of the collinear antiferromagnetic pinning layer 30 deposited directly on the silicon substrate 10 poor, and thus makes the quality of the interface between the collinear antiferromagnetic pinning layer 30 and the non-collinear antiferromagnetic reference layer 40 poor when the non-collinear antiferromagnetic reference layer 40 is deposited on the collinear antiferromagnetic pinning layer 30 again, and the magnetic moment direction of the non-collinear antiferromagnetic reference layer 40 is difficult to be pinned by the collinear antiferromagnetic pinning layer 30.
Based on this, in the antiferromagnetic tunnel junction provided in the embodiment of the application, the insulating oxide layer 20 is added between the silicon substrate 10 and the collinear antiferromagnetic pinning layer 30, that is, the insulating oxide layer 20 is formed by first depositing on the silicon substrate 10, then the collinear antiferromagnetic pinning layer 30 is formed by depositing on the insulating oxide layer 20, and the insulating oxide layer 20 is a single crystal film layer, and since the crystal lattice orientations of the single crystal film layers are consistent, the quality of the collinear antiferromagnetic pinning layer 30 deposited on the insulating oxide layer 20 is better, and further, when the non-collinear antiferromagnetic reference layer 40 is formed by redeposition on the collinear antiferromagnetic pinning layer 30 with better quality, the interface quality between the collinear antiferromagnetic pinning layer 30 and the non-collinear antiferromagnetic reference layer 40 is also better, so that the exchange bias effect between the collinear antiferromagnetic pinning layer 30 and the non-collinear antiferromagnetic reference layer 40 is enhanced, and the magnetic moment direction of the non-collinear antiferromagnetic reference layer 40 can be pinned by the collinear antiferromagnetic pinning layer 30, and the reliability of the device is improved.
Therefore, the antiferromagnetic tunnel junction provided by the embodiment of the application is a full antiferromagnetic tunnel junction with a silicon substrate 10-an insulating oxide layer 20-a collinear antiferromagnetic pinning layer 30-a non-collinear antiferromagnetic reference layer 40-a tunneling layer 50-a non-collinear antiferromagnetic free layer 60, and the reference layer 40 and the free layer 60 are both non-collinear antiferromagnetic material layers, so that the antiferromagnetic tunnel junction has the advantages of high writing speed and high storage density, and has great development potential in the microelectronics field; in a second aspect, the silicon substrate 10 may be a silicon wafer, i.e. the antiferromagnetic tunnel junction may be fabricated on a large scale on a silicon wafer, facilitating integration; in a third aspect, an insulating oxide layer 20 is added between the silicon substrate 10 and the collinear antiferromagnetic pinning layer 30, and the insulating oxide layer 20 is a single crystal film layer, so as to improve the quality of the collinear antiferromagnetic pinning layer 30 and the interface quality between the collinear antiferromagnetic pinning layer 30 and the non-collinear antiferromagnetic reference layer 40, enhance the exchange bias between the collinear antiferromagnetic pinning layer 30 and the non-collinear antiferromagnetic reference layer 40, and further enable the magnetic moment direction of the non-collinear antiferromagnetic reference layer 40 to be pinned by the collinear antiferromagnetic pinning layer 30, and improve the reliability of the device. It can be seen that the antiferromagnetic tunnel junction is an antiferromagnetic tunnel junction with excellent performance prepared based on antiferromagnetic materials.
Alternatively, in one embodiment of the present application, the insulating oxide layer 20 may be SrTiO 3 Layer, mgAl 2 O 4 Layer, laAlO 3 A layer or MgO layer.
Alternatively, in one embodiment of the present application, the thickness of the insulating oxide layer 20 may be 3nm to 500nm, inclusive, in a direction perpendicular to the plane of the silicon substrate 10, but the present application is not limited thereto, as the case may be.
Alternatively, in one embodiment of the present application, the pinning layer 30 may be a manganese-based collinear antiferromagnetic material layer, and in particular, the pinning layer 30 may be a MnPt layer or a MnIr layer.
Alternatively, in one embodiment of the present application, the thickness of the pinning layer 30 may be 5nm-100nm, inclusive, in a direction perpendicular to the plane of the silicon substrate 10, although the present application is not limited thereto, as the case may be.
Alternatively, in one embodiment of the present application, tunneling layer 50 may be a MgO layer, mgAl 2 O 4 Layers or Al 2 O 3 A layer. Tunneling layer 50 acts as a tunnel to increase the signal.
Alternatively, in one embodiment of the present application, the thickness of the tunneling layer 50 may be 1nm-3nm, inclusive, in a direction perpendicular to the plane of the silicon substrate 10, but the present application is not limited thereto, as the case may be.
Alternatively, in one embodiment of the present application, the reference layer 40 may be Mn 3 Sn layer, mn 3 Ge layer, mn 3 Ga layer, mn 3 Pt layer, mn 3 Ir layer or Mn 3 A Rh layer;
the free layer 60 and the reference layer 40 are the same layer of non-collinear antiferromagnetic material.
In the present embodiment, the free layer 60 and the reference layer 40 are the same layer of non-collinear antiferromagnetic material, e.g., the free layer 60 and the reference layer 40 are both Mn 3 The Ge layer, and thus the magnetic moment of the non-collinear antiferromagnetic reference layer 40, is pinned by the pinning layer 30, the magnetic moment of the non-collinear antiferromagnetic free layer 60 is relatively easily parallel or antiparallel to the magnetic moment of the non-collinear antiferromagnetic reference layer 40, respectively, under external magnetic field or current manipulation, thereby placing the antiferromagnetic tunnel junction in a low or high resistance state.
The inventors have further studied that the coercive field of a non-collinear antiferromagnetic material is relatively large compared to that of a ferromagnetic material, whereas the coercive field of a non-collinear antiferromagnetic material has a very strong thickness dependent characteristic, and that the thickness of the non-collinear antiferromagnetic free layer 60 in a direction perpendicular to the plane of the silicon substrate 10 can be reduced in order to achieve a free layer 60 of low coercive field. Thus, alternatively, in one embodiment of the present application, the thickness d of the free layer 60 in a direction perpendicular to the plane of the silicon substrate 10 satisfies: d is more than or equal to 5nm and less than or equal to 20nm.
In the present embodiment, the thickness d of the free layer 60 is set to 5nm-20nm, inclusive, in the direction perpendicular to the plane of the silicon substrate 10, so that the coercive field of the free layer 60 can be effectively reduced, thereby realizing a high-performance, low-power-consumption antiferromagnetic tunnel junction.
Alternatively, in one embodiment of the present application, the thickness of the reference layer 40 may be 10nm-50nm, inclusive, in a direction perpendicular to the plane of the silicon substrate 10. However, the present application is not limited thereto, and the present application is not limited thereto as the case may be.
FIG. 2 shows a schematic structural diagram of another antiferromagnetic tunnel junction provided in an embodiment of the present application, and as shown in FIG. 2, the antiferromagnetic tunnel junction may further include:
a metal layer 70 on the side of the free layer 60 facing away from the silicon substrate 10.
It should be noted that some non-collinear antiferromagnetic materials are susceptible to oxidation, and that to protect the non-collinear antiferromagnetic free layer 60 from oxidation, a metal layer 70 may be provided on the side of the free layer 60 facing away from the silicon substrate 10. Of course, a protective effect may be provided by covering the metal layer 70 with a non-collinear antiferromagnetic material layer that is not easily oxidized.
Alternatively, in one embodiment of the present application, the metal layer 70 may be an Au layer, a Pt layer, a W layer, an Ag layer, or a Cu layer.
Alternatively, in one embodiment of the present application, the thickness of the metal layer 70 may be 3nm-100nm, inclusive, in a direction perpendicular to the plane of the silicon substrate 10. However, the present application is not limited thereto, and the present application is not limited thereto as the case may be.
FIG. 3 shows a schematic structure of yet another antiferromagnetic tunnel junction provided in an embodiment of the present application, as shown in FIG. 3, comprising a silicon substrate 10, srTiO arranged in sequence 3 Insulating oxide layer 20, mnIr collinear antiferromagnetic pinning layer 30, mn 3 Ge non-collinear antiferromagnetic reference layer 40, mgO tunneling layer 50, mn 3 A Ge non-collinear antiferromagnetic free layer 60 and a Pt metal layer 70. Wherein SrTiO 3 The insulating oxide layer 20 may be 5nm, the MnIr collinear antiferromagnetic pinning layer 30 may be 10nm, mn 3 The Ge non-collinear antiferromagnetic reference layer 40 may be 10nm, the MgO tunneling layer 50 may be 2nm, mn 3 The Ge non-collinear antiferromagnetic free layer 60 may be 5nm and the pt metal layer 70 may be 4nm.
The embodiment of the application also provides a preparation method of the antiferromagnetic tunnel junction, and fig. 4 shows a schematic flow chart of the preparation method of the antiferromagnetic tunnel junction provided by the embodiment of the application, as shown in fig. 4, the method includes:
s100: a silicon wafer is provided.
S200: the surface treatment is performed on the silicon wafer to obtain a single crystal silicon wafer, i.e., a single crystal silicon substrate 10.
In order to obtain good quality of each film layer deposited on the silicon wafer, impurities and SiO on the surface of the silicon wafer need to be removed 2 A layer is formed to give a single crystal silicon wafer 10 for depositing a subsequent film layer on the single crystal silicon wafer 10.
Specifically, in step S200, performing surface treatment on a silicon wafer to obtain a single crystal silicon wafer includes:
s210: and removing impurities on the surface of the silicon wafer.
Specifically, the silicon wafer is placed in deionized water and subjected to ultrasonic treatment for a period of time, such as 10 minutes, to remove impurities on the surface of the silicon wafer.
S220: siO on the surface of silicon wafer is removed by adopting buffer oxide etching liquid 2 And removing the residual buffer oxide etching liquid on the surface of the silicon wafer to obtain the monocrystalline silicon wafer.
Specifically, the silicon wafer after ultrasonic cleaning is placed in a buffer oxide etching solution for a period of time, such as 30s, to remove SiO on the surface of the silicon wafer 2 The layer can be made of HF and NH as buffer oxide etching liquid 4 F and H 2 O, wherein the mass fraction of HF can be 4.5%, NH 4 The mass fraction of F may be 36.5%; then the silicon wafer is placed in deionized water again for ultrasonic treatment for a period of time, such as 10min, so as to remove the residual buffer oxide etching solution and SiO on the surface of the silicon wafer 2 A single crystal silicon wafer is obtained, for example, in which Si is oriented to (001).
S300: referring to fig. 1, an insulating oxide layer 20, a pinning layer 30, a reference layer 40, a tunneling layer 50, and a free layer 60 are sequentially deposited on a side of a monocrystalline silicon wafer 10 in a direction away from the monocrystalline silicon wafer 10 to obtain a stacked structure 100, wherein the insulating oxide layer 20 is a monocrystalline film layer, the pinning layer 30 is a collinear antiferromagnetic material layer, and the reference layer 40 and the free layer 60 are non-collinear antiferromagnetic material layers.
In the embodiment of the present application, the stacked structure includes a monocrystalline silicon wafer 10, and an insulating oxide layer 20, a pinning layer 30, a reference layer 40, a tunneling layer 50, and a free layer 60, which are sequentially arranged on one side of the monocrystalline silicon wafer 10 in a direction away from the monocrystalline silicon wafer 10.
In step S300, the deposition manner of each film layer may include magnetron sputtering deposition, molecular beam epitaxy deposition, ion beam deposition, pulse laser deposition, chemical vapor deposition, etc., and in the following, the magnetron sputtering deposition is taken as an example, and step S300 is specifically described.
First, a monocrystalline silicon wafer 10 is glued onto a magnetron sputtering sample stage by means of silver nanoparticle conductive glue.
Specifically, the silver nanoparticle conductive adhesive is uniformly coated on the back surface of the monocrystalline silicon wafer 10, the monocrystalline silicon wafer 10 is adhered on the magnetron sputtering sample stage by utilizing the silver nanoparticle conductive adhesive, and the magnetron sputtering sample stage and the monocrystalline silicon wafer 10 are cured for 1 hour at 60 ℃ so as to enhance heat transfer between the magnetron sputtering sample stage and the monocrystalline silicon wafer 10, wherein the used silver nanoparticle conductive adhesive can be a mixture of silver nanoparticles and epoxy resin, the mass fraction of the silver nanoparticles can be 40%, and the mass fraction of the epoxy resin can be 60%.
Secondly, vacuumizing the magnetron sputtering chamber to a preset vacuum degree.
Specifically, the magnetron sputtering chamber can be evacuated to 1×10 -6 Pa；
Third, vacuum annealing is performed on the single crystal silicon wafer 10 to remove adsorbed gas on the surface of the single crystal silicon wafer 10.
In step S220, the buffer oxide etching solution is used to remove SiO on the surface of the silicon wafer 2 When in layer, the buffer oxide etching liquid can be mixed with SiO 2 The layer reaction generates gases which may be adsorbed on the surface of the single crystal silicon wafer, and thus vacuum annealing of the single crystal silicon wafer is required to remove the adsorbed gases on the surface of the single crystal silicon wafer, wherein the annealing temperature may be not lower than 500 ℃, and the vacuum degree in the annealing chamber may be more than 10% -4 Pa。
Specifically, the temperature in the magnetron sputtering chamber is raised to a set temperature (such as 700 ℃) at a certain heating rate (such as 5 ℃/min), the temperature is kept for a period of time (such as 60 min) so as to remove the adsorbed gas on the surface of the monocrystalline silicon wafer 10, and after the heat preservation process is finished, the temperature in the magnetron sputtering chamber is cooled to another set temperature (such as 600 ℃) at a certain cooling rate (such as 5 ℃/min) for standby.
Fourth, argon is introduced into the magnetron sputtering chamber, and meanwhile, a molecular pump gate valve is adjusted to enable the air pressure in the magnetron sputtering chamber to reach the set air pressure, and the sample table is started to rotate.
Specifically, argon with purity of over 99.999 percent can be introduced into the magnetron sputtering chamber, the flow rate of the argon can be 20 milliliters per minute, meanwhile, the molecular pump gate valve is adjusted, so that the air pressure in the magnetron sputtering chamber reaches 3 millitorr, the sample stage is started to rotate, and the rotating speed of the sample stage can be set to 20 revolutions per minute.
Fifthly, closing a baffle of a sample table in the magnetron sputtering chamber, opening a baffle of a target in the magnetron sputtering chamber, and performing pre-sputtering for a period of time (such as 5 min) to remove impurities on the surface of the target.
Sixthly, opening the sample table baffle and the radio frequency power supply, setting the power of the radio frequency power supply as preset power, opening the target baffle, and depositing a film layer.
The fifth step and the sixth step are repeated, and different targets on different targets are adopted to deposit an insulating oxide layer 20, a pinning layer 30, a reference layer 40, a tunneling layer 50 and a free layer 60 on the monocrystalline silicon wafer 10 in sequence, wherein specific preparation parameters such as temperature, air pressure and the like in the film deposition process depend on the selected deposition materials.
For example, as shown in FIG. 3, in the stacked structure 100, the insulating oxide layer 20 is SrTiO 3 The thickness of the layer is 5nm, the power of a radio frequency power supply during magnetron sputtering is 120W, and the deposition rate is 0.15nm/min; the collinear antiferromagnetic pinning layer 30 is a MnIr layer with the thickness of 10nm, and adopts a direct current power supply to carry out magnetron sputtering, the sputtering power is 60W, and the deposition rate is 0.87nm/min; the non-collinear antiferromagnetic reference layer 40 is Mn 3 The thickness of the Ge layer is 10nm, the magnetron sputtering is carried out by adopting a direct current power supply, the sputtering power is 60W, and the deposition rate is 0.93nm/min; tunneling layer 50 is a MgO layer having a thickness of 2nm; the non-collinear antiferromagnetic free layer 60 is Mn 3 The Ge layer has a thickness of 5nm, and is subjected to magnetron sputtering by adopting a direct current power supply, wherein the sputtering power is 60W, and the deposition rate is 0.93nm/min. All targets can be 60mm in diameter and thicknessMay be 5mm, the purity may be 99.99%, and the spacing between the target and the monocrystalline silicon wafer may be 24cm.
After the deposition is completed, the temperature is kept for a period of time (such as 1 min) at a certain temperature (such as 600 ℃), then the temperature is reduced to room temperature at a certain cooling rate (5 ℃/min), and the magnetron sputtering deposition chamber is inflated to ensure that the air pressure reaches the atmospheric pressure.
S400: the stack 100 is annealed in a magnetic field vacuum annealing furnace to enhance the exchange interaction between the pinned layer 30 and the reference layer 40, fixing the magnetic moment orientation of the reference layer 40.
Specifically, the stacked structure 100 is removed from the magnetron sputter deposition chamber and annealed in a magnetic field vacuum annealing oven to enhance the exchange coupling between the collinear antiferromagnetic pinning layer 30 and the non-collinear antiferromagnetic reference layer 40.
It should be noted that the specific annealing parameters are related to the non-collinear antiferromagnetic material used for the reference layer. Specifically, when the pinning layer 30 is a MnIr layer, the reference layer 40 is Mn 3 When the Ge layer is used, the annealing temperature can be 250 ℃, the magnetic field can be 500 millitesla, the temperature rise and fall rate can be 5 ℃/min, and the vacuum degree in the magnetic field vacuum annealing furnace can be 10 millitorr.
Fig. 5 shows the deposition of SrTiO on a monocrystalline silicon wafer 10 3 Layer as X-ray diffraction pattern of the semifinished product obtained from the insulating oxide layer 20, srTiO 3 (001) And Si (001) series diffraction peaks, srTiO 3 The insulating oxide layer 20 and the single crystal Si substrate 10 have a high epitaxial quality.
S500: the stacked structure 100 is etched to obtain a plurality of antiferromagnetic tunnel junctions.
Specifically, photoresist is uniformly applied to the annealed stacked structure 100, and after photolithography, exposure and development, the redundant portions of the stacked structure 100 are etched and removed, so as to obtain a plurality of antiferromagnetic tunnel junctions. The lithography mode may include ultraviolet lithography, ion beam lithography or electron beam lithography, and the etching mode may include mask etching, reactive ion etching or ion beam etching. The specific photolithography and etching modes are not limited, and may be a combination of multiple processes, and may be specific to each layer of material of the antiferromagnetic tunnel junction.
Finally, an array of antiferromagnetic tunnel junctions with a diameter of 200nm may be obtained on the monocrystalline silicon wafer 10, wherein one antiferromagnetic tunnel junction element may have a characteristic dimension of 10nm-300nm, inclusive.
Therefore, the antiferromagnetic tunnel junction prepared by the method provided by the embodiment of the application has the following advantages:
(1) In the removal of SiO 2 The insulating oxide layer 20 is deposited first, and then the collinear antiferromagnetic pinning layer 30 is deposited on the insulating oxide layer 20, and the quality of the collinear antiferromagnetic pinning layer 30 can be improved, so that high-quality growth of the large-size collinear antiferromagnetic pinning layer 30 is realized, and a good foundation is laid for preparation of the non-collinear antiferromagnetic reference layer 40 and generation of exchange coupling.
(2) By adopting the non-collinear antiferromagnetic material layer as the reference layer 40, a high-quality interface can be formed with the collinear antiferromagnetic pinning layer 30, so that the exchange coupling effect between two films is greatly improved, the magnetic moment direction of the non-collinear antiferromagnetic reference layer 40 can be pinned by the collinear antiferromagnetic pinning layer 30, and the reliability of the device is improved.
(3) The preparation method of the antiferromagnetic tunnel junction is simple and easy to realize, and is compatible with related processes of the traditional semiconductor or ferromagnetic tunnel junction.
(4) The reference layer 40 and the free layer 60 are both non-collinear antiferromagnetic material layers, and the antiferromagnetic material magnetic moments are arranged in a mode that macroscopic magnetic moment is zero, so that antiferromagnetic coupling is realized, the intrinsic spin dynamics frequency can reach THz, the antiferromagnetic material has no stray magnetic field and is insensitive to magnetic field, and therefore, the antiferromagnetic tunnel junction has the advantages of high writing speed and high storage density, and has great development potential in the microelectronics field.
Therefore, the method provided by the embodiment of the application can be based on the antiferromagnetic tunnel junction with excellent performance prepared from the antiferromagnetic material.
Alternatively, in one embodiment of the present application, the insulating oxide layer 20 may be SrTiO 3 Layer, mgAl 2 O 4 Layer, laAlO 3 A layer or MgO layer.
Alternatively, in one embodiment of the present application, the thickness of the insulating oxide layer 20 may be 3nm to 500nm, inclusive, in a direction perpendicular to the plane of the silicon substrate 10, but the present application is not limited thereto, as the case may be.
Alternatively, in one embodiment of the present application, the pinning layer 30 may be a manganese-based collinear antiferromagnetic material layer, and in particular, the pinning layer 30 may be a MnPt layer or a MnIr layer.
Alternatively, in one embodiment of the present application, the thickness of the pinning layer 30 may be 5nm-100nm, inclusive, in a direction perpendicular to the plane of the silicon substrate 10, although the present application is not limited thereto, as the case may be.
Alternatively, in one embodiment of the present application, tunneling layer 50 may be a MgO layer, mgAl 2 O 4 Layers or Al 2 O 3 A layer. Tunneling layer 50 acts as a tunnel to increase the signal.
Alternatively, in one embodiment of the present application, the thickness of the tunneling layer 50 may be 1nm-3nm, inclusive, in a direction perpendicular to the plane of the silicon substrate 10, but the present application is not limited thereto, as the case may be.
Alternatively, in one embodiment of the present application, the reference layer 40 may be Mn 3 Sn layer, mn 3 Ge layer, mn 3 Ga layer, mn 3 Pt layer, mn 3 Ir layer or Mn 3 A Rh layer;
the free layer 60 and the reference layer 40 are the same layer of non-collinear antiferromagnetic material.
In the present embodiment, the free layer 60 and the reference layer 40 are the same layer of non-collinear antiferromagnetic material, e.g., the free layer 60 and the reference layer 40 are both Mn 3 A Ge layer such that after the magnetic moment of the non-collinear antiferromagnetic reference layer 40 is pinned by the pinning layer 30, the magnetic moment of the non-collinear antiferromagnetic free layer 60 is in an external magnetic or electrical fieldUnder flow manipulation, the magnetic moment directions of the non-collinear antiferromagnetic reference layer 40 are relatively easily parallel or antiparallel, respectively, thereby placing the antiferromagnetic tunnel junction in either a low resistance state or a high resistance state.
The inventors have further studied that the coercive field of a non-collinear antiferromagnetic material is relatively large compared to that of a ferromagnetic material, whereas the coercive field of a non-collinear antiferromagnetic material has a very strong thickness dependent characteristic, and that the thickness of the non-collinear antiferromagnetic free layer 60 in a direction perpendicular to the plane of the silicon substrate 10 can be reduced in order to achieve a free layer 60 of low coercive field. Thus, alternatively, in one embodiment of the present application, the thickness d of the free layer 60 in a direction perpendicular to the plane of the silicon substrate 10 satisfies: d is more than or equal to 5nm and less than or equal to 20nm.
In the present embodiment, the thickness d of the free layer 60 is set to 5nm-20nm, inclusive, in the direction perpendicular to the plane of the silicon substrate 10, so that the coercive field of the free layer 60 can be effectively reduced, thereby realizing a high-performance, low-power-consumption antiferromagnetic tunnel junction.
Alternatively, in one embodiment of the present application, the thickness of the reference layer 40 may be 10nm-50nm, inclusive, in a direction perpendicular to the plane of the silicon substrate 10. However, the present application is not limited thereto, and the present application is not limited thereto as the case may be.
FIG. 6 is a schematic flow chart of another method for fabricating an antiferromagnetic tunnel junction according to an embodiment of the disclosure, as shown in FIG. 6, after depositing the free layer 60, the method further comprises:
s600: referring to fig. 2 and 3, a metal layer 70 is deposited on the side of the free layer 60 facing away from the monocrystalline silicon wafer 10, such that the laminate structure 100 further includes the metal layer 70.
It should be noted that some non-collinear antiferromagnetic materials are susceptible to oxidation, and that to protect the non-collinear antiferromagnetic free layer 60 from oxidation, a metal layer 70 may be provided on the side of the free layer 60 facing away from the silicon substrate 10. Of course, a protective effect may be provided by covering the non-collinear antiferromagnetic free layer 60 with a metal layer 70 that is not readily oxidized.
Alternatively, in one embodiment of the present application, the metal layer 70 may be an Au layer, a Pt layer, a W layer, an Ag layer, or a Cu layer.
Wherein when the metal layer 70 is a Pt layer, an Au layer, the non-collinear antiferromagnetic free layer 60 can be protected from oxidation, and thus the annealing vacuum can be not required to be too high when the annealing is performed in step 400.
When the metal layer is a Pt layer, an Au layer, or a W layer, the non-collinear antiferromagnetic free layer 60 can also be used to reverse its magnetic moment direction with a current in addition to a magnetic field.
Alternatively, in one embodiment of the present application, the thickness of the metal layer 70 may be 3nm-100nm, inclusive, in a direction perpendicular to the plane of the silicon substrate 10. However, the present application is not limited thereto, and the present application is not limited thereto as the case may be.
Specifically, when the metal layer 70 is deposited by using a magnetron sputtering deposition method, as shown in fig. 3, taking the metal layer 70 as a Pt layer as an example, direct current power sputtering is adopted, the sputtering power may be 30W, and the growth rate may be 1.6nm/min.
In practical applications, referring to fig. 2 and 3, the collinear antiferromagnetic pinning layer 30 and the non-collinear antiferromagnetic reference layer 40 are typically used as bottom electrodes of the antiferromagnetic tunnel junction, the non-collinear antiferromagnetic free layer 60 and the metal layer 70 are typically used as top electrodes of the antiferromagnetic tunnel junction, and in step S500, when the stacked structure 100 is etched, the antiferromagnetic tunnel junction cell and its bottom and top electrodes are obtained, and then the bottom and top electrode connections can be prepared using the semiconductor standard damascene process to obtain the antiferromagnetic tunnel junction device on a silicon wafer.
In the description, each part is described in a parallel and progressive mode, and each part is mainly described as a difference with other parts, and all parts are identical and similar to each other.
The features described in the various embodiments of the present disclosure may be interchanged or combined with one another in the description to enable those skilled in the art to make or use the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A antiferromagnetic tunnel junction comprising:
a silicon substrate;
the device comprises a silicon substrate, an insulating oxide layer, a pinning layer, a reference layer, a tunneling layer and a free layer, wherein the insulating oxide layer, the pinning layer, the reference layer, the tunneling layer and the free layer are sequentially arranged on one side of the silicon substrate along the direction deviating from the silicon substrate, the insulating oxide layer is a single crystal film layer, the pinning layer is a collinear antiferromagnetic material layer, and the reference layer and the free layer are non-collinear antiferromagnetic material layers.
2. The antiferromagnetic tunnel junction of claim 1 further comprising:
and the metal layer is positioned on one side of the free layer away from the silicon substrate.
3. The antiferromagnetic tunnel junction according to claim 1 or 2, wherein said insulating oxide layer is SrTiO 3 Layer, mgAl 2 O 4 Layer, laAlO 3 A layer or MgO layer.
4. The antiferromagnetic tunnel junction according to claim 1 or 2, characterized in that said pinning layer is a MnPt layer or a MnIr layer.
5. The antiferromagnetic tunnel junction according to claim 1 or 2, wherein said tunneling layer is a MgO layer, mgAl 2 O 4 Layers or Al 2 O 3 A layer.
6. The antiferromagnetic tunnel junction according to claim 1 or 2, wherein said reference layer is Mn 3 Sn layer, mn 3 Ge layer, mn 3 Ga layer, mn 3 Pt layer, mn 3 Ir layer or Mn 3 A Rh layer;
the free layer and the reference layer are the same layer of non-collinear antiferromagnetic material.
7. The antiferromagnetic tunnel junction according to claim 1 or 2, characterized in that the thickness d of said free layer in a direction perpendicular to the plane of said silicon substrate satisfies: d is more than or equal to 5nm and less than or equal to 20nm.
8. The antiferromagnetic tunnel junction according to claim 2, wherein said metal layer is an Au layer, a Pt layer, a W layer, an Ag layer or a Cu layer.
9. The preparation method of the antiferromagnetic tunnel junction is characterized by comprising the following steps of:
providing a silicon wafer;
carrying out surface treatment on the silicon wafer to obtain a monocrystalline silicon wafer;
sequentially depositing an insulating oxide layer, a pinning layer, a reference layer, a tunneling layer and a free layer along the direction deviating from the monocrystalline silicon wafer on one side of the monocrystalline silicon wafer to obtain a laminated structure, wherein the insulating oxide layer is a monocrystalline film layer, the pinning layer is a collinear antiferromagnetic material layer, and the reference layer and the free layer are both non-collinear antiferromagnetic material layers;
annealing the laminated structure in a magnetic field vacuum annealing furnace to enhance the exchange interaction between the pinning layer and the reference layer and fix the magnetic moment direction of the reference layer;
and etching the laminated structure to obtain a plurality of antiferromagnetic tunnel junctions.
10. The method of fabricating a antiferromagnetic tunnel junction according to claim 9, further comprising, after depositing said free layer:
and depositing a metal layer on one side of the free layer, which is away from the monocrystalline silicon wafer, so that the laminated structure further comprises the metal layer.
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