CN116054820A - Programmable phase-locked loop circuit with out-of-lock calibration - Google Patents

Programmable phase-locked loop circuit with out-of-lock calibration Download PDF

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Publication number
CN116054820A
CN116054820A CN202310025229.XA CN202310025229A CN116054820A CN 116054820 A CN116054820 A CN 116054820A CN 202310025229 A CN202310025229 A CN 202310025229A CN 116054820 A CN116054820 A CN 116054820A
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China
Prior art keywords
frequency
clock
phase
output
voltage
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Pending
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CN202310025229.XA
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Chinese (zh)
Inventor
刘源
徐叔喜
张磊
汪健
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China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
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China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
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Priority to CN202310025229.XA priority Critical patent/CN116054820A/en
Publication of CN116054820A publication Critical patent/CN116054820A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention discloses a programmable phase-locked loop circuit with out-of-lock calibration, which comprises a PLL module, a control/state configuration circuit and a clock monitoring circuit, wherein: the PLL module comprises a prescaler, a phase detector, a low-pass filter, a voltage-controlled oscillator and an output clock frequency device which are sequentially connected, and further comprises a charge pump and a frequency controller, wherein the charge pump is connected between the phase detector and the voltage-controlled oscillator, the frequency controller controls the output of a frequency multiplication factor, and the voltage-controlled oscillator generates a clock frequency Fvco and feeds the clock frequency Fvco back to the phase detector through the frequency multiplication factor; the control/status configuration register locks the corresponding frequency through the register configuration PREDIV, MFD, RFD, LOCK bit operation and performs out-of-lock calibration synchronously according to the information fed back by the clock monitoring circuit. The clock monitoring circuit judges whether the clock is in an out-of-lock state by monitoring the frequencies of the input signal and the output signal, and transmits the out-of-lock state signal to the control/state configuration register.

Description

Programmable phase-locked loop circuit with out-of-lock calibration
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a programmable phase-locked loop circuit with out-of-lock calibration.
Background
A Phase-Locked Loop is a feedback control circuit, called a Phase-Locked Loop (PLL). The phase-locked loop is characterized in that: the frequency and phase of the oscillation signal inside the loop are controlled by using an externally input reference signal. When the frequency of the output signal is equal to that of the input signal, the phase difference value between the output voltage and the input voltage is kept fixed, namely the phase of the output voltage and the input voltage is locked, which is the origin of the name of the phase-locked loop. The Phase locked Loop is generally composed of five parts, i.e., a frequency reference, a Phase Detector (PD), a Charge Pump (CP), a Loop Filter (LF), and a voltage controlled oscillator (VCO, voltage Controlled Oscillator). The signal flow direction is the input signal- > phase discriminator- > low-pass filter- > voltage controlled oscillator- > output signal. The output of the phase discriminator is in direct proportion to the difference between the two input signals under the condition that the phase difference and the frequency difference are not very large, the output of the phase discriminator is an analog signal, high-frequency clutter is filtered by a low-pass filter and then enters the voltage-controlled oscillator, and the output frequency of the voltage-controlled oscillator generates corresponding frequency along with the voltage of the input signal so as to output a clock signal.
Currently, many techniques are disclosed for studying PLL phase locked loop circuits. The patent 202210905294.7 relates to a method design of many PLLs, but the prior programmable phase-locked loop circuit based on clock calibration does not relate to the method design of the PLL, such as an inverter stability optimization control method based on PLL link parameter adjustment, a PLL frequency synthesizer of 201780091028.2, a dual charge pump PLL circuit of 202210331811.4, a PLL circuit of 202080083618.2, and a control method thereof.
Disclosure of Invention
The invention aims at: a programmable phase locked loop circuit design with clock calibration is provided with a frequency controller module to configure the corresponding frequency of use. Whether the input signal is from an external clock or an internal RCOSC is selected by configuring the PLLREF bit. Meanwhile, whether the input clock and the output clock are unlocked or not is continuously monitored in the circuit through the clock calibration circuit, if the input clock and the output clock are unlocked, the clock calibration circuit generates a FAILURE signal and sends the FAILURE signal to the control/state configuration circuit to carry out unlocking calibration configuration, so that the PLL works normally, and stability is improved.
The technical scheme of the invention is as follows:
a programmable phase-locked loop circuit with out-of-lock calibration, comprising a PLL module, a control/status configuration circuit, a clock monitoring circuit, wherein: the PLL module comprises a prescaler, a phase detector, a low-pass filter, a voltage-controlled oscillator and an output clock frequency device which are sequentially connected, and further comprises a charge pump and a frequency controller, wherein the charge pump is connected between the phase detector and the voltage-controlled oscillator, the frequency controller controls the output of a frequency multiplication factor, and the voltage-controlled oscillator generates a clock frequency Fvco and feeds the clock frequency Fvco back to the phase detector through the frequency multiplication factor;
the control/status configuration register locks the corresponding frequency through the register configuration PREDIV, MFD, RFD, LOCK bit operation and performs out-of-lock calibration synchronously according to the information fed back by the clock monitoring circuit.
The clock monitoring circuit judges whether the clock is in an out-of-lock state by monitoring the frequencies of the input signal and the output signal, and transmits the out-of-lock state signal to the control/state configuration register.
Preferably, the input signal enters a prescaler to be processed and then the output frequency Spre is input into a phase discriminator to perform phase comparison operation, the detected phase difference signal is converted into an output signal Spd, then the Spd signal enters a low-pass filter to filter high-frequency clutter and generate an output signal Slp, and meanwhile the phase discriminator generates a phase difference to control a current pump to charge and discharge so as to achieve feedback control on a voltage-controlled oscillator; finally, the output signal Slp enters a voltage-controlled oscillator, the voltage-controlled oscillator generates a clock frequency Fvco, the Fvco is fed back to the phase discriminator through a frequency multiplication factor, and then the clock frequency Fvco enters an output clock frequency device to output corresponding clock frequency.
Preferably, the prescaler performs prescaler processing on the input signal to reduce in-band noise.
Preferably, the phase detector monitors the phase difference between the output frequency Spre signal and the clock frequency Fvco through the frequency multiplication factor feedback signal to generate a corresponding phase difference signal, so that the phase detector generates a corresponding frequency signal in the voltage-controlled oscillator.
Preferably, the voltage-controlled oscillator converts the input voltage signal Slp into the clock frequency Fvco with a corresponding relationship by using a tuning voltage.
Preferably, the output clock frequency divider is used to adjust the corresponding frequency output by controlling the output value of the frequency divider.
Preferably, the multiplication factor multiplies the output clock by a value N configured by the MFD, which locks the voltage controlled oscillator output frequency of the PLL module to a frequency n×refck.
Preferably, the programmable phase-locked loop circuit further comprises an RC oscillating circuit, and the RC oscillating circuit ensures that the programmable phase-locked loop circuit works normally under the condition that no external clock/crystal oscillator input exists.
The invention has the advantages that:
the PLL module of the present invention selects the corresponding clock frequency by configuring the corresponding register PREDIV, MFD, RFD, LOCK bits, thereby improving the flexibility of the PLL phase-locked loop circuit. Meanwhile, whether the output clock and the reference clock have the lock losing or failure state is monitored in real time through the clock monitoring circuit, so that corresponding reaction is made to enable the PLL to work normally, and the stability of the PLL phase-locked loop circuit is improved.
Drawings
The invention is further described below with reference to the accompanying drawings and examples:
fig. 1 is a functional block diagram of a programmable phase-locked loop circuit with out-of-lock calibration of the present invention.
Detailed Description
As shown in fig. 1, the programmable phase-locked loop circuit with out-of-lock calibration of the present invention includes a PLL module, a control/status configuration circuit, and a clock monitoring circuit, wherein: the PLL module comprises a prescaler, a phase detector, a low-pass filter, a voltage-controlled oscillator and an output clock frequency device which are sequentially connected, and further comprises a charge pump and a frequency controller, wherein the charge pump is connected between the phase detector and the voltage-controlled oscillator, the frequency controller controls the output of a frequency multiplication factor, and the voltage-controlled oscillator generates a clock frequency Fvco and feeds the clock frequency Fvco back to the phase detector through the frequency multiplication factor;
the input signal enters a prescaler to be processed and then is input into a phase discriminator to carry out phase comparison operation, the detected phase difference signal is converted into an output signal Spd, then the Spd signal enters a low-pass filter to filter high-frequency clutter to generate an output signal Slp, and meanwhile, the phase discriminator generates a phase difference to control a current pump to charge and discharge so as to realize feedback control on a voltage-controlled oscillator; finally, the output signal Slp enters a voltage-controlled oscillator, the voltage-controlled oscillator generates a clock frequency Fvco, the Fvco is fed back to the phase discriminator through a frequency multiplication factor, and then the clock frequency Fvco enters an output clock frequency device to output corresponding clock frequency.
The control/status configuration register locks the corresponding frequency through the register configuration PREDIV, MFD, RFD, LOCK bit operation and performs out-of-lock calibration synchronously according to the information fed back by the clock monitoring circuit. The clock monitoring circuit judges whether the clock is in an out-of-lock state by monitoring the frequencies of the input signal and the output signal, and transmits the out-of-lock state signal to the control/state configuration register.
The programmable phase-locked loop circuit block diagram with out-of-lock calibration shown in fig. 1:
(1) Prescaler
In the technical design of high-frequency circuits, the input signals are subjected to prescaled processing, so that in-band noise is reduced.
(2) Phase discriminator
The phase difference signal is used for monitoring the phase difference of two paths of input signals to generate a corresponding phase difference signal, so that the corresponding frequency signal is generated in the voltage-controlled oscillator.
(3) Charge pump/low pass filter
The low-pass filter filters high-frequency clutter, and the current pump controls the charge and discharge of the current pump because the phase detector generates a phase difference so as to achieve feedback control on the VCO.
(4) Voltage controlled oscillator
The voltage-controlled oscillator is used for converting the voltage signal of the phase detector into output frequencies with corresponding relations.
(5) Output clock frequency device (RFD)
The output value of the frequency divider is controlled to adjust the corresponding frequency output.
(6) Frequency Multiplication Factor (MFD)
The MFD locks the VCO output frequency of the PLL to the frequency of N x refck by multiplying the output clock by the N value configured by the MFD.
(7) Frequency controller
For controlling the frequency output for a frequency Multiplication Factor (MFD).
(8) Control/status configuration registers
The corresponding frequency is locked through the register configuration PREDIV, MFD, RFD, LOCK bit operation, and the out-of-lock calibration is synchronously performed according to the information fed back by the out-of-lock calibration circuit.
(9) Clock monitoring circuit
The clock is judged whether to be in an out-of-lock state by monitoring the frequencies of the input signal and the output signal, and the out-of-lock state signal is transmitted to the control/state configuration register.
(10) RC oscillating circuit (RCOSC)
Under the condition of no external clock/crystal oscillator input, the on-chip integrated RC oscillating circuit ensures that the chip can work normally.
The corresponding clock frequency is selected by configuring the corresponding register PREDIV, MFD, RFD, LOCK bits in the PLL circuit module, so that the flexibility of the PLL phase-locked loop circuit is improved. Meanwhile, whether the output clock and the reference clock have the lock losing or failure state is monitored in real time through the clock monitoring circuit, so that corresponding reaction is made to enable the PLL to work normally, and the stability of the PLL phase-locked loop circuit is improved.
The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement the same according to the content of the present invention, and are not intended to limit the scope of the present invention. All modifications made according to the spirit of the main technical proposal of the invention should be covered in the protection scope of the invention.

Claims (9)

1. A programmable phase-locked loop circuit with out-of-lock calibration, comprising a PLL module, a control/status configuration circuit, a clock monitoring circuit, wherein: the PLL module comprises a prescaler, a phase detector, a low-pass filter, a voltage-controlled oscillator and an output clock frequency device which are sequentially connected, and further comprises a charge pump and a frequency controller, wherein the charge pump is connected between the phase detector and the voltage-controlled oscillator, the frequency controller controls the output of a frequency multiplication factor, and the voltage-controlled oscillator generates a clock frequency Fvco and feeds the clock frequency Fvco back to the phase detector through the frequency multiplication factor;
the control/status configuration register locks the corresponding frequency through the register configuration PREDIV, MFD, RFD, LOCK bit operation and performs out-of-lock calibration synchronously according to the information fed back by the clock monitoring circuit.
2. The clock monitoring circuit judges whether the clock is in an out-of-lock state by monitoring the frequencies of the input signal and the output signal, and transmits the out-of-lock state signal to the control/state configuration register.
3. The programmable phase-locked loop circuit with out-of-lock calibration according to claim 1, wherein the input signal is processed by a prescaler, the output frequency Spre is input into a phase discriminator for phase comparison operation, the detected phase difference signal is converted into an output signal Spd, then the Spd signal is input into a low-pass filter for filtering high-frequency clutter to generate an output signal Slp, and the phase discriminator generates a phase difference to control the charge and discharge of a current pump so as to realize feedback control of a voltage-controlled oscillator; finally, the output signal Slp enters a voltage-controlled oscillator, the voltage-controlled oscillator generates a clock frequency Fvco, the Fvco is fed back to the phase discriminator through a frequency multiplication factor, and then the clock frequency Fvco enters an output clock frequency device to output corresponding clock frequency.
4. A programmable phase-locked loop circuit with out-of-lock calibration as claimed in claim 3, wherein said prescaler prescales the input signal to reduce in-band noise.
5. The programmable phase-locked loop circuit with out-of-lock calibration of claim 4, wherein the phase detector monitors the phase difference between the output frequency Spre signal and the clock frequency Fvco to generate a corresponding phase difference signal by multiplying the phase difference of the factor feedback signal to generate a corresponding frequency signal in the voltage-controlled oscillator.
6. The programmable phase-locked loop circuit with out-of-lock calibration of claim 5, wherein the voltage controlled oscillator converts the input voltage signal Slp to a corresponding clock frequency Fvco using a tuning voltage.
7. A programmable phase locked loop circuit with out-of-lock calibration as claimed in claim 6, wherein said output clock frequency divider is operable to adjust the corresponding frequency output by controlling the output value of the frequency divider.
8. The programmable phase-locked loop circuit with out-of-lock calibration of claim 7, wherein the multiplication factor multiplies the N value configured by the MFD by the output clock, the MFD locking the voltage-controlled oscillator output frequency of the PLL module to a frequency of N x refck.
9. The programmable phase-locked loop circuit with out-of-lock calibration of claim 8, further comprising an RC oscillating circuit that ensures proper operation of the programmable phase-locked loop circuit without an external clock/crystal oscillator input.
CN202310025229.XA 2023-01-09 2023-01-09 Programmable phase-locked loop circuit with out-of-lock calibration Pending CN116054820A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117353765A (en) * 2023-12-06 2024-01-05 杭州长川科技股份有限公司 Signal transmitting device, tester and signal output method of tester
CN117375642A (en) * 2023-12-06 2024-01-09 杭州长川科技股份有限公司 Signal transmitting device, tester and signal output method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117353765A (en) * 2023-12-06 2024-01-05 杭州长川科技股份有限公司 Signal transmitting device, tester and signal output method of tester
CN117375642A (en) * 2023-12-06 2024-01-09 杭州长川科技股份有限公司 Signal transmitting device, tester and signal output method thereof
CN117353765B (en) * 2023-12-06 2024-04-02 杭州长川科技股份有限公司 Signal transmitting device, tester and signal output method of tester
CN117375642B (en) * 2023-12-06 2024-04-02 杭州长川科技股份有限公司 Signal transmitting device, tester and signal output method thereof

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