CN116053325A - High-resistance field plate shielding gate groove type field effect transistor device and manufacturing method - Google Patents

High-resistance field plate shielding gate groove type field effect transistor device and manufacturing method Download PDF

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CN116053325A
CN116053325A CN202310190056.7A CN202310190056A CN116053325A CN 116053325 A CN116053325 A CN 116053325A CN 202310190056 A CN202310190056 A CN 202310190056A CN 116053325 A CN116053325 A CN 116053325A
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field plate
groove
forming
gate electrode
oxide layer
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伍震威
梁嘉进
单建安
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Anjian Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

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Abstract

The invention relates to a high-resistance field plate shielding gate groove type field effect transistor device and a manufacturing method, belonging to a power semiconductor device, comprising: a drain metal layer at the bottom; an n+ substrate layer over the drain metal layer; an N-type epitaxial layer over the n+ substrate layer; the P doped body region and the N+ doped source region are positioned on the upper surface of the device; the N+ doped source region is connected with source metal positioned on the upper surface of the device; the N-type epitaxial layer is provided with a groove, a shielding gate electrode and gate electrodes positioned on the left side and the right side of the shielding gate electrode or on one side of the shielding gate electrode are filled in the groove, the shielding gate electrode is connected with upper surface metal positioned at the top of the device, a high-resistance field plate is arranged below the shielding gate electrode, the lower part of the high-resistance field plate extends into the N+ substrate layer, and a thin oxide layer is arranged between the high-resistance field plate and the side wall of the groove for isolation. The high-resistance field plate has the beneficial effects that the electric field intensity in the deep part of the groove is reduced, uniform electric field intensity distribution is realized, and the breakdown voltage is increased.

Description

High-resistance field plate shielding gate groove type field effect transistor device and manufacturing method
Technical Field
The invention belongs to a power semiconductor device, and particularly relates to a high-resistance field plate shielding gate trench type field effect transistor device and a manufacturing method thereof.
Background
The related art background of the conventional shielded gate trench type field effect transistor will be described below. It is noted that corresponding positional words such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "vertical" as described in this document are relative positions corresponding to the reference drawings. The fixing direction is not limited in the specific implementation. It should be noted that the devices in the drawings are not necessarily drawn to scale. The straight lines shown in the boundaries of the doped regions and trenches in the drawings, and the sharp corners formed by the boundaries, are generally not straight lines and precise angles in practical applications.
The shielded gate trench type field effect transistor has the characteristics of low on-resistance and high switching speed. Fig. 1 is a schematic cross-sectional view of an N-type shielded gate trench fet of conventional structure. The device structure comprises: a drain metal layer (113) at the bottom; an n+ substrate layer (100) over the drain metal layer; an N-type epitaxial layer (101) over the n+ substrate layer; and a P doped body region (108) and an N+ doped source region (107) located on the upper surface of the device; a series of grooves are formed on the N-type epitaxial layer, and three electrodes, namely a gate electrode (106) positioned on the left side and the right side and a shielding gate electrode (105) positioned in the middle, are filled in the grooves. Wherein, the gate electrode (106) is isolated from the corresponding side wall of the groove through the gate oxide layer (103); the shielding gate electrode (105) is isolated from the corresponding side wall of the groove through the groove oxide layer (102); the gate electrode (106) and the shield gate electrode (105) are isolated by an inter-electrode isolation oxide layer (104). Meanwhile, the N+ doped source region (107) is connected with the source metal (110) positioned on the upper surface of the device through a through hole on the oxide dielectric layer (114); the shielding gate electrode (105) is connected with the source metal (111) positioned on the upper surface of the device through a through hole on the oxide dielectric layer (114); the gate electrode (106) is connected to a gate metal (112) on the upper surface of the device through a via in an oxide dielectric layer (114).
With the increase of breakdown voltage, the depth of the trench and the thickness of the trench oxide layer (102) need to be adjusted correspondingly to achieve charge balance. For devices above 100V, a thickness of 5000A or more is often required for the trench oxide layer (102). However, increasing the thickness of the oxide layer filling the thick trench increases the width of the trench, thereby reducing the silicon area when the device is turned on and increasing the on-resistance of the device.
In addition, when the shielding gate trench type field effect transistor device is reversely biased, higher electric fields are formed at the bottom of the trench and in the area below the P doped body region (108) respectively, so that the breakdown voltage of the device is limited to be further improved.
In addition, in the shielded gate trench type field effect transistor structure, the shielded gate electrode (105) is connected with the source electrode, and when the device is reversely biased, the potential of the shielded gate electrode in the trench is equal to the potential of the source electrode. Therefore, there is a relatively high potential difference in the horizontal direction at the semiconductor drift region near the bottom of the shield gate electrode. Therefore, when avalanche breakdown occurs in the device, high-energy electron flow is easy to sink in the trench oxide layer in the horizontal direction, so that the electric field intensity near the trench is reduced, instability of breakdown voltage is generated, and even UIS performance of the device is affected.
Finally, in high frequency applications, the parasitic capacitance between the shield gate electrode and the drift region is large, so that a large source-drain capacitance is generated, and a large overshoot current is easily generated in the switching process, which is detrimental to the reliability of the circuit system.
Disclosure of Invention
In order to solve the problems, the invention provides a high-resistance field plate shielding gate groove type field effect transistor device with lower resistance, higher breakdown voltage and improved switching performance compared with the prior shielding gate groove type field effect transistor device and a manufacturing method thereof.
The invention adopts the following technical scheme:
a high resistance field plate shielded gate trench field effect transistor device comprising: a drain metal layer at the bottom; an n+ substrate layer over the drain metal layer; an N-type epitaxial layer over the n+ substrate layer; the P doped body region and the N+ doped source region are positioned on the upper surface of the device; the N+ doped source region is connected with source metal positioned on the upper surface of the device;
the N-type epitaxial layer is provided with a groove, a shielding gate electrode and gate electrodes positioned on the left side and the right side of the shielding gate electrode or on one side of the shielding gate electrode are filled in the groove, the shielding gate electrode is connected with upper surface metal positioned at the top of the device, a high-resistance field plate is arranged below the shielding gate electrode, the lower part of the high-resistance field plate extends into the N+ substrate layer, and a thin oxide layer is arranged between the high-resistance field plate and the side wall of the groove for isolation.
Optionally, the high-resistance field plate is composed of materials with resistivity changing from top to bottom or is composed of multiple layers of materials with different resistivity.
Alternatively, the high resistance field plate is composed of a material of varying resistivity and is minimally divided into upper and lower portions, wherein the upper resistivity is lower than the lower resistivity, and the boundary between the upper and lower portions is located 0.1-0.5. 0.5um below the adjacent gate electrodes.
Optionally, the high-resistance field plate is made of materials with variable resistivity and is divided into an upper part and a lower part at least, wherein the upper part has lower resistivity than the lower part, and the boundary of the upper part and the lower part is positioned above the boundary of the adjacent N-type epitaxial layer and the N+ substrate layer.
Optionally, the high-resistance field plate is a thin conductive layer covered on the thin oxide layer, and a filling material is filled in a groove formed by the thin conductive layer.
Optionally, the groove is divided into an upper portion and a lower portion, wherein the width of the upper groove is greater than the width of the lower groove.
Optionally, a P-type injection region is arranged at the bottom of the high-resistance field plate in the N-type epitaxial layer.
Optionally, a P-type charge storage layer is provided between the thin oxide layer and the trench.
Optionally, a P-type island region is formed in the N-type epitaxial layer below the P-doped body region.
A manufacturing method of a high-resistance field plate shielding gate groove type field effect transistor device comprises the following steps:
s1, forming a groove on a semiconductor, forming a thin oxide layer in the groove, and then removing the thin oxide layer at the bottom of the groove;
s2, filling a high-resistance field plate material in the groove, and refilling a shielding gate electrode material;
s3, etching back the thin oxide layer;
s4, forming a gate oxide layer and a shielding gate oxide layer;
s5, forming a gate electrode, then forming upper surface metal, a contact hole and finally forming the device.
A manufacturing method of a high-resistance field plate shielding gate groove type field effect transistor device comprises the following steps:
s1, forming a groove on a semiconductor, forming a thin oxide layer in the groove, and then removing the thin oxide layer at the bottom of the groove;
s2, forming a thin conductive layer covering the thin oxide layer in the groove, and refilling filling materials;
s3, etching back the thin oxide layer;
s4, forming a gate oxide layer and a shielding gate oxide layer;
s5, forming a gate electrode, then forming upper surface metal, a contact hole and finally forming the device.
A manufacturing method of a high-resistance field plate shielding gate groove type field effect transistor device comprises the following steps:
s1, forming a groove on a semiconductor, forming a thin oxide layer in the groove, and then removing the thin oxide layer at the bottom of the groove;
s2, filling high-resistance field plate materials in the grooves to form a narrow groove high-resistance field plate structure,
s3, etching a wide groove above the semiconductor, etching a thin oxide layer, and refilling a shielding gate electrode material;
s4, forming a gate oxide layer and a shielding gate oxide layer;
s5, forming a gate electrode, then forming upper surface metal, a contact hole and finally forming the device.
A manufacturing method of a high-resistance field plate shielding gate groove type field effect transistor device comprises the following steps:
s1, forming a wide groove on a semiconductor, and forming a gate oxide layer and a gate electrode;
s2, etching the middle part of the gate electrode and the semiconductor below the gate electrode to form a narrow groove, wherein the gate electrode part pole is remained in the wide groove;
s3, filling high-resistance field plate materials in the grooves to form high-resistance field plate structures;
s4, performing thermal oxidation, forming a shielding gate oxide layer on the gate electrode, and refilling shielding gate electrode materials;
s5, forming upper surface metal, contact holes and finally forming the device.
The novel groove type field effect transistor device structure with the high-resistance field plate has the advantages that the high-resistance field plate is utilized to reduce the electric field intensity in the depth of the groove, so that uniform electric field intensity distribution is realized, and breakdown voltage is increased. In the device, the breakdown voltage is irrelevant to the thickness of the oxide layer of the groove, so that the width of the groove is narrower, the conducting area of the device is larger, and the on-resistance is lower. Meanwhile, the high-resistance field plate provides a current path for the vertical direction of the device, so that the influence caused by high-energy electron collapse is avoided. In addition, the high-resistance field plate between the source electrode and the drain electrode in the device can be used as a buffer, and can improve the overshoot current during switching and reverse recovery of the device.
Drawings
FIG. 1 is a schematic cross-sectional view of a prior art shielded gate trench field effect transistor device;
FIG. 2 is a schematic cross-sectional view of a first embodiment of a shielded gate trench field effect transistor device of the present invention;
FIG. 3 is a graph showing the distribution of electric field strength with depth for a conventional shielded gate trench FET device and the device of the present invention during reverse bias;
FIGS. 4A-4C are schematic cross-sectional views illustrating a portion of steps of the manufacturing method of the first embodiment of FIG. 2;
FIG. 5 is a schematic cross-sectional view of a second embodiment of a shielded gate trench FET of the present invention;
FIGS. 6A-6B are schematic cross-sectional views of partial steps of the manufacturing process of the second embodiment of FIG. 5;
fig. 7 is a schematic cross-sectional view of a third embodiment of a shielded gate trench field effect transistor of the present invention;
fig. 8 is a schematic cross-sectional view of a fourth embodiment of a shielded gate trench field effect transistor of the present invention;
fig. 9 is a schematic cross-sectional view of a fifth embodiment of a shielded gate trench field effect transistor of the present invention;
fig. 10 is a schematic cross-sectional view of a sixth embodiment of a shielded gate trench field effect transistor of the present invention;
fig. 11 is a schematic cross-sectional view of a seventh and eighth embodiment of a shielded gate trench field effect transistor of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Note that, in the following description of the shielded gate trench type field effect transistor device and the method of manufacturing the same of the present invention, a semiconductor substrate of the shielded gate trench type field effect transistor device is considered to be composed of a silicon (Si) material. However, the substrate may be formed of any other material suitable for manufacturing a shielded gate trench field effect transistor, such as gallium nitride (GaN), silicon carbide (SiC), and the like. In the following description, the conductivity type of the semiconductor region is classified into P-type (second conductivity type) and N-type (first conductivity type), and one P-type conductivity type semiconductor region may be formed by doping one or several impurities into the original semiconductor region, which may be, but are not limited to: boron (B), aluminum (Al), gallium (Ga), and the like. An N-type conductive semiconductor region may also be formed by doping the original semiconductor region with one or more impurities, such as, but not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (h+), and the like. In the following description, a heavily doped P-type conductive semiconductor region is denoted as a p+ region, and a heavily doped N-type conductive semiconductor region is denoted as an n+ region. For example, in a silicon material substrate, the impurity concentration of a heavily doped region is typically 1X 10 19 cm-3 to 1X 10 21 cm-3. Those skilled in the art will appreciate that the present inventionThe P-type (second conductivity type) and N-type (first conductivity type) may be interchanged.
Embodiment one:
as shown in fig. 2, the present embodiment provides a high-resistance field plate shielding gate trench type field effect transistor device, including: a drain metal layer 213 located at the bottom; an n+ substrate layer 201 over the drain metal layer 213; an N-type epitaxial layer 202 over the n+ substrate layer; the P doped body region and the N+ doped source region are positioned on the upper surface of the device; the n+ doped source region is connected to source metal 210 on the upper surface of the device; the N-type epitaxial layer 202 is provided with a trench 200, the trench 200 is filled with a shielding gate electrode 205 and gate electrodes 206 located at the left side and the right side of the shielding gate electrode 205 or at one side of the shielding gate electrode, the shielding gate electrode 205 is connected with an upper surface metal 211 located at the top of the device, a high-resistance field plate 220 is arranged below the shielding gate electrode 205, the lower part of the high-resistance field plate 220 extends into the n+ substrate layer 201, and a thin oxide layer 221 is arranged between the high-resistance field plate 220 and the side wall of the trench 200 for isolation.
Wherein the gate electrode 206 is isolated from the sidewalls of the trench 200 by a gate oxide layer. The gate electrode 206 and the shield gate electrode 205 are isolated by an inter-electrode isolation oxide layer.
Wherein the gate electrode 206 is typically comprised of polysilicon. The shield gate electrode 205 may be composed of polysilicon or amorphous silicon, or may be composed of a metal, a metal compound such as Ti, tiN, W, pt, or the like.
The high-resistance field plate 220 may be composed of high-resistance polysilicon SIPOS, amorphous silicon, silicon oxynitride, a metal compound such as TiN, siTi, etc., or an organic compound, etc. In order to limit the leakage current between the source and the drain and to consider the RC delay of the high-resistance field plate, the resistivity of the high-resistance field plate 220 from the upper end to the lower end needs to be reasonably selected according to practical applications. Generally, a narrower trench 200 is advantageous for forming a high resistance field plate 220 having a larger resistance value. For example, in an active area of 10mm 2 In an embodiment of the 100V device, the high resistance field plate has a width of between 0.05-0.5um and a resistivity of between 1e-4 Ohm-m and 1e-7 Ohm-m.
Wherein the depth of the high resistance field plate 220 is dependent on the withstand voltage of the device, for example in a 100V device embodiment, the selectable depth of the high resistance field plate is between 4-8 um; in a 200V device embodiment, the selectable depth of the high resistance field plate is between 6-14 um.
Wherein the thin oxide layer 221 between the high resistance field plate 220 and the sidewalls of the semiconductor trench 200, has a thickness of between 0.05 and 0.4 um.
As shown in fig. 3, the distribution of the electric field intensity with depth of the conventional shielded gate trench type field effect transistor device and the above device at the time of reverse bias are compared. Wherein the upper diagram is a conventional device and the lower diagram is a device of the present invention. When the traditional device is reversely biased, areas with higher electric field intensity are respectively formed at the bottom of the groove 200 and below the P doped body area, so that the breakdown voltage of the device is limited. Compared with the traditional shielded gate trench type field effect transistor device, when the device is reversely biased, linear potential difference can be formed in the high-resistance field plate, and even electric field distribution is formed on the semiconductor between the P doped body region and the bottom of the trench 200 through electric coupling, so that higher breakdown voltage is realized.
Alternatively, the high-resistance field plate 220 is made of materials with resistivity varying from top to bottom or multiple layers of materials with different resistivity to provide the coupling electric field distribution required by the design, where the high-resistance field plate 220 is from top to bottom near the top of the device to bottom near the bottom of the device on the high-resistance field plate 220. For example, to avoid too high an electric field at the corners below the gate electrode 206 during reverse bias, the high resistance field plate 220 may be formed of a combination of materials with a lower low resistivity above and a higher resistivity below, such that a relatively high upper and lower electric field distribution is exhibited in the semiconductor. Thereby reducing the electric field intensity at the corners of the gate electrode 206 near the lower portion of the P-doped body region, and achieving the purpose of protecting the corners of the gate electrode 206. For another example, the N-type epitaxial layer 202 with a variable concentration may be used in the device, or the impurity diffusion of the n+ substrate layer 201 causes the concentration under the N-type epitaxial layer 202 to be increased, and the high-resistance field plate may correspondingly use a higher resistivity at the high concentration of the N-type epitaxial layer 202, so as to realize overall charge balance, so as to improve the breakdown voltage and UIS performance.
In an alternative embodiment, the high resistance field plate 220 is composed of a material of varying resistivity and is minimally divided into upper and lower portions, wherein the upper resistivity is lower than the lower resistivity and the boundary between the upper and lower portions is 0.1-0.5 um below the adjacent gate electrode 206.
In an alternative embodiment, the high resistance field plate 220 is composed of a material with varying resistivity and is minimally divided into upper and lower portions, wherein the upper resistivity is lower than the lower resistivity, and the boundary between the upper and lower portions is located above the boundary between the adjacent N-type epitaxial layer 202 and the n+ substrate layer 201.
The breakdown voltage of the device of the present invention is independent of the thickness of thin oxide layer 221, and thus the width of trench 200 can be narrower and the cell size denser than conventional devices. In a 100V device embodiment, the conventional device trench 200 has a width between 1.5um and 3um and a cell size between 2 um and 4 um; the width of the device trench 200 of the present invention can be 1um-3 um. Therefore, the device has larger conduction area, larger channel density and lower conduction resistance.
Meanwhile, compared with the traditional structure, the device has the advantages that the potential difference in the horizontal direction of the semiconductor near the groove 200 is smaller in the reverse bias process, the electric field is lower, and the high-resistance field plate provides a current path for the device in the vertical direction, so that the problem of unstable breakdown voltage caused by high-energy electrons falling into the groove 200 in the avalanche breakdown process can be avoided.
In addition, the high-resistance field plate in the device is used as a buffer (Snubber), so that the overshoot current during switching and reverse recovery of the device can be improved.
In the structure shown in fig. 2, the shield gate electrode 205 serves to electrically connect the upper surface metal 211 to the high resistance field plate 220 while facilitating the formation of a thicker inter-electrode isolation oxide to reduce the capacitance between the source and gate. In some embodiments, such as where an oxidizable material is used as the high resistance field plate material, it is possible to directly connect the high resistance field plate 220 to the upper surface metal 211, omitting the shielded gate electrode 205 structure.
In addition, the upper surface metal 211 is typically connected to the source. However, the upper surface metal 211 functions to provide a potential lower than that of the drain electrode to the high resistance field plate upon reverse bias to form a current path, so that the upper surface metal may be connected to other potential than the drain electrode. In some embodiments, the upper surface metal 211 may be connected to additional electrodes outside the source, drain, gate. The potential of the additional electrode may be provided by an external circuit. In one embodiment, the field effect transistor device has additional electrodes outside the source, drain, gate, which are connected to the high resistance field plate 230, and part of the upper surface metal 211.
As shown in fig. 4A to 4C, a possible manufacturing method of the high-resistance field plate shielding gate trench type field effect transistor device of the first adaptive embodiment in fig. 2 is shown, and the steps include:
s1, forming a trench 200 on the semiconductor, forming a thin oxide layer 221 in the trench 200, and then removing the thin oxide layer 221 at the bottom of the trench 200. The method of removing the thin oxide layer 221 at the bottom of the trench 200 may be dry etching;
s2, filling the high-resistance field plate material in the groove 200, and refilling the shielding gate electrode material 205. As shown in fig. 4A. Wherein the high resistance field plate material may be formed by a Chemical Vapor Deposition (CVD) method. In one embodiment, the resistivity of the high resistance field plate material varies with the depth of the trench 200, wherein the high resistance field plate resistivity is adjusted by variations in parameters during the CVD process;
s3, etching back the thin oxide layer 221, as shown in FIG. 4B;
s4, forming a gate oxide layer and a shielding gate oxide layer 222, as shown in fig. 4C. The shield gate oxide 222 and the gate oxide may be formed simultaneously by thermal oxidation. The thickness of the shield gate oxide 222 is typically thicker than the gate oxide. Prior to thermal oxidation, the shield gate electrode material 205 may include amorphous silicon or amorphous silicided polysilicon to increase the oxidation rate of the shield gate electrode material to the effect of forming a thicker shield gate oxide layer 222. In one embodiment, the shield gate electrode material 205 is polysilicon, and after filling the shield gate electrode material 205, ion implantation is performed on the polysilicon to increase the oxidation rate of the shield gate electrode material;
s5, forming a gate electrode 206, then forming upper surface metal, a contact hole and finally forming a device; the gate electrode 206 material may be polysilicon or metal to further reduce gate resistance.
Embodiment two:
in addition to the above proposed structure, the high resistance field plate 220 of the present invention may be changed more. To further reduce the resistivity of the high resistance field plate 220 and improve process uniformity, a device structure is shown in fig. 5. Wherein the high resistance field plate 220 is a thin conductive layer overlying a thin oxide layer 221. The trench 200 formed of the thin conductive layer is filled with a filling material 230.
In this structure, the resistivity of the high-resistance field plate 220 can be adjusted by controlling the thickness of the thin conductive layer, which is easy to achieve higher resistivity and better process uniformity.
As shown in fig. 6A to 6B, a feasible manufacturing method of the high-resistance field plate shielding gate trench type field effect transistor device of the second embodiment includes the steps of:
s1, forming a trench 200 on the semiconductor, forming a thin oxide layer 221 in the trench 200, and then removing the thin oxide layer 221 at the bottom of the trench 200. The method of removing the thin oxide layer 221 at the bottom of the trench 200 may be dry etching;
s2, a thin conductive layer 220 covering the thin oxide layer 221 is formed in the trench 200, and then the filling material 230 is refilled. The thin conductive layer 220 may comprise a metal compound such as indium, titanium, nickel, tin, etc., or a metal oxide or nitride such as titanium nitride, indium oxide, etc., and may be formed by CVD or vapor deposition to a thickness of between 50A and 500A. The filler material may be an insulating material such as silicon oxide, a polymer, etc., or may be a conductive material having a resistivity higher than that of the thin conductive layer. In addition, after forming the thin conductive layer 220 and the filling material 230, a plurality of back etching steps may be performed to adjust the high resistance field plate 220 to a desired height;
s3, etching back the thin oxide layer 221, as shown in FIG. 4B;
s4, forming a gate oxide layer and a shielding gate oxide layer 222, as shown in fig. 4C. The shield gate oxide 222 and the gate oxide may be formed simultaneously by thermal oxidation. The thickness of the shield gate oxide 222 is typically thicker than the gate oxide. Prior to thermal oxidation, the shield gate electrode material 205 may include amorphous silicon or amorphous silicided polysilicon to increase the oxidation rate of the shield gate electrode material to the effect of forming a thicker shield gate oxide layer 222. In one embodiment, the shield gate electrode material 205 is polysilicon, and after filling the shield gate electrode material 205, ion implantation is performed on the polysilicon to increase the oxidation rate of the shield gate electrode material;
and S5, forming a gate electrode 206, then forming an upper surface metal, a contact hole and finally forming the device. The gate electrode 206 material may be polysilicon or metal to further reduce gate resistance.
In the above-described structure, the width of the gate electrode 206 may be limited by the thickness of the thin oxide layer 221 in the trench 200. In practice, the structure of the gate electrode 206 may vary according to the requirements, as in the embodiments shown in fig. 7 and 8.
Embodiment III:
fig. 7 shows another variant embodiment of the invention. In contrast to the previous embodiments, the trench 200 is divided into upper and lower portions in the structure, wherein the width of the upper trench is greater than the width of the lower trench. The width of the gate electrode 206 may not be limited to the thickness of the thin oxide layer 221, and may be wider than the thin oxide layer. The structure is favorable for reducing the grid resistance and accelerating the switching speed of the device.
Embodiment four:
another alternate embodiment of the device structure of fig. 7 is shown in fig. 8, which employs a single sided gate electrode structure, with the gate electrode on one side of the trench 200. In this structure, the thin oxide layers 221 on the left and right sides of the cell may have different thicknesses according to a specific process. The structure is not limited by the etching process of the contact hole, so that the denser cell density is realized, and the resistance of the offset region is further reduced.
The method of forming the special trench 200 structure described above may include a minimum of two steps, followed by forming the upper wider trench 200 and the lower narrower trench 200. For example, the narrower trench 200 is etched first to form a high resistance field plate structure, and then the upper wider trench 200 is etched to form a gate structure. For another example, the upper wider trench 200 is etched first and after the gate structure is completed, the lower narrower trench 200 is etched to form a high resistance field plate structure.
A feasible manufacturing method of the high-resistance field plate shielding gate trench type field effect transistor device suitable for the third and fourth embodiments comprises the following steps:
s1, forming a trench 200 on the semiconductor, forming a thin oxide layer 221 in the trench 200, and then removing the thin oxide layer 221 at the bottom of the trench 200.
S2, filling the high-resistance field plate material in the groove 200 to form a narrow-groove high-resistance field plate structure,
s3, etching a wide groove above the semiconductor, etching the thin oxide layer 221 back, and refilling the shielding gate electrode material 205.
S4, forming a gate oxide layer and shielding the gate oxide layer 222.
And S5, forming a gate electrode 206, then forming an upper surface metal, a contact hole and finally forming the device.
In addition, another feasible manufacturing method of the high-resistance field plate shielding gate trench type field effect transistor device suitable for the third and fourth embodiments is provided, and the steps include:
s1, forming a wide groove on a semiconductor, and forming a gate oxide layer and a gate electrode;
s2, etching the middle part of the gate electrode and the semiconductor below the gate electrode to form a narrow groove, wherein the gate electrode part pole remains in the wide groove 200;
and S3, filling the high-resistance field plate material in the groove 200 to form a high-resistance field plate structure.
S4, performing thermal oxidation, forming a shielding gate oxide layer on the gate electrode, and refilling shielding gate electrode materials.
S5, forming upper surface metal, contact holes and finally forming the device.
In the above embodiments, the bottom of the high resistance field plate is typically connected to the n+ substrate layer 201, but may in fact be connected to the N-type epitaxial layer 202, depending on the extent and depth of the electric field coupling of the device to the high resistance field plate.
Fifth embodiment:
typically, the bottom of the high resistance field plate may be connected to a semiconductor region of higher doping concentration to form an ohmic contact. In some embodiments, the ohmic contact region 301 may be formed by performing ion implantation with low energy and high doping concentration at the bottom of the trench 200 in advance, as shown in fig. 9.
Example six:
fig. 10 shows another variant embodiment of the invention. In this structure, a P-type implantation region 302 is disposed in the N-type epitaxial layer 202 at the bottom of the high-resistance field plate. The method for forming the P-type implantation region may be as follows: after the formation of the trench 200, a multi-step vertical ion implantation of different implantation energies is performed before the high resistance field plate material is filled. The P-type injection region can form a depletion region when the device is reversely biased so as to increase the reverse bias withstand voltage of the device, reduce the leakage current of the high-resistance field plate in the switching transient state of the device and accelerate the transient response speed of the high-resistance field plate.
Embodiment seven:
in addition, in order to further increase the breakdown voltage of the device while reducing the delay effect of the high-resistance field plate, a charge storage layer may be further added near the high-resistance field plate. In the alternative embodiment shown in fig. 11, a P-type charge storage layer 303 is provided between the thin oxide layer 221 and the trench 200. During reverse bias, a depletion region can be formed in the P-type charge storage layer rapidly, so that the response speed of the field plate is increased. The P-type charge storage layer may be formed by ion diffusion or inclined ion implantation after forming the trench 200.
Example eight:
as shown in fig. 11, in the present embodiment, a P-type island region 304 is formed in the N-type epitaxial layer 202 below the P-doped body region. The P-type island region can further reduce the input capacitance of the device and improve the switching performance of the device. The method for forming the P-type island region may be: after contact hole etching, high-energy ion implantation is performed, and the implantation energy is between 200keV and 1 MKEV.
The above-described embodiments of the invention, in which the structural features mentioned, may be combined with one another to form further embodiment device structures.
The novel groove type field effect transistor device structure with the high-resistance field plate has the advantages that the high-resistance field plate is utilized to reduce the electric field intensity in the depth of the groove, so that uniform electric field intensity distribution is realized, and breakdown voltage is increased. In the device, the breakdown voltage is irrelevant to the thickness of the oxide layer of the groove, so that the width of the groove is narrower, the conducting area of the device is larger, and the on-resistance is lower. Meanwhile, the high-resistance field plate provides a current path for the vertical direction of the device, so that the influence caused by high-energy electron collapse is avoided. In addition, the high-resistance field plate between the source electrode and the drain electrode in the device can be used as a buffer, and can improve the overshoot current during switching and reverse recovery of the device.

Claims (13)

1. A high resistance field plate shielded gate trench fet device comprising: a drain metal layer (213) located at the bottom; an n+ substrate layer (201) located over the drain metal layer (213); an N-type epitaxial layer (202) over the n+ substrate layer; the P doped body region and the N+ doped source region are positioned on the upper surface of the device; the N+ doped source region is connected with source metal (210) positioned on the upper surface of the device;
the N-type epitaxial layer (202) is provided with a groove (200), the groove (200) is internally filled with a shielding gate electrode (205) and gate electrodes (206) which are arranged on the left side and the right side of the shielding gate electrode (205) or on one side of the shielding gate electrode, the shielding gate electrode (205) is connected with upper surface metal (211) which is arranged on the top of the device, a high-resistance field plate (220) is arranged below the shielding gate electrode (205), the lower side of the high-resistance field plate (220) extends into an N+ substrate layer (201), and a thin oxide layer (221) is arranged between the high-resistance field plate (220) and the side wall of the groove (200) for isolation.
2. The high resistance field plate shielded gate trench fet device of claim 1, wherein the high resistance field plate (220) is composed of a material with varying resistivity from top to bottom or of multiple layers of materials with different resistivity.
3. The high resistance field plate shielded gate trench fet device of claim 1 wherein the high resistance field plate (220) is comprised of a material of varying resistivity and is minimally divided into upper and lower portions, wherein the upper resistivity is lower than the lower resistivity and the upper and lower portions are separated by a boundary between 0.1-0.5 and um below adjacent gate electrodes (206).
4. The high resistance field plate shielded gate trench type field effect transistor device of claim 1, wherein the high resistance field plate (220) is comprised of a material of varying resistivity and is minimally divided into an upper portion and a lower portion, wherein the upper portion has a lower resistivity and the lower portion has a boundary between the upper portion and the lower portion above the boundary between the adjacent N-type epitaxial layer (202) and the n+ substrate layer (201).
5. The high resistance field plate shielded gate trench type field effect transistor device of claim 1, wherein the high resistance field plate (220) is a thin conductive layer overlying a thin oxide layer (221), and the trench (200) formed by the thin conductive layer is filled with a filler material (230).
6. The high resistance field plate shielded gate trench fet device of claim 1, wherein the trench (200) is divided into upper and lower portions, wherein the width of the upper trench is greater than the width of the lower trench.
7. The high resistance field plate shielded gate trench type field effect transistor device of claim 1, wherein a P-type implantation region (302) is provided in the N-type epitaxial layer (202) at the bottom of the high resistance field plate.
8. The high resistance field plate shielded gate trench field effect transistor device of claim 1, wherein a P-type charge storage layer (303) is provided between the thin oxide layer (221) and the trench (200).
9. The high resistance field plate shielded gate trench fet device of claim 1, wherein a P-type island region (304) is formed in the N-type epitaxial layer (202) below the P-doped body region.
10. The manufacturing method of the high-resistance field plate shielding gate groove type field effect transistor device is characterized by comprising the following steps:
s1, forming a groove on a semiconductor, forming a thin oxide layer in the groove, and then removing the thin oxide layer at the bottom of the groove;
s2, filling a high-resistance field plate material in the groove, and refilling a shielding gate electrode material;
s3, etching back the thin oxide layer;
s4, forming a gate oxide layer and a shielding gate oxide layer;
s5, forming a gate electrode, then forming upper surface metal, a contact hole and finally forming the device.
11. The manufacturing method of the high-resistance field plate shielding gate groove type field effect transistor device is characterized by comprising the following steps:
s1, forming a groove on a semiconductor, forming a thin oxide layer in the groove, and then removing the thin oxide layer at the bottom of the groove;
s2, forming a thin conductive layer covering the thin oxide layer in the groove, and refilling filling materials;
s3, etching back the thin oxide layer;
s4, forming a gate oxide layer and a shielding gate oxide layer;
s5, forming a gate electrode, then forming upper surface metal, a contact hole and finally forming the device.
12. The manufacturing method of the high-resistance field plate shielding gate groove type field effect transistor device is characterized by comprising the following steps:
s1, forming a groove on a semiconductor, forming a thin oxide layer in the groove, and then removing the thin oxide layer at the bottom of the groove;
s2, filling high-resistance field plate materials in the grooves to form narrow groove high-resistance field plate structures;
s3, etching a wide groove above the semiconductor, etching a thin oxide layer, and refilling a shielding gate electrode material;
s4, forming a gate oxide layer and a shielding gate oxide layer;
s5, forming a gate electrode, then forming upper surface metal, a contact hole and finally forming the device.
13. The manufacturing method of the high-resistance field plate shielding gate groove type field effect transistor device is characterized by comprising the following steps:
s1, forming a wide groove on a semiconductor, and forming a gate oxide layer and a gate electrode;
s2, etching the middle part of the gate electrode and the semiconductor below the gate electrode to form a narrow groove, wherein the gate electrode part pole is remained in the wide groove;
s3, filling high-resistance field plate materials in the grooves to form high-resistance field plate structures;
s4, performing thermal oxidation, forming a shielding gate oxide layer on the gate electrode, and refilling shielding gate electrode materials;
s5, forming upper surface metal, contact holes and finally forming the device.
CN202310190056.7A 2023-03-02 2023-03-02 High-resistance field plate shielding gate groove type field effect transistor device and manufacturing method Pending CN116053325A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117558746A (en) * 2024-01-09 2024-02-13 润新微电子(大连)有限公司 Device containing variable-potential multi-field plate structure and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117558746A (en) * 2024-01-09 2024-02-13 润新微电子(大连)有限公司 Device containing variable-potential multi-field plate structure and preparation method thereof
CN117558746B (en) * 2024-01-09 2024-04-16 润新微电子(大连)有限公司 Device containing variable-potential multi-field plate structure and preparation method thereof

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