CN116052746A

CN116052746A - Voltage correction method, memory storage device and memory control circuit unit

Info

Publication number: CN116052746A
Application number: CN202310212268.0A
Authority: CN
Inventors: 陈柏皓; 苏柏诚; 曾士家; 许祐诚; 林纬
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2023-03-07
Filing date: 2023-03-07
Publication date: 2023-05-02

Abstract

The invention provides a voltage correction method, a memory storage device and a memory control circuit unit. The method comprises the following steps: reading first data from the first physical unit using the first read voltage level and reading second data from the at least one second physical unit using the second read voltage level; obtaining counting information according to the first data and the second data, wherein the counting information reflects the total number of storage units meeting preset conditions in the first entity unit and at least one second entity unit; and correcting the first read voltage level according to the count information. Thus, the correction efficiency of the read voltage level can be improved.

Description

Voltage correction method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory control technology, and more particularly, to a voltage correction method, a memory storage device and a memory control circuit unit.

Background

Smartphones, tablet computers and personal computers have grown very rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.

In a memory device in which one memory cell can store a plurality of bits, a plurality of preset read voltage levels are used to read data stored in memory cells belonging to different states. However, after the memory device is used for a period of time, as the memory cells wear, the preset read voltage levels may be severely shifted with respect to the threshold voltage distribution of the memory cells, and even shifted to the read voltage levels that are misinterpreted as being used to read the adjacent states. At this time, the conventional read voltage correction mechanism may not correct the read voltage level correctly, which may result in a shortened lifetime of the memory device.

Disclosure of Invention

The invention provides a voltage correction method, a memory storage device and a memory control circuit unit, which can improve the correction efficiency of a read voltage level.

Exemplary embodiments of the present invention provide a voltage correction method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module includes a plurality of physical units. The voltage correction method includes: reading first data from a first physical cell of the plurality of physical cells using a first read voltage level and reading second data from at least a second physical cell of the plurality of physical cells using a second read voltage level; obtaining counting information according to the first data and the second data, wherein the counting information reflects the total number of storage units meeting preset conditions in the first entity unit and the at least one second entity unit; and correcting the first read voltage level according to the count information.

In an exemplary embodiment of the present invention, the step of obtaining the count information according to the first data and the second data includes: determining the counting information according to first counting information and second counting information, wherein the first counting information reflects the total number of first storage units in the first entity unit, the second counting information reflects the total number of second storage units in the at least one second entity unit, the numerical relation between the critical voltage of the first storage unit and the first reading voltage level accords with a first condition, and the numerical relation between the critical voltage of the second storage unit and the second reading voltage level accords with a second condition.

In an exemplary embodiment of the present invention, the step of correcting the first read voltage level according to the count information includes: determining an adjustment value according to the count information; and correcting the first read voltage level according to the adjustment value.

In an exemplary embodiment of the present invention, the first entity unit and the at least one second entity unit operate in the same programming environment.

In an exemplary embodiment of the present invention, the first entity unit and the at least one second entity unit operate in the same programming environment, which means at least one of the entity programming units of the same type, time points when the first entity unit and the at least one second entity unit are programmed at least partially overlap, and time points when the first entity unit and the at least one second entity unit are programmed are adjacent to each other.

In an exemplary embodiment of the invention, the rewritable nonvolatile memory module includes a plurality of planes, the first physical unit is located in a first plane of the planes, and the at least one second physical unit is located in at least one second plane of the planes.

In an example embodiment of the present invention, the step of reading the first data from the first physical unit of the plurality of physical units using the first read voltage level and reading the second data from the at least one second physical unit of the plurality of physical units using the second read voltage level includes: performing a programming operation on an entity management unit to program the entity management unit, wherein the entity management unit comprises the first entity unit and the at least one second entity unit, and the entity management unit spans the first plane and the at least one second plane; and after programming the entity management unit, performing a read operation on the entity management unit to read the first data from the first entity unit using the first read voltage level and to read the second data from the at least one second entity unit using the second read voltage level.

In an exemplary embodiment of the present invention, the read operation for respectively reading the first data and the second data from the first entity unit and the at least one second entity unit includes one of a multi-plane read operation and a single page read operation.

In an exemplary embodiment of the present invention, in the reading operation for respectively reading the first data and the second data from the first entity unit and the at least one second entity unit, time points at which the first entity unit and the at least one second entity unit are read at least partially overlap or are adjacent to each other.

In an exemplary embodiment of the invention, the voltage correction method further includes: after the first data is acquired, performing a hard decoding operation on the first data, wherein the step of obtaining the count information according to the first data and the second data is performed after determining that the hard decoding operation on the first data fails.

In an example embodiment of the present invention, the second data is not applied in the hard decoding operation of the first data.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: sending at least one read command sequence, wherein the at least one read command sequence is used for indicating that first data is read from a first entity unit in the plurality of entity units by using a first read voltage level and second data is read from at least one second entity unit in the plurality of entity units by using a second read voltage level; obtaining counting information according to the first data and the second data, wherein the counting information reflects the total number of storage units meeting preset conditions in the first entity unit and the at least one second entity unit; and correcting the first read voltage level according to the count information.

In an example embodiment of the present invention, the operation of the memory control circuit unit to obtain the count information according to the first data and the second data includes: determining the counting information according to first counting information and second counting information, wherein the first counting information reflects the total number of first storage units in the first entity unit, the second counting information reflects the total number of second storage units in the at least one second entity unit, the numerical relation between the critical voltage of the first storage unit and the first reading voltage level accords with a first condition, and the numerical relation between the critical voltage of the second storage unit and the second reading voltage level accords with a second condition.

In an example embodiment of the present invention, the operation of the memory control circuit unit to correct the first read voltage level according to the count information includes: determining an adjustment value according to the count information; and correcting the first read voltage level according to the adjustment value.

In an example embodiment of the present invention, the operation of the memory control circuit unit to send the at least one read instruction sequence includes: sending at least one writing instruction sequence, wherein the at least one writing instruction sequence is used for indicating to execute programming operation on an entity management unit so as to program the entity management unit, the entity management unit comprises the first entity unit and the at least one second entity unit, and the entity management unit spans the first plane and the at least one second plane; and after programming the entity management unit, sending the at least one read instruction sequence, wherein the at least one read instruction sequence is used for indicating to perform a read operation on the entity management unit so as to read the first data from the first entity unit by using the first read voltage level and read the second data from the at least one second entity unit by using the second read voltage level.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: after the first data is acquired, performing a hard decoding operation on the first data, wherein the operation of obtaining the count information according to the first data and the second data is performed after determining that the hard decoding operation on the first data fails.

The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the memory interface and the memory interface. The memory management circuit is to: sending at least one read command sequence, wherein the at least one read command sequence is used for indicating that first data is read from a first entity unit in the plurality of entity units by using a first read voltage level and second data is read from at least one second entity unit in the plurality of entity units by using a second read voltage level; obtaining counting information according to the first data and the second data, wherein the counting information reflects the total number of storage units meeting preset conditions in the first entity unit and the at least one second entity unit; and correcting the first read voltage level according to the count information.

In an example embodiment of the present invention, the operation of the memory management circuit to obtain the count information according to the first data and the second data includes: determining the counting information according to first counting information and second counting information, wherein the first counting information reflects the total number of first storage units in the first entity unit, the second counting information reflects the total number of second storage units in the at least one second entity unit, the numerical relation between the critical voltage of the first storage unit and the first reading voltage level accords with a first condition, and the numerical relation between the critical voltage of the second storage unit and the second reading voltage level accords with a second condition.

In an example embodiment of the present invention, the operation of the memory management circuit to correct the first read voltage level according to the count information includes: determining an adjustment value according to the count information; and correcting the first read voltage level according to the adjustment value.

In an example embodiment of the present invention, the operation of the memory management circuit to send the at least one sequence of read instructions comprises: sending at least one writing instruction sequence, wherein the at least one writing instruction sequence is used for indicating to execute programming operation on an entity management unit so as to program the entity management unit, the entity management unit comprises the first entity unit and the at least one second entity unit, and the entity management unit spans the first plane and the at least one second plane; and after programming the entity management unit, sending the at least one read instruction sequence, wherein the at least one read instruction sequence is used for indicating to perform a read operation on the entity management unit so as to read the first data from the first entity unit by using the first read voltage level and read the second data from the at least one second entity unit by using the second read voltage level.

In an example embodiment of the present invention, the memory control circuit unit further includes an error checking and correcting circuit connected to the memory management circuit. The memory management circuit is also to: after the first data is acquired, the error checking and correcting circuit is instructed to perform a hard decoding operation on the first data, wherein the operation of obtaining the count information according to the first data and the second data is performed after determining that the hard decoding operation on the first data fails.

Based on the above, after the first data is read from the first physical unit using the first read voltage level and the second data is read from the at least one second physical unit using the second read voltage level, the count information can be obtained according to the first data and the second data. In particular, the count information may reflect a total number of storage units in the first entity unit and the second entity unit that meet a predetermined condition. Thereafter, the first read voltage level may be corrected based on the count information. Thus, the correction efficiency of the read voltage level can be effectively improved.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;

FIG. 5 is a schematic diagram of a memory control circuit unit shown according to an example embodiment of the invention;

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a threshold voltage distribution of a memory cell according to an exemplary embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating a correction operation of a read voltage according to an example embodiment of the invention;

FIG. 9 is a schematic diagram illustrating correction of a first read voltage level according to an example embodiment of the invention;

FIG. 10 is a schematic diagram of a first memory cell and a second memory cell according to an example embodiment of the invention;

FIG. 11 is a schematic diagram of a rewritable non-volatile memory module containing multiple planes, shown in accordance with an exemplary embodiment of the present invention;

FIG. 12 is a flowchart of a voltage correction method according to an exemplary embodiment of the present invention;

fig. 13 is a flowchart illustrating a voltage correction method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.

In an example embodiment, host system 11 may be coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention.

Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.

Fig. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the peripheral component interconnect local bus (Peripheral Component Interconnect Express, PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may be a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) compliant standard, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying a read voltage, it is possible to determine which memory state a memory cell belongs to, and thereby obtain one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If a memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and a physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Fig. 5 is a schematic diagram of a memory control circuit unit according to an example embodiment of the invention.

Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53. The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 51 is explained as follows, which is equivalent to the explanation of the operation of the memory control circuit unit 42.

In an example embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 51. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is connected to the memory management circuit 51. Memory management circuitry 51 may communicate with host system 11 through host interface 52. The host interface 52 is used to receive and identify the commands and data transmitted by the host system 11. For example, instructions and data transmitted by host system 11 may be transmitted to memory management circuit 51 via host interface 52. In addition, the memory management circuitry 51 may communicate data to the host system 11 through the host interface 52. In the present example embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 is to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.

The buffer memory 55 is connected to the memory management circuit 51 and is used for buffering data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of fig. 5 may include a flash memory management circuit.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention.

Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602. Each physical unit may include one or more physical programming units.

The entity units 610 (0) -610 (a) in the storage area 601 are used to store user data (e.g., user data from the host system 11 of fig. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and/or invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).

The memory management circuit 51 may configure the logic units 612 (0) through 612 (C) to map the physical units 610 (0) through 610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.

It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is currently mapped by a certain logic unit, the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit is invalid.

The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

In the following exemplary embodiment, the MLC NAND type flash memory module is described as the type of the rewritable nonvolatile memory module 43. However, in another example embodiment, the same or similar operations may also be applied to TLC NAND type, QLC NAND type, or other types of flash memory modules.

In an exemplary embodiment, the memory management circuit 51 performs a randomization operation on the original data to randomize the original data into another data (also referred to as random data) before storing the original data (also referred to as the original data) in one or more physical units (also referred to as first physical units) in the rewritable nonvolatile memory module 43. For example, after a randomization operation, the number of bits "0" and "1" in the random data may tend to agree (i.e., be equal or close).

In an example embodiment, the memory management circuit 51 may send a write command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to program the randomized original data (i.e., random data) to a plurality of memory cells in the first physical unit. For example, a programmed memory cell may be attempted to be programmed evenly to store bits "11", "10", "00", and "01".

In an example embodiment, the raw data is from the host system 11 with the data to be stored to the memory storage device 10. The original data can be randomized and then stored. In an exemplary embodiment, the number of bits of the original data is the same as the number of bits of the random data.

FIG. 7 is a schematic diagram illustrating a threshold voltage distribution of a memory cell according to an exemplary embodiment of the present invention. It should be noted that fig. 7 shows the threshold voltage distribution of the programmed memory cells after the memory cells in the first physical cell are programmed according to the random data. In fig. 7, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

Referring to FIG. 7, the programmed memory cell in the first physical unit may have 4 states 701-704. The memory cells belonging to states 701-704 may be used to store bits "11", "10", "00" and "01", respectively. In other words, states 701 to 704 correspond to preset bit values "11", "10", "00" and "01", respectively. However, in another example embodiment, the number of states 701-704 may be adjusted, and the preset bit value corresponding to each state may also be adjusted.

In an example embodiment, it is assumed that the programmed memory cells are evenly distributed among states 701-704. That is, if the total number of memory cells is N and the total number of states 701-704 is M (i.e., 4), then the total number of memory cells belonging to each of states 701-704 is preset to be N/M (i.e., N/4).

When data is to be read, the read voltage levels VH (1) -VH (3) may be applied to the first physical unit to read the data stored in at least some of the memory cells in the first physical unit. In other words, by sequentially applying the read voltage levels VH (1) to VH (3) to the first physical cell, one of the memory cells in the first physical cell can be determined to belong to one of the states 701 to 704, so as to obtain the data stored in the memory cell. For example, if a certain memory cell is turned on by the read voltage level VH (2) but not turned on by the read voltage level VH (3), the threshold voltage of the memory cell is between the read voltage levels VH (2) and VH (3). Thus, it may be determined that this memory cell belongs to state 703 and is used to store bit "00".

However, as the usage time of the first entity unit increases and/or the operating environment changes, performance degradation (degradation) of the storage units in the first entity unit may occur. After performance degradation occurs, the states 701-704 may gradually approach each other and even overlap each other. In addition, the states 701-704 may also become flatter. For example, states 711-714 may be used to represent the threshold voltage distribution of the memory cells in the first physical cell after performance degradation.

After the performance degradation occurs, the read voltage levels VH (1) to VH (3) are severely shifted from the states 711 to 714, as shown in fig. 7. At this time, if the uncorrected read voltage levels VH (1) -VH (3) are continuously used to read the memory cells, the states of many memory cells are misjudged, and thus many errors exist in the data read from the first physical cell. If too many errors are included in the read data, the data may not be successfully decoded and output.

Fig. 8 is a schematic diagram illustrating a correction operation of a read voltage according to an exemplary embodiment of the present invention.

Referring to fig. 8, in an example embodiment, the memory management circuit 51 may read data 801 (also referred to as first data) from the physical unit 81 (i.e., the first physical unit) using at least one read voltage level and read data 802 (also referred to as second data) from the physical unit 82 (also referred to as the second physical unit) using at least one read voltage level. In particular, the read voltage level for reading data 801 from physical cell 81 comprises a first read voltage level, and the read voltage level for reading data 802 from physical cell 82 comprises a second read voltage level. The voltage value of the first read voltage level may be the same or different from the voltage value of the second read voltage level. In addition, the

entity units

81 and 82 may include at least one entity unit among the entity units 610 (0) to 610 (a) of fig. 6, respectively. It should be noted that the number of physical units 82 may be one or more.

After acquiring the

data

801 and 802, the memory management circuit 51 can obtain the count information 803 according to the

data

801 and 802. The count information 803 may reflect the total number of memory cells in the

entity units

81 and 82 that meet the predetermined condition. Then, the memory management circuit 51 may correct the first read voltage level according to the count information 803. Alternatively, from another point of view, the memory management circuit 51 may correct the first read voltage level according to the total number of memory cells in the

physical units

81 and 82 meeting the predetermined condition.

Fig. 9 is a schematic diagram illustrating correction of a first read voltage level according to an example embodiment of the invention.

Referring to fig. 8 and 9, it is assumed that the first read voltage level is the read voltage level VH (3). The memory management circuit 51 may determine an adjustment value Δv according to the count information 803. For example, the memory management circuit 51 may input the count information 803 into an equation or lookup table and obtain the adjustment value ΔV based on the output of the equation or lookup table. Then, the memory management circuit 51 may correct the first read voltage level from the read voltage level VH (3) to the read voltage level VH (3)' according to the adjustment value Δv. The read voltage level VH (3)' is closer to the interface between

states

713 and 714 than the read voltage level VH (3). Therefore, using the read voltage level VH (3)' to re-read data from the physical unit 81 as compared to the read voltage level VH (3) can effectively reduce the total number of error bits in the read data. In addition, the first read voltage level may also be the remaining read voltage levels (e.g., read voltage level VH (1) or VH (2) of fig. 7) used to read the first physical cell.

In an example embodiment, the memory management circuit 51 may obtain one count information (also referred to as a first count information) based on the data 801 and another count information (also referred to as a second count information) based on the data 802. The first count information may reflect the total number of memory cells (also referred to as first memory cells) in the entity unit 81 that meet a predetermined condition (also referred to as first predetermined condition). For example, the first count information may be obtained by counting the total number of bits "1" (or bits "0") in the data 801. The second count information may reflect a total number of memory cells (also referred to as second memory cells) in the physical unit 82 that satisfy another predetermined condition (also referred to as second predetermined condition). For example, the second count information may be obtained by counting the total number of bits "1" (or bits "0") in the data 802.

In an exemplary embodiment, the memory management circuit 51 may determine, as the first memory cell, a memory cell in which a numerical relationship between the threshold voltage and the first read voltage level in the physical cell 81 meets a specific condition (also referred to as a first condition) according to the data 801. For example, the first memory cell may include all memory cells in the physical cell 81 having a threshold voltage less than the first read voltage level. In other words, the first memory cell may be turned on by the first read voltage level in the process of applying the first read voltage level to the physical unit 81 to read the data 801.

In an exemplary embodiment, the memory management circuit 51 may determine, as the second memory cell, a memory cell in the physical cell 82 for which the numerical relationship between the threshold voltage and the second read voltage level meets a certain condition (also referred to as a second condition) according to the data 802. For example, the second memory cell may include all memory cells in the physical cell 82 having a threshold voltage less than the second read voltage level. In other words, the second memory cell may be turned on by the second read voltage level during the process of applying the second read voltage level to the physical cell 82 to read the data 802.

Fig. 10 is a schematic diagram of a first memory cell and a second memory cell according to an exemplary embodiment of the invention.

Referring to fig. 8 and 10, it is assumed that distribution 1001 is a threshold voltage distribution (also referred to as a first threshold voltage distribution) of a plurality of memory cells in physical cell 81, and distribution 1002 is a threshold voltage distribution (also referred to as a second threshold voltage distribution) of a plurality of memory cells in physical cell 82. Further, it is assumed that the first read voltage level is the read voltage level VH (3), and the second read voltage level is the read voltage level VH (4).

In an example embodiment, the memory management circuit 51 may obtain the count information Δc (1) (i.e., the first count information) according to the data 801. The count information Δc (1) may reflect the total number of memory cells (i.e., the first memory cells) in the physical unit 81 having the threshold voltage smaller than the read voltage level VH (3). For example, the value of count information Δc (1) may be positively correlated with the area of the sloped line region in distribution 1001.

In an example embodiment, the memory management circuit 51 may obtain count information Δc (2) (i.e., second count information) according to the data 802. The count information Δc (2) may reflect the total number of memory cells (i.e., second memory cells) in the physical cell 82 having a threshold voltage less than the read voltage level VH (4). For example, the value of count information ΔC (2) may be positively correlated to the area of the slashed region in distribution 1002.

In an exemplary embodiment, the memory management circuit 51 may obtain preset count information (also referred to as first preset count information) corresponding to the entity unit 81 and obtain preset count information (also referred to as second preset count information) corresponding to the entity unit 82. The first preset count information may reflect an ideal value of the first count information. The second preset count information may reflect an ideal value of the second count information. Taking fig. 10 as an example, the values of the first preset count information and the second preset count information may be 3× (N/4), where N is the total number of memory cells in a physical unit.

In an exemplary embodiment, a difference between the first count information and the first predetermined count information (also referred to as a first difference) may reflect a degree of shift of the first read voltage level compared to a threshold voltage distribution (i.e., a first threshold voltage distribution) of the plurality of memory cells in the first physical cell. Taking fig. 10 as an example, the larger the difference (i.e., the first difference) between the count information Δc (1) and the first preset count information, the greater the offset of the read voltage level VH (3) from the first threshold voltage distribution. Similarly, the difference between the second count information and the second predetermined count information (also referred to as a second difference) may reflect the degree of deviation of the second read voltage level from the threshold voltage distribution (i.e., the second threshold voltage distribution) of the plurality of memory cells in the second physical cell. Taking fig. 10 as an example, the larger the difference between the count information Δc (2) and the second preset count information (i.e., the second difference), the greater the offset degree of the read voltage level VH (4) compared to the second threshold voltage distribution.

In an example embodiment, the memory management circuit 51 may correct the first read voltage level according to the first difference value to eliminate or reduce the offset between the first read voltage level and the first threshold voltage distribution. For example, the memory management circuit 51 may determine the adjustment value Δv in fig. 9 according to the first difference value and correct the read voltage level VH (3) according to the adjustment value Δv. Similarly, the memory management circuit 51 may correct the second read voltage level according to the second difference to eliminate or reduce the offset between the second read voltage level and the second threshold voltage distribution.

It should be noted that, in an exemplary embodiment, if the first read voltage level is corrected simply according to the first count information or the first difference, the correction efficiency of the first read voltage level may be reduced due to the inaccuracy of the first preset count information. Taking fig. 9 as an example, it is assumed that the value of the first preset count information is 3× (N/4), but in reality the number of memory cells belonging to states 711 to 713 is 3× (N/4) +r, where R can be regarded as noise and can be a positive or negative value. This noise (i.e., R) can result from imperfections in randomization of the original data. Due to this noise (i.e., R), the adjustment value Δv determined according to the first difference may not be accurate enough, thereby reducing the correction efficiency of the read voltage level VH (3).

In an example embodiment, the memory management circuit 51 may obtain the count information 803 of fig. 8 according to the sum of the first count information and the second count information. For example, the value of count information 803 may be equal to or positively correlated with the sum of count information Δc (1) and Δc (2) of fig. 10. In addition, the memory management circuit 51 may obtain another preset count information (also referred to as a third preset count information) according to the sum of the first preset count information and the second preset count information. Taking fig. 10 as an example, assuming that the values of the first preset count information and the second preset count information are both 3× (N/4), the value of the third preset count information may be 2×3× (N/4).

In an example embodiment, the memory management circuit 51 may obtain a difference (also referred to as a third difference) between the count information 803 and the third predetermined count information. The memory management circuit 51 may correct the first read voltage level according to the third difference. For example, the memory management circuit 51 may determine the adjustment value Δv in fig. 9 according to the third difference value. For example, the memory management circuit 51 may input the third difference value to an equation or a lookup table and obtain the adjustment value Δv according to the output of the equation or the lookup table. For example, the third difference may be positively correlated to the adjustment value Δv. Then, the memory management circuit 51 may correct the read voltage level VH (3) according to the adjustment value Δv.

In other words, in an exemplary embodiment, the influence of the noise on the preset count information is reduced by increasing the base of the preset count information (e.g., the third preset count information is equal to the sum of the first preset count information and the second preset count information). Thereby, the above-described problem can be improved and the correction efficiency for the first read voltage level can be improved.

In an exemplary embodiment, in order to correct the first read voltage level for reading the physical unit 81, the physical unit 82 must meet a specific filtering condition. For example, the filtering condition may include that the first entity and the second entity must be operated in the same programming environment. If the selected physical unit 82 does not meet the filtering condition, the first reading voltage level may be misaligned due to the different programming environments of the first physical unit and the second physical unit.

In an example embodiment, the rewritable nonvolatile memory module 43 may include a plurality of planes (also referred to as memory planes). The physical unit 81 may be located in one of the planes (also referred to as a first plane). The physical unit 82 may be located in another one of the plurality of planes (also referred to as a second plane).

In an exemplary embodiment,

entity units

81 and 82 may belong to the same entity management unit. For example, an entity management unit is also referred to as a super entity programmer (super physical programming unit) or super page (loader page). The physical management unit may span a first plane and a second plane. The memory management circuit 51 may access the

physical units

81 and 82 via the same or different channels.

FIG. 11 is a schematic diagram of a rewritable non-volatile memory module including multiple planes according to an example embodiment of the present invention.

Referring to fig. 11, assume that the rewritable nonvolatile memory module 43 includes a plane P (1) (i.e., a first plane) and a plane P (2) (i.e., a second plane). The memory management circuit 51 can access the planes P (1) and P (2) through the channels CH (1) and CH (2), respectively. The plane P (1) contains a plurality of physical units, and the plane P (2) also contains a plurality of physical units. For example, planes P (1) and P (2) may belong to the same or different dies (die). The die are obtained from a Wafer (Wafer) by laser dicing.

In an example embodiment, the

entity units

81 and 82 of fig. 8 may include

entity units

1101 and 1102, respectively. The physical unit 1101 is located in plane P (1), and the physical unit 1102 is located in plane P (2). The entity management unit 1110 includes

entity units

1101 and 1102. In addition, the entity management unit 1110 spans planes P (1) and P (2).

In an example embodiment, the memory management circuit 51 may send at least one write command sequence to the rewritable nonvolatile memory module 43. The sequence of write instructions may instruct the rewritable non-volatile memory module 43 to perform a programming operation on the entity management unit 1110 to program the entity management unit 1110. For example, the write command sequences may be transmitted to planes P (1) and P (2) via channels CH (1) and CH (2), respectively. According to the write instruction sequence, the

entity units

1101 and 1102 in the entity management unit 1110 may be synchronized or continuously programmed. In an example embodiment, the programming operation performed on entity management unit 1110 is also referred to as a multi-plane (multi-plane) write operation.

After programming the entity management unit 1110, the memory management circuit 51 may send at least one sequence of read instructions to the rewritable non-volatile memory module 43. The sequence of read instructions may instruct the rewritable non-volatile memory module 43 to perform a read operation on the entity management unit 1110. For example, the read command sequences may be transmitted to planes P (1) and P (2) via channels CH (1) and CH (2), respectively. According to the read command sequence, the rewritable nonvolatile memory module 43 can read data (i.e. first data) from the physical unit 1101 using at least one read voltage level including a first read voltage level and read data (i.e. second data) from the physical unit 1102 using at least one read voltage level including a second read voltage level. Then, the memory management circuit 51 may perform the aforementioned correction for the first read voltage level according to the first data and the second data. In an example embodiment, the read operation performed on the entity management unit 1110 is also referred to as a multi-plane read operation. Furthermore, in an exemplary embodiment, channels CH (1) and CH (2) may also be implemented as a single channel.

It should be noted that although in the exemplary embodiment of fig. 11, the entity units 1101 (i.e., the first entity unit) and 1102 (i.e., the second entity unit) are included in the same entity management unit and located on different planes, in another exemplary embodiment, the first entity unit and the second entity unit may not be included in the same entity management unit and/or the first entity unit and the second entity unit may be located on the same plane, as long as the first entity unit and the second entity unit operate in the same programming environment.

In an exemplary embodiment, the first entity unit and the second entity unit operate in the same programming environment, which may mean that the first entity unit and the second entity unit belong to the same type of entity programming unit, the first entity unit and the second entity unit are included in the same entity management unit, and/or the time points when the first entity unit and the second entity unit are programmed at least partially overlap or are adjacent to each other. The first entity unit and the second entity unit belong to the same type of entity programming unit, which may mean that both the first entity unit and the second entity unit belong to an upper entity programming unit (e.g., upper page), a middle entity programming unit (e.g., middle page), or a lower entity programming unit (e.g., lower page). The physical programming unit may also have other types for different types of flash memory modules, and the invention is not limited thereto. The time points at which the first entity unit and the second entity unit are programmed at least partially overlap or are adjacent to each other may mean that the time difference between the time point at which the first entity unit is programmed and the time point at which the second entity unit is programmed is less than a predetermined value or that the first entity unit and the second entity unit are programmed in parallel or consecutively.

In an exemplary embodiment, the memory management circuit 51 may also issue a read command (e.g., a single page read command) to the rewritable nonvolatile memory module 43 to read the first data and the second data from the first physical unit and the second physical unit, respectively.

In an exemplary embodiment, on the premise that the first entity unit and the second entity unit operate in the same programming environment, in a reading operation of reading the first data and the second data from the first entity unit and the second entity unit, respectively, the time points when the first entity unit and the second entity unit are read also at least partially overlap or are adjacent to each other. For example, the time points at which the first entity unit and the second entity unit are read at least partially overlap or are adjacent to each other may mean that the time difference between the time point at which the first entity unit is read and the time point at which the second entity unit is read is smaller than a preset value or that the first entity unit and the second entity unit are read in parallel or continuously.

In an example embodiment, after the first data is obtained, the memory management circuit 51 may instruct the error checking and correction circuit 54 to perform a decoding operation (also referred to as a hard decoding operation) on the first data in an attempt to correct an error in the first data. If the hard decoding operation on the first data is successful (indicating that all errors in the first data are corrected), the memory management circuit 51 may output the successfully decoded first data. For example, the memory management circuit 51 may read the first data and transmit the successfully decoded first data back to the host system 11 in response to a read instruction from the host system 11. In addition, if the hard decoding operation for the first data fails, the memory management circuit 51 may initiate a read voltage correction for the first read voltage level. For example, in the read voltage correction, the memory management circuit 51 may obtain count information according to the first data and the second data and correct the first read voltage level according to the count information. Details of the relevant operations are detailed above and are not repeated here.

In an exemplary embodiment, if a decoding of a certain time in the hard decoding operation cannot correct all errors (i.e. decoding fails) in the first data, the memory management circuit 51 may update a retry count (e.g. increment the retry count by one) and determine whether the retry count reaches a predetermined value. If the retry count does not reach the predetermined value, the memory management circuit 51 may query a retry table (retry table) to change the read voltage level (including the first read voltage level) used to read the first physical cell. The memory management circuit 51 may then use the changed read voltage level to re-read the data from the first entity unit until the read data (i.e., the first data) can be successfully decoded or the retry count reaches a preset value. In an exemplary embodiment, if the retry count reaches a predetermined value, the memory management circuit 51 may determine that the hard decoding operation for the first data fails and initiate the read voltage correction corresponding to the first physical cell.

In an example embodiment, the second data read from the second physical unit is not applied in a hard decoding operation of the first data. In an exemplary embodiment, if the second data has been read from the second physical unit before or during decoding of the first data, the memory management circuit 51 may cache the second data in the buffer memory 55 and not apply the second data to the hard decoding operation of the first data. In an example embodiment, the memory management circuit 51 does not apply the second data to the read voltage correction for the first physical unit until it is determined that the hard decoding operation for the first data fails and/or the read voltage correction for the first physical unit is activated. Details of the relevant operations are detailed above and are not repeated here.

Fig. 12 is a flowchart illustrating a voltage correction method according to an exemplary embodiment of the present invention.

Referring to fig. 12, in step S1201, first data is read from a first physical unit using a first read voltage level and second data is read from at least one second physical unit using a second read voltage level. In step S1202, count information is obtained according to the first data and the second data, wherein the count information reflects the total number of storage units meeting a preset condition in the first entity unit and the at least one second entity unit. In step S1203, the first read voltage level is corrected according to the count information.

Referring to fig. 13, in step S1301, first data is read from a first physical cell using a first read voltage level. In step S1302, the first data is decoded. In step S1303, it is determined whether decoding of the first data fails. If the decoding of the first data has not failed (i.e., the decoding is successful), the decoded first data is output in step S1304. If the decoding of the first data fails, the retry count is updated in step S1305. In step S1306, it is determined whether the retry count reaches a preset value. If the retry count does not reach the preset value, in step S1307, the first read voltage level is changed, and step S1301 is repeatedly performed. In addition, if the retry count reaches the preset value, in step S1308, the read voltage correction corresponding to the first physical unit is started and executed.

However, the steps in fig. 12 and 13 are described in detail above, and will not be repeated here. It should be noted that each step in fig. 12 and fig. 13 may be implemented as a plurality of program codes or circuits, which is not limited in this disclosure. In addition, the methods of fig. 12 and 13 may be used with the above exemplary embodiments, or may be used alone, which is not limited in this disclosure.

In summary, the voltage correction method, the memory storage device and the memory control circuit unit according to the exemplary embodiments of the present invention can apply the second data read from the additional physical unit (i.e. the second physical unit) to the correction operation of the first read voltage level. Therefore, the influence of the programming error (or the randomizing error) of a single physical unit on the whole can be reduced, so that the correction efficiency of the first reading voltage level can be improved.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A voltage correction method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical cells, and the voltage correction method comprises:

reading first data from a first physical cell of the plurality of physical cells using a first read voltage level and reading second data from at least a second physical cell of the plurality of physical cells using a second read voltage level;

obtaining counting information according to the first data and the second data, wherein the counting information reflects the total number of storage units meeting preset conditions in the first entity unit and the at least one second entity unit; and

correcting the first read voltage level according to the count information.

2. The voltage correction method according to claim 1, wherein the step of obtaining the count information from the first data and the second data includes:

determining the counting information according to the first counting information and the second counting information,

the first count information reflects the total number of first storage units in the first entity unit, the second count information reflects the total number of second storage units in the at least one second entity unit, the numerical relation between the critical voltage of the first storage units and the first reading voltage level accords with a first condition, and the numerical relation between the critical voltage of the second storage units and the second reading voltage level accords with a second condition.

3. The voltage correction method of claim 1, wherein correcting the first read voltage level according to the count information comprises:

determining an adjustment value according to the count information; and

correcting the first read voltage level according to the adjustment value.

4. The method of claim 1, wherein the first physical unit and the at least one second physical unit operate in a same programming environment.

5. The voltage correction method according to claim 4, wherein the first entity unit and the at least one second entity unit operate in the same programming environment, which means at least one of the first entity unit and the at least one second entity unit belonging to the same type of entity programming unit, at least partially overlapping the time points at which the first entity unit and the at least one second entity unit are programmed, and adjacent to each other.

6. The method of claim 1, wherein the rewritable nonvolatile memory module comprises a plurality of planes, the first physical unit is located in a first plane of the plurality of planes, and the at least one second physical unit is located in at least one second plane of the plurality of planes.

7. The voltage correction method of claim 6, wherein reading the first data from the first one of the plurality of physical units using the first read voltage level and reading the second data from the at least one second one of the plurality of physical units using the second read voltage level comprises:

performing a programming operation on an entity management unit to program the entity management unit, wherein the entity management unit comprises the first entity unit and the at least one second entity unit, and the entity management unit spans the first plane and the at least one second plane; and

after programming the entity management unit, a read operation is performed on the entity management unit to read the first data from the first entity unit using the first read voltage level and to read the second data from the at least one second entity unit using the second read voltage level.

8. The voltage correction method of claim 1, wherein the read operation for respectively reading the first data and the second data from the first physical unit and the at least one second physical unit comprises one of a multi-plane read operation and a single page read operation.

9. The voltage correction method of claim 1, wherein in a read operation for respectively reading the first data and the second data from the first physical unit and the at least one second physical unit, time points at which the first physical unit and the at least one second physical unit are read at least partially overlap or are adjacent to each other.

10. The voltage correction method of claim 1, further comprising:

after the first data is retrieved, performing a hard decoding operation on the first data,

wherein the step of obtaining the count information from the first data and the second data is performed after determining that the hard decoding operation on the first data fails.

11. The voltage correction method of claim 10, wherein the second data is not applied in the hard decoding operation of the first data.

12. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

Wherein the memory control circuit unit is configured to:

sending at least one read command sequence, wherein the at least one read command sequence is used for indicating that first data is read from a first entity unit in the plurality of entity units by using a first read voltage level and second data is read from at least one second entity unit in the plurality of entity units by using a second read voltage level;

correcting the first read voltage level according to the count information.

13. The memory storage device of claim 12, wherein the operation of the memory control circuit unit to obtain the count information from the first data and the second data comprises:

14. The memory storage device of claim 12, wherein the operation of the memory control circuit unit to correct the first read voltage level according to the count information comprises:

determining an adjustment value according to the count information; and

correcting the first read voltage level according to the adjustment value.

15. The memory storage device of claim 12, wherein the first entity unit and the at least one second entity unit operate in a same programming environment.

16. The memory storage device of claim 15, wherein the first entity unit and the at least one second entity unit operate in a same programming environment, meaning at least one of the first entity unit and the at least one second entity unit belong to a same type of entity programming unit, time points at which the first entity unit and the at least one second entity unit are programmed at least partially overlap, and time points at which the first entity unit and the at least one second entity unit are programmed are adjacent to each other.

17. The memory storage device of claim 12, wherein the rewritable non-volatile memory module comprises a plurality of planes, the first physical unit is located in a first plane of the plurality of planes, and the at least one second physical unit is located in at least one second plane of the plurality of planes.

18. The memory storage device of claim 17, wherein the operation of the memory control circuit unit sending the at least one sequence of read instructions comprises:

sending at least one writing instruction sequence, wherein the at least one writing instruction sequence is used for indicating to execute programming operation on an entity management unit so as to program the entity management unit, the entity management unit comprises the first entity unit and the at least one second entity unit, and the entity management unit spans the first plane and the at least one second plane; and

after programming the entity management unit, sending the at least one read instruction sequence, wherein the at least one read instruction sequence is used for instructing the entity management unit to execute a read operation so as to read the first data from the first entity unit by using the first read voltage level and read the second data from the at least one second entity unit by using the second read voltage level.

19. The memory storage device of claim 12, wherein the read operation for respectively reading the first data and the second data from the first physical unit and the at least one second physical unit comprises one of a multi-plane read operation and a single page read operation.

20. The memory storage device of claim 12, wherein in a read operation for reading the first data and the second data from the first physical unit and the at least one second physical unit, respectively, points in time at which the first physical unit and the at least one second physical unit are read at least partially overlap or are adjacent to each other.

21. The memory storage device of claim 12, wherein the memory control circuit unit is further to:

wherein the operation of obtaining the count information from the first data and the second data is performed after determining that the hard decoding operation on the first data fails.

22. The memory storage device of claim 21, wherein the second data is not applied in the hard decoding operation of the first data.

23. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, and the memory control circuit unit includes:

A host interface for connecting to a host system;

a memory interface to connect to the rewritable non-volatile memory module; and

a memory management circuit coupled to the memory interface and the memory interface,

wherein the memory management circuit is to:

correcting the first read voltage level according to the count information.

24. The memory control circuit unit of claim 23, wherein the operation of the memory management circuit to obtain the count information from the first data and the second data comprises:

25. The memory control circuit unit of claim 23, wherein the operation of the memory management circuit to correct the first read voltage level according to the count information comprises:

determining an adjustment value according to the count information; and

correcting the first read voltage level according to the adjustment value.

26. The memory control circuit unit of claim 23, wherein the first physical unit and the at least one second physical unit operate in a same programming environment.

27. The memory control circuit unit of claim 26, wherein the first entity unit and the at least one second entity unit operate in a same programming environment, which means at least one of the first entity unit and the at least one second entity unit belong to a same type of entity programming unit, time points at which the first entity unit and the at least one second entity unit are programmed at least partially overlap, and time points at which the first entity unit and the at least one second entity unit are programmed are adjacent to each other.

28. The memory control circuit unit of claim 23, wherein the rewritable non-volatile memory module comprises a plurality of planes, the first physical unit is located in a first plane of the plurality of planes, and the at least one second physical unit is located in at least one second plane of the plurality of planes.

29. The memory control circuit unit of claim 28, wherein the operation of the memory management circuit sending the at least one sequence of read instructions comprises:

30. The memory control circuit unit of claim 23, wherein the read operation for respectively reading the first data and the second data from the first physical unit and the at least one second physical unit comprises one of a multi-plane read operation and a single page read operation.

31. The memory control circuit unit of claim 23, wherein in a read operation for reading the first data and the second data from the first physical unit and the at least one second physical unit, respectively, points in time at which the first physical unit and the at least one second physical unit are read at least partially overlap or are adjacent to each other.

32. The memory control circuit unit of claim 23, wherein the memory control circuit unit further comprises an error checking and correction circuit connected to the memory management circuit, and the memory management circuit is further to:

after the first data is obtained, the error checking and correcting circuit is instructed to perform a hard decoding operation on the first data,

33. The memory control circuit unit of claim 32, wherein the second data is not applied in the hard decoding operation of the first data.