CN116048479B

CN116048479B - Quick programming method for memory and calculation integrated chip

Info

Publication number: CN116048479B
Application number: CN202310341637.6A
Authority: CN
Inventors: 王宇宣; 郝晨君; 安梦瑜; 潘红兵; 彭成磊
Original assignee: Nanjing University
Current assignee: Nanjing University
Priority date: 2023-04-03
Filing date: 2023-04-03
Publication date: 2023-07-21
Anticipated expiration: 2043-04-03
Also published as: CN116048479A

Abstract

The invention discloses a rapid programming method for a memory and calculation integrated chip, and belongs to the field of memory and calculation integrated chips. The method comprises the following steps: step 1, extracting position information of 0 in a matrix to be programmed; step 2, programming on the memory integrated chip according to the position information of 0 in a whole-column programming mode; and step 3, programming the non-0 value on the memory integrated chip. The invention fully considers the characteristics of large 0 value programming difficulty and excessive programming resistance of the memory integrated device, separately programs the 0 value and other values, and the 0 value programming can program an entire column at a time according to the entire column programming mode, and the verification times are reduced to only one verification time for each column programming according to the characteristic that the 0 value result is accumulated to 0, thereby greatly shortening the programming time of the 0 value and further shortening the programming time of the whole matrix. The invention greatly improves the time of the AI application deployment on the memory integrated chip.

Description

Quick programming method for memory and calculation integrated chip

Technical Field

The invention relates to a rapid programming method for a memory and calculation integrated chip, and belongs to the field of memory and calculation integrated chips.

Background

The existing deep neural network has large weight and high calculation complexity, and a large amount of off-chip caches are required to be accessed to complete matrix multiplication and addition, so that the storage wall and the power consumption wall of the traditional calculation architecture limit the further increase of energy efficiency.

The integrated architecture of memory and calculation can realize integration of calculation and memory, and can complete a large amount of matrix multiplication and addition operations with extremely low power consumption, thus becoming one of the most promising architectures. However, the existing integrated device generally has the defects of high programming difficulty and low programming speed. For example, patent application CN111208865a discloses a photoelectric calculation unit, a memory integrated chip and a photoelectric calculation method, where the memory integrated chip can be programmed by means of optical input, and is characterized in that the programming is performed from the maximum value to the small direction, the early programming speed is fast, the later programming speed is slow, and the difficulty of programming to 0 value is relatively large.

It has been reported in the literature (Wan W, kubendor R, schaefer C, et al, A computer-in-memory chip based on resistive random-access memory J. Nature, 2022, 608 (7923): 504-512.) that the accuracy of device programming can be flexibly adjusted using an incremental pulse write verification technique, but the programming speed is limited by DAC and ADC, and the programming speed can only be increased by increasing DAC and ADC, which would increase additional chip area without taking into account the programming specificity of 0 values.

Disclosure of Invention

In order to solve the problems, the invention provides a rapid programming method for a memory integrated chip, which optimizes the programming speed of the memory integrated chip. In the invention, the neural network has larger sparsity, the weight array contains a large number of 0 values, the 0 values are not over programmed, and the programming of the 0 values and other values are separately programmed, so that the programming efficiency can be improved; the input result of each column of the memory integrated chip array is the accumulation of the output result of the column, because the 0 value of the whole column can be directly programmed in the process of programming 0, and the programming condition can be verified by only one verification.

The invention provides a rapid programming method for a memory integrated chip, which comprises the following steps: obtain location information for 0, program a 0 value, program a non-0 value.

In one embodiment, the method, programming the 0 value is specifically: and programming 0 on a whole column of the matrix directly on the memory integrated chip in a column programming mode, wherein when all devices with 0 in the whole column are turned on, the output result of current accumulation is 0, programming is considered to be finished, and programming of the next column is performed until the value of 0 in the whole matrix is coded.

In one embodiment, the method specifically comprises the following steps:

step 1, acquiring position information of a value 0; for the matrix to be programmed, when the element in the matrix is 0, the element is marked as 1, and when the element in the matrix is not 0, the element is marked as 0, so that the position information of 0 in the matrix is obtained, and the position information is stored with the least data;

step 2, programming a value of 0; inputting 0 position information (a place marked as 1 in step 1), programming 0 according to the 0 position information, wherein the process adopts a column programming mode to directly program 0 on a whole column in a matrix on an integrated memory chip, the output result of current accumulation is 0 (a certain error is allowed) when all devices with 0 in the whole column are opened, programming is considered to be finished, and programming of the next column is performed until the value of 0 in the whole matrix is compiled;

step 3, programming a non-0 value; inputting a matrix to be programmed, and starting programming non-0 values of the matrix; the programming of the next value is skipped directly when a value of 0 is encountered in step 3.

Further, in the step 1, the method for obtaining the position information of the matrix 0 to be programmed is as follows: and taking a null matrix corresponding to the matrix to be programmed, setting the position corresponding to 0 as 1, setting the position corresponding to the non-0 value as 0, obtaining a 0-position matrix, and storing. In practical application, the number of devices programmed each time can be controlled by adjusting the position matrix of 0 so as to adapt to different scene requirements.

Further, in the step 2, the programming for the value 0 includes three phases of judging, programming and verifying. In the judging stage, for the column without 0 value, the column is directly skipped and the next column is judged until the column with 0 value appears, and the programming mode is entered. In the programming stage, programming is carried out according to the 0 position matrix obtained in the step 1, and programming is carried out on the 0 value of an entire column at each time; in the verification stage, the calculation result of one column of the integrated memory chip is read, and since the readout result of one column of the integrated memory chip is the sum of the output results of all the turned-on devices in the column, when the 0 value is successfully programmed, the readout result should also be 0. The 0 values of the entire matrix are programmed in this way until all 0 values have been coded.

Further, the programming in the step 2 includes two modes, and only the programming time periods of the two modes are different; in the invention, in the two modes, the relative programming time is long and the relative programming time is short. The first programming is performed in a long programming mode, a longer time is compiled according to the actual measurement result of the chip device programming to 0, then verification is started, verification is passed, programming of the next value is performed, if verification is not passed, a short programming mode is performed, the device to be programmed further approaches to the 0 value, and a shorter time can be set in the process.

Further, in the step 2, a certain error is allowed, mainly: the integrated memory chip has certain non-ideality, different material processes are different, so that partial devices can only be practically approximate to but cannot be programmed to an absolute 0 value, and the integrated memory chip is acceptable as long as the performance of AI application deployed on the chip is not greatly influenced, and different application conditions are different.

Further, in the step 3, the programming for the non-0 value includes three phases: pre-judging, programming and checking. In the pre-judging stage, judging whether the value is 0, if so, skipping the value, simultaneously updating the position of the value to be programmed, judging the next value until the value is a non-0 value, and entering the programming stage; the programming stage adopts a mode of programming a single device one by one, comprising programming one by rows and programming one by columns, programming one by rows, then programming the next row from the beginning, programming one column by columns, then programming the next column from the beginning; and in the verification stage, when the read value is consistent with the value to be programmed, judging that the programming is correct, and programming the next value, otherwise, repeating programming the value.

Further, in the step 3, the programming phase is also divided into two phases of long programming and short programming (in the present invention, the long programming period is referred to as long programming, the short programming period is referred to as short programming), the first programming adopts long programming, the programming time is set according to the target value, the device is programmed to the vicinity of the target value, and when the error is verified, the short programming mode is used, the programming time is shorter to approach the target value, so as to prevent the over programming.

Further, both step 2 and step 3 have an erroneous jump-out mechanism. When the programming time exceeds a preset threshold value, the actual value of the device still does not reach the preset value, the programming is considered to fail, error information is saved or output, the programming is skipped, and the next programming is continued.

The invention also provides a memory integrated chip, which comprises a controller; the controller performs the steps of the programming method of the present invention when performing programming control.

In one embodiment, in the integrated memory chip, the gate of each row in the array is connected to a WL (Word Line, WL) end, the Source of each column is connected to a SL (Source Line, SL) end, and the drain of each column is connected to a BL (Bit Line, BL) end. And when programming, starting WL, BL and SL corresponding to the photoelectric memory integrated device, keeping the WL and SL corresponding to the device unchanged during verification, and reading out the result at the SL end through the ADC.

The present invention also provides a computer readable storage medium having a program stored thereon, which when executed by a processor, implements the steps of the method for programming a memory integrated chip of the present invention.

The invention also provides a programming system for the memory integrated chip, which is used for realizing the programming method for the memory integrated chip; the programming system includes: a 0-value position information acquisition module, a 0-value programming module and a non-0-value programming module; the position information acquisition module of 0 value acquires the position information of which the element in the matrix of the needed path is 0 value; the 0 value programming module is used for programming 0 based on the 0 value position information acquired by the 0 value position information acquisition module; and the non-0 value programming module is used for programming other values in the matrix to be programmed after receiving the signal of finishing 0 value programming.

In one embodiment, the 0-value programming module comprises a judging module, a programming module and a checking module; the judging module is used for realizing the judgment and the jump of the 0 value, directly skipping the column without the 0 value and judging the next column until the column with the 0 value appears, and triggering the programming module; the programming module is used for programming the 0 position matrix based on the received 0 value signal of the judging module, and programming the 0 value of an entire column at each time; and the verification module reads out a row of calculation results of the integrated chip.

The invention has the following beneficial effects:

the invention fully considers the characteristics of large 0 value programming difficulty and excessive programming resistance of the integrated memory device, separately programs the 0 value and other values, programs the 0 value in a whole column at a time according to the whole column programming mode, and reduces the verification times to one column for verification only once in each programming according to the characteristic that the 0 value result is accumulated to 0, thereby greatly shortening the programming time of the 0 value, further shortening the programming time of the whole matrix, and having great advantages compared with the existing programming mode aiming at the integrated memory chip.

Drawings

FIG. 1 is a block diagram of a multi-functional region of a computing unit in an embodiment of the invention.

FIG. 2 is a block diagram of a memory chip according to an embodiment of the present invention.

FIG. 3 is a general flow chart of a fast programming method of the present invention.

FIG. 4 is a 0 value programming flow chart.

FIG. 5 is a non-0 value programming flow chart.

Fig. 6 is a memory integrated chip diagram.

Fig. 7 is a generic test verification platform for a chip.

Fig. 8 is a matrix to be programmed.

Detailed Description

The technical scheme of the invention is further described in detail below with reference to the attached drawings and specific embodiments.

Example 1

The embodiment adopts a photoelectric calculation integrated unit, the structure of which is shown in figure 1, and three functional areas are as follows: a carrier control region, a coupling region, a photogenerated carrier collection region, and a readout region. The carrier control region is used for controlling and modulating carriers in the photogenerated carrier collecting region and the readout region; the collecting areas in the photo-generated carrier collecting area and the reading area are used for absorbing photons emitted by the light emitting unit and collecting generated photo-generated carriers; the carrier control region or the photo-generated carrier collection region and the readout region are connected with the electric signal, and the readout region is used for outputting carriers acted by the photo-generated carriers and the electric signal; the coupling region connects the collection region and the readout region.

The integrated memory chip structure of this embodiment is shown in fig. 2, where the gate of each row in the array is connected to the WL end, the source of each column is connected to the SL end, and the drain of each column is connected to the BL end. And when programming, starting WL, BL and SL corresponding to the photoelectric memory integrated device, keeping the WL and SL corresponding to the device unchanged during verification, and reading out the result at the SL end through the ADC.

In this embodiment, a 512×256 matrix is programmed on a memory integrated chip, and the flow is as shown in fig. 3, and the specific process implemented by the method is as follows.

First, the location information of all 0 s in the 512×256 matrix is acquired, and in this embodiment, a program is written to implement the function in an off-chip implementation manner. And judging each element in the matrix in turn, when the element is 0, marking the judgment result as 1, storing the judgment result in a new matrix, and when the element in the matrix is not 0, marking the judgment result as 0, and storing the judgment result in the matrix. In this way a 0 position matrix of 512 x 256 matrices is obtained.

Programming of the 0 value is then started, the flow of which is shown in fig. 4. Inputting first column data of a 0-position matrix, judging whether the first column is all 0, if not, indicating that the first column needs to be programmed with 0 value, and entering a programming mode; if the number of the columns is 0, indicating that the column has no 0 value, sending a data reading request, inputting the next column of the 0-position matrix again, adding one to the numerical value of the programmed column, keeping the same with the number of the columns of the input data until the column is judged to be not 0, and starting programming of the column.

In the programming stage of 0 value, BL and SL corresponding to the row to be programmed are both started, the input data of the 0-position matrix is WL on signal, WL corresponding to 1 is started, WL corresponding to 0 is closed, and the memory integrated chip to be programmed is polished for optical programming (or directly electrical programming). Since there is no over-programmed condition for the 0 value, the first programming is for a longer time, which is determined by the specific device test conditions. And after programming is finished, entering a verification mode, and verifying whether programming is finished. In the verify mode, WL and SL are unchanged, BL for the column is turned off, current is accumulated on SL, and the result is read out by ADC. Since the sum of 0 is still 0, if the ADC readout result is 0, which indicates that the programming of the present column is finished, a read data request is sent out, and the programming of the 0 value of the next column is started; if the result is not 0, it indicates that the programming time is insufficient, the column needs to be programmed again, this programming is a fine tuning process, the programming is not needed for a long time, and a shorter time is determined according to the experimental result.

The device may be damaged and cannot be programmed to a value of 0, an exit mechanism is set to prevent the programming card from being in a damaged column, each time the verification error can enter the next short programming, when the programming times exceed the threshold value, the programming of the column is exited, error information is saved, and the programming of the next column is started. When the programming column counts to the last column and checks correctly (or the programming frequency of the current column exceeds the upper limit), the programming of the 0 value of the whole matrix is considered to be finished, and a 0 value programming finishing signal is output.

After programming of the 0 value, programming of the non-0 value is started, and the flow is shown in fig. 5, wherein the non-programming includes programming by columns and programming by rows, and the embodiment adopts a mode of programming by rows. Firstly, inputting a value of a first row and a first column in a 512 x 256 matrix, judging whether the value is a non-0 value, and entering a programming mode if the value is the non-0 value; if the value is 0, the value is skipped directly because the 0 value is programmed, a data reading request is sent, the next value of the current row is input again for the last value of the non-row, meanwhile, the number of columns to be programmed is increased by one, the number of rows is unchanged, the first value of the next row is input for the last value of the row, the number of columns to be programmed is changed to one, the number of rows is increased by one, and the programming of the value is started until the data is judged to be not 0. If the determined data is that the last value of the last row in the 512×256 matrix is 0, the programming mode is not entered, the programming is directly considered to be completed, and a programming end signal is output.

The non-0 value programs only one device at a time, and each time programming, the corresponding BL, SL, WL of the device is turned on and the light is shined for optical programming (or directly for electrical programming). Programming for a long time for the first time, wherein the time calculation formula is as follows:

。

w is a value to be programmed, and u is obtained from an actual experimental result and is slightly less than the time for the programming of the device to drop by 1. After the first programming is finished, a verification mode is entered, WL and SL are unchanged, corresponding BL is closed, and the result is read out through an ADC. If the read result is consistent with the value to be programmed, programming of the next device is carried out, and if the read result is inconsistent with the value to be programmed, the device needs to be programmed again, so as to prevent over programming, and then programming is carried out for a short time each time. The method also comprises a step of exiting the programming of the device when the programming times exceed the threshold value, saving error information, starting programming of the next device, wherein the exiting threshold value of non-0 value programming is possibly different from the exiting threshold value of 0 value programming, and the result is obtained by specific experimental results.

When the programming of the last device of the last row is finished (the verification is successful or the programming times exceed the upper limit), the whole matrix programming is finished, and a programming finishing signal is output. Since 0-value programming does not need to worry about over-programming, the first programming time can be extended, the number of subsequent checks can be reduced, and a single device can be programmed to achieve a K-fold acceleration (K > 1). By using the programming method of the present invention, the acceleration ratio of 512×k (the matrix to be programmed is all 0) can be obtained at the highest speed in this embodiment.

For an n×m integrated memory chip, up to n×k speed-up ratios can be obtained, and the more 0 values, the larger the speed-up ratio. Compared with the programming technology used in the prior literature report (Wan W, kubendor R, schaefer C, et al A computer-in-memory chip based on resistive random-access memory [ J ]. Nature, 2022, 608 (7923): 504-512 ]), the programming efficiency of 0 can be greatly accelerated without increasing the additional ADC cost. Considering that the neural network generally has higher sparseness, the invention greatly improves the time for the AI application to be deployed on the memory integrated chip.

Example 2

A memory integrated chip comprises a controller; the controller performs the steps of the programming method of fig. 3-4 of the present invention when programmed.

Alternatively, the chip is a photovoltaics integrated unit-based chip (OPU), as shown in fig. 6, which can be used to test the acceleration of the fast programming method of the present patent. Optionally, the chip is composed of 512×256 devices, and can support storing 512×256×8bit data at maximum.

Example 3

A programming system for a memory integrated chip is used for realizing the programming method of the invention.

The programming system comprises a 0-value position information acquisition module, a 0-value programming module and a non-0-value programming module;

the 0-value position information acquisition module acquires position information with 0 value of elements in a matrix of a needed path;

the 0 value programming module is used for programming 0 based on the 0 value position information acquired by the 0 value position information acquisition module;

and the non-0 value programming module is used for programming other values in the matrix to be programmed after receiving the signal of finishing 0 value programming.

Further, the 0-value programming module comprises a judging module, a programming module and a checking module; the judging module is used for realizing the judgment and the jump of the 0 value, directly skipping the column without the 0 value and judging the next column until the column with the 0 value appears, and triggering the programming module; the programming module is used for programming the 0 position matrix based on the received 0 value signal of the judging module, and programming the 0 value of an entire column at each time; and the verification module reads out a row of calculation results of the integrated chip.

Optionally, as shown in fig. 7, the general test verification platform of the chip is a general test verification platform of the chip, wherein a 0-value position information acquisition module is deployed in an upper computer, and a 0-value programming module and a non-0-value programming module are deployed in the FPGA.

Example 4

With the programming method of fig. 3-5 of the present invention, a 256×256 identity matrix is programmed (the values on the main diagonal are all 1, as shown in fig. 8), and the initial value of all devices of the chip is 255. The programming time and the verification time of the non-0 programming module are both set to 50us, the programming time of the 0 programming module is set to 50 x 255us, and the verification time is set to 50us.

The non-zero value time is unchanged using the fast programming method of the present invention, requiring 50 x 256us time to program a 0 value alone, which is 1.99 times faster than if the 0 value was programmed without the method of the present invention (2 x 50 x 255 us).

Since the matrix to be programmed has 256 columns in total, each column has only one non-0 value, namely 255 0 values in each column, the method of the invention is used for programming the 0 values 255 times 1.99= 507.45 times faster, and the speed is 507.45 times 255/256= 505.46 times faster for the whole matrix.

Example 5

The OPU chip generic test verification platform of fig. 7 is used in this embodiment for programming work.

In this embodiment, matlab is used to randomly generate a 512×256 matrix, where the 0 value in the generated matrix accounts for 50% and the initial value of all devices in the chip is 255. The programming time and the verification time of the non-0 programming module are both set to 50us, the programming time of the 0 programming module is set to 50 x 255us, and the verification time is set to 50us.

The 0 value is programmed using the fast programming method of the present invention (as shown in fig. 3-5) to average a speed ratio of 1.99 x 512 x 50% = 509 times. The programming result of the chip is read out and compared with the matrix to be programmed, and the numerical value is consistent.

The present invention is not limited to the above specific embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. The quick programming method for the integrated memory chip is characterized by comprising the following steps of:

extracting the position information of 0 in the matrix to be programmed; programming on the memory integrated chip according to the position information of 0 in a whole-column programming mode; programming a non-0 value on the memory integrated chip;

the method specifically comprises the following steps:

step 2, programming a value of 0; inputting the position information of 0, programming the 0 according to the position information of 0, programming the 0 in a column programming mode in the process of programming the 0 value, directly programming the 0 on a whole column in a matrix on an integrated memory chip, outputting a result of current accumulation when all devices with 0 in the whole column are opened to be 0, considering that programming is finished, and programming the next column until the 0 value in the whole matrix is programmed; wherein, the output result is 0, which allows a certain error;

step 3, programming a non-0 value; inputting a matrix to be programmed, and starting programming other values of the matrix; the programming of the next value is skipped directly when a value of 0 is encountered in step 3.

2. The method according to claim 1, wherein in the step 1, the method for obtaining the position information of the matrix 0 to be programmed is: and taking a null matrix corresponding to the matrix to be programmed, setting the position corresponding to 0 as 1, setting the position corresponding to the non-0 value as 0, obtaining a 0-position matrix, and storing.

3. The method according to claim 1, wherein in step 2, the programming for a value of 0 includes three phases of judging, programming and verifying; in the judging stage, for the column without 0 value, directly skipping the column and judging the next column until the column with 0 value appears, and entering the programming stage; in the programming stage, programming is carried out according to the 0 position matrix obtained in the step 1, and programming is carried out on the 0 value of an entire column at each time; in the verification stage, reading out a row of calculation results of the integrated memory chip; the 0 values of the entire matrix are programmed until all 0 values have been programmed.

4. The method of claim 1, wherein the programming in step 2 comprises two modes, the two modes differing only in programming duration; in the two modes, the relative programming time is long and the relative programming time is short; programming for the first time, programming for a long time according to the actual measurement result of programming the chip device to 0, starting verification, entering programming of the next value if verification passes, and performing short programming if verification does not pass, so that the device to be programmed further approaches to the 0 value.

5. The method according to claim 1, wherein in step 3, the programming for non-0 values comprises three phases: pre-judging, programming and checking; in the pre-judging stage, judging whether the value to be programmed is 0, if so, skipping over the value to be programmed, updating the position of the value to be programmed, judging the next value until the value to be programmed is a non-0 value, and entering the programming stage; the programming stage adopts a mode of programming a single device one by one, comprising programming one by rows and programming one by columns, programming one by rows, then programming the next row from the beginning, programming one column by columns, then programming the next column from the beginning; and in the verification stage, when the read value is consistent with the value to be programmed, judging that the programming is correct, and programming the next value, otherwise, repeatedly programming the value to be programmed.

6. The method of any one of claims 1-5, wherein both step 2 and step 3 have a false pop-out mechanism.

7. A memory integrated chip or computer readable storage medium comprising a controller for performing programming control or a storage medium storing a programming program, the controller being capable of implementing the steps of the programming method of any one of claims 1-6 when the controller performs programming control or the programming program is executed by a processor.

8. A programming system for a memory integrated chip, for implementing the programming method of any one of claims 1-6, wherein the programming system includes a 0 value location information acquisition module, a 0 value programming module, and a non-0 value programming module; the position information acquisition module of 0 value acquires the position information of which the element in the matrix of the needed path is 0 value; the 0 value programming module is used for programming 0 based on the 0 value position information acquired by the 0 value position information acquisition module; and the non-0 value programming module is used for programming other values in the matrix to be programmed after receiving the signal of finishing 0 value programming.