CN116032813A

CN116032813A - Communication module testing method and device, electronic equipment and storage medium

Info

Publication number: CN116032813A
Application number: CN202211713343.3A
Authority: CN
Inventors: 张贝; 徐廷松; 杨涛; 陈锦; 钟明
Original assignee: Longsung Technology Shanghai Co ltd
Current assignee: Longsung Technology Shanghai Co ltd
Priority date: 2022-12-29
Filing date: 2022-12-29
Publication date: 2023-04-28
Anticipated expiration: 2042-12-29
Also published as: CN116032813B

Abstract

The invention discloses a communication module testing method, a device, electronic equipment and a storage medium, wherein the method comprises the following steps: controlling the high-level output pins to output high-level signals and controlling the output pins different from the high-level output pins to output low-level signals in response to the test instruction; reading corresponding level signals, and determining a test variable value based on each level signal; updating the test array based on the test variable values and the corresponding preset correct variable values; and taking an output pin adjacent to the high-level output pin as the high-level output pin, repeatedly executing the output level signals, determining a single test result and updating the test array until the high-level output pin is the last output pin, obtaining a target test array, and determining the test result based on the target test array so as to process the communication module to be tested based on the test result. The technical scheme of the embodiment realizes the effects of reducing the test cost and saving the test time.

Description

Communication module testing method and device, electronic equipment and storage medium

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method and apparatus for testing a communication module, an electronic device, and a storage medium.

Background

With the continuous expansion and enrichment of functions, a plurality of embedded products, such as 5G communication modules and the like, integrate various communication interfaces, such as I2C, SPI, UART, SDIO and the like. The engineering test complexity is also increasing during production.

At present, a conventional engineering test scheme is generally aimed at connecting a specific external device to the same communication interface, when a 5G communication module is powered on and started, the external device of the communication interface to be tested is initialized by initializing the communication interface to be tested, then the 5G communication module reads information in the external device through the communication interface, and whether the communication interface is normal is tested by judging whether the read information accords with expected information or not.

However, the 5G communication module integrates a plurality of different communication interfaces, each communication interface needs to be connected with respective external devices during testing, and the connected external devices need respective working conditions, so that during testing, materials such as the external devices of various communication interfaces and respective matched power supply circuits need to be prepared, and testing cost is increased; moreover, the different communication interfaces need to sequentially execute the testing steps to check whether the communication interfaces are normal or not, so that the testing efficiency is seriously affected.

Disclosure of Invention

The invention provides a communication module testing method, a device, electronic equipment and a storage medium, which are used for realizing the effects of reducing the testing cost and saving the testing time, and simultaneously realizing the effects of carrying out fault positioning and repairing on a communication module to be tested, which fails to test, while testing the communication module to be tested.

According to an aspect of the present invention, there is provided a communication module testing method, the method comprising:

determining a high-level output pin from at least one predetermined output pin corresponding to a communication module to be tested in response to a test instruction corresponding to the communication module to be tested, controlling the high-level output pin to output a high-level signal, and controlling each output pin different from the high-level output pin to output a low-level signal;

reading corresponding level signals based on an input pin connected with the at least one output pin, and determining a test variable value based on each of the level signals; the output pins are connected with the connected input pins through resistance elements with preset resistance values;

determining a single test result based on the test variable value and a corresponding preset correct variable value, and updating a preset value corresponding to the single test result into a pre-constructed test array; wherein the preset correct variable value corresponds to the number of test cycles;

And taking an output pin adjacent to the high-level output pin as a high-level output pin, repeatedly executing output level signals, determining a single test result and updating a test array until the high-level output pin is the last output pin in the communication module to be tested, obtaining a target test array, determining a test result corresponding to the communication module to be tested based on the target test array, and processing the communication module to be tested based on the test result.

According to another aspect of the present invention, there is provided a communication module testing apparatus comprising

A test instruction response module, configured to determine a high-level output pin from at least one predetermined output pin corresponding to a to-be-tested communication module in response to a test instruction corresponding to the to-be-tested communication module, control the high-level output pin to output a high-level signal, and control each output pin different from the high-level output pin to output a low-level signal;

the test variable value determining module is used for reading corresponding level signals based on an input pin connected with the at least one output pin and determining a test variable value based on each level signal; the output pins are connected with the connected input pins through resistance elements with preset resistance values;

The single test result determining module is used for determining a single test result based on the test variable value and the corresponding preset correct variable value and updating the preset value corresponding to the single test result into a pre-constructed test array; wherein the preset correct variable value corresponds to the number of test cycles;

and the target test array determining module is used for taking an output pin adjacent to the high-level output pin as a high-level output pin, repeatedly executing output level signals, determining a single test result and updating the test array until the high-level output pin is the last output pin in the communication module to be tested, obtaining a target test array, determining a test result corresponding to the communication module to be tested based on the target test array, and processing the communication module to be tested based on the test result.

According to another aspect of the present invention, there is provided an electronic apparatus including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the communication module testing method according to any one of the embodiments of the present invention.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute a method for testing a communication module according to any one of the embodiments of the present invention.

According to the technical scheme, a high-level output pin is determined from at least one predetermined output pin corresponding to a communication module to be tested through responding to a test instruction corresponding to the communication module to be tested, the high-level output pin is controlled to output a high-level signal, each output pin different from the high-level output pin is controlled to output a low-level signal, then, based on an input pin connected with at least one output pin, the corresponding level signal is read, and based on each level signal, a test variable value is determined, further, based on the test variable value and the corresponding preset correct variable value, a single test result is determined, a preset numerical value corresponding to the single test result is updated into a pre-built test array, finally, an output pin adjacent to the high-level output pin is used as the high-level output pin, the steps of outputting the high-level signal and updating the test array are repeated until the high-level output pin is the last output pin in the communication module to be tested, a target test array is obtained, the test result corresponding to the communication module to be tested is determined, so that the communication module to be tested is processed based on the test result, the power supply cost of each communication module to be tested is increased, and the external equipment is required to be matched with the test equipment; and the different communication interfaces all need to execute the test steps in sequence to check whether the communication interfaces are normal or not, so that the problems of seriously influencing the test efficiency and the like are solved, the effects of reducing the test cost and saving the test time are realized, and meanwhile, the effects of positioning and repairing faults of the communication module to be tested, which fails in the test, are realized while the communication module to be tested is tested.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a method for testing a communication module according to a first embodiment of the present invention;

fig. 2 is a schematic diagram of a communication module to be tested according to a first embodiment of the present invention;

fig. 3 is a schematic diagram of a power-on and power-on process of a communication module to be tested according to a first embodiment of the present invention;

fig. 4 is a schematic structural diagram of a communication module testing device according to a second embodiment of the present invention;

fig. 5 is a schematic structural diagram of an electronic device implementing a method for testing a communication module according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example 1

Fig. 1 is a flowchart of a communication module testing method according to an embodiment of the present invention, where the method may be applied to a case of testing a communication module integrated with a plurality of communication interfaces without connecting to an external device, and the method may be performed by a communication module testing device, and the communication module testing device may be implemented in a form of hardware and/or software, and the communication module testing device may be configured in a terminal and/or a server. As shown in fig. 1, the method includes:

s110, responding to a test instruction corresponding to the communication module to be tested, determining a high-level output pin from at least one predetermined output pin corresponding to the communication module to be tested, controlling the high-level output pin to output a high-level signal, and controlling each output pin different from the high-level output pin to output a low-level signal.

In this embodiment, the communication module to be tested may be a communication module that needs to perform communication interface detection. It should be understood by those skilled in the art that a plurality of communication interfaces may be integrated in the communication module, and before the communication module is manufactured, it may be further detected whether each communication interface may work normally, so that the communication module in which each communication interface may work normally may be applied to each field. The communication module to be tested can be any communication module, and optionally can be a 5G communication module. The test instruction may be a piece of program code, and the program code may execute a communication interface test procedure of the communication module under test. The output pins may be pins whose operation mode is the output mode. Correspondingly, the high-level output pin is a pin for outputting a high-level signal. Those skilled in the art will appreciate that a pin is a connection from an internal circuit of an integrated circuit to a peripheral circuit. In the practical application process, in order to detect the communication function of each communication interface integrated in the communication interface to be detected, peripheral pins can be respectively set for each communication interface, and further, the communication function test condition of the corresponding communication interface can be determined by determining the signal transmission condition among the peripheral pins.

It should be noted that, in order to enable each communication interface to realize a function test process without connecting with a corresponding external device, each peripheral pin to be tested in the communication module to be tested may be connected in pairs, and at least one input pin and at least one output pin are determined based on each peripheral pin to be tested after connection, so that signals output by the output pins may be read based on the connected input pins.

Based on the above, the above technical means further includes: connecting a plurality of peripheral pins to be tested in a communication module to be tested through resistance elements with preset resistance values in pairs to obtain at least one closed loop; and for each closed loop, setting the working mode of one peripheral pin to be tested in the current closed loop as an input mode, and setting the working mode of the other peripheral pin to be tested as an output mode to obtain an input pin and an output pin corresponding to the current closed loop.

In this embodiment, the external pins to be tested may be wires led out from each communication interface to be tested in the communication module to be tested. The preset resistance may be any resistance, and optionally, may be one kiloohm. The closed loop may be a circuit that is connected and that can function properly, while the circuit must include a resistor.

It should be noted that when the plurality of peripheral pins to be tested are connected in pairs, any two peripheral pins to be tested may be connected in pairs, and in this embodiment, two adjacent peripheral pins to be tested may be connected in pairs, and other connection manners may be further included, which is not limited in this embodiment.

In the practical application process, after the to-be-tested communication module comprising a plurality of to-be-tested peripheral pins is obtained, each to-be-tested peripheral pin can be connected in pairs through a resistor element with a preset resistance value, and then at least one closed loop can be obtained.

It should be noted that, in order to avoid the situation that the pins of the peripheral to be tested are damaged in the testing process, the pins of the peripheral to be tested may be grounded to the TVS diode.

As shown in fig. 2, an example may be taken as a 5G communication module as an to-be-tested communication module, where the 5G communication module includes four types of communication interfaces including an I2C, UART, SPI and an SDIO, each communication interface includes a corresponding peripheral pin to be tested, each peripheral pin to be tested may be grounded to a TVS diode, and two adjacent peripheral pins to be tested may be connected by a resistor of one kiloohm, so as to obtain a closed loop 1, a closed loop 2, a closed loop 3, a closed loop 4, a closed loop 5, a closed loop 6 and a closed loop 7, and further, an operation mode of one of the peripheral pins to be tested in each closed loop may be set to an input mode, that is, an input pin 1, an input pin 2, an input pin 3, an input pin 4, an input pin 6 and an input pin 7 may be obtained, and an operation mode of the other peripheral pin to be set to be an output mode, that is, an output pin 1, an output pin 2, an output pin 3, an output pin 4, an output pin 5, an output pin 6 and an output pin 7 may be obtained.

In a specific implementation, after determining at least one output pin and at least one input pin corresponding to the communication module to be tested, the communication module to be tested can be tested. In order to perform the same test on the input pins and the output pins in each closed loop, the number corresponding to the number of the closed loops can be used as the number of times of the cyclic test, and in each cyclic test, only one output pin outputs a high-level signal, the other output pins output low-level signals, and when the number of times of the cyclic test reaches the number corresponding to the number of the closed loops, the test process of the communication module to be tested can be completed.

Optionally, in response to a test instruction corresponding to the communication module to be tested, determining a high-level output pin from at least one predetermined output pin corresponding to the communication module to be tested, including: when the test instruction is received, a test cycle number variable and an output cycle number variable are determined based on the test instruction, and a high-level output pin is determined based on the test cycle number variable and the output cycle number variable.

In this embodiment, the test cycle number variable may be a variable for controlling the number of cycles in the test instruction, and the test cycle number variable is added by 1 every time a cycle. The test cycle number variable corresponds to the number of closed loops. For example, when the number of closed loops is 7, the test cycle number variable is 0,1,2,3,4,5,6. The output cycle number variable may be a variable in the test instruction that is used to control the output pin cycle number. The number of output cycles variable is the same as the number of test cycles variable, and the corresponding function in the test instruction is different.

In a specific implementation, when a test instruction corresponding to a communication module to be tested is received, the test instruction can be analyzed to obtain a test cycle number variable and an output cycle number variable, and further, a high-level output pin for outputting a high-level signal and other output pins for outputting a low-level signal can be determined by comparing the test cycle number variable with the output cycle number variable.

Optionally, determining the high level output pin based on the test cycle number variable and the output cycle number variable includes: when the output cycle number variable is smaller than the total number of output pins and the output cycle number variable is equal to the test cycle number variable, determining a target output pin sequence number which is the same as the output cycle number variable from the predetermined output pin sequence numbers, and taking the output pin corresponding to the target output pin sequence number as a high-level output pin.

In this embodiment, the output pin sequence number may be a number set in advance for each output pin. Alternatively, the serial number of the output pins may be a serial number determined according to the arrangement sequence of the output pins in the communication module to be tested, or may be a serial number set by the user for each output pin randomly based on own will, which is not specifically limited in this embodiment. For example, with continued reference to fig. 2, the output pins may be arranged in a top-to-bottom order and corresponding output pin numbers may be set, i.e., output pin 1, output pin 2, output pin 3, output pin 4, output pin 5, output pin 6, and output pin 7.

In a specific implementation, after the test cycle number variable and the output cycle number variable are obtained, it may be determined first whether the output cycle number variable is smaller than the total number of output pins, if so, it may be determined whether the output cycle number variable is equal to the test cycle number variable, and if so, it may be determined from the output pin serial numbers that the output cycle number variable is the same, and the output pin serial number is used as a target output pin serial number, and further, an output pin corresponding to the target output pin serial number is used as a high-level output pin. The advantages of this arrangement are that: only one high-level output pin is arranged in each output pin in each cycle test process, the other output pins are pins for outputting low-level signals, and the serial numbers of the high-level output pins in each cycle test process are the same as the current times of test cycles.

It should be noted that, in each cycle process, if the output cycle number variable is not equal to the test cycle number variable, the output pin corresponding to the output cycle number variable may be controlled to output a low level signal; if the output cycle number variable is not less than the total number of output pins, the cycle is jumped out.

By way of example, the level signal output of each output pin may be described based on the following execution logic: 1. determining a test cycle number variable con=0 and outputting a cycle number variable num=0; 2. determining whether num (0) is smaller than the total number total (7) of output pins, if so, executing the step 3, and if not, jumping out of the loop; 3. determining whether num (0) is equal to con (0), if so, enabling a num (0) output pin in each output pin to be a high-level output pin, and otherwise enabling a num (0) output pin in each output pin to be an output pin for outputting a low-level signal; 4. num (0) plus 1 is then num (1); 5. if num (1) is smaller than total (7), executing step 6 if so, and jumping out of the loop if not; 6. if num (1) is equal to con (0), outputting a high level by the num (1) th output pin in each output pin, and if not, outputting a low level signal by the num (1) th output pin in each output pin; 7. cycling until num (6) plus 1 is then num (7); 8. if num (7) is smaller than total (7), if so, the execution is continued, and if not, the loop is jumped out.

S120, based on an input pin connected with at least one output pin, sequentially reading corresponding level signals according to a preset reading sequence, so as to determine a test variable value based on each level signal.

In this embodiment, the input pins are to-be-tested peripheral pins whose operation mode is the input mode. Wherein, each pair of input pins and output pins which are connected through a resistance element with preset resistance value. The level signals include a high level signal and a low level signal. The preset reading sequence may be preset, and the reading sequence corresponding to reading the signals of each level. The preset reading sequence may be any sequence, and optionally, may be an arrangement sequence of the input pins on the communication module to be tested, that is, a sequence corresponding to the serial numbers of the output pins. The test variable value may be a value used in each cycle to characterize the level signal output of the respective output pin for that cycle.

In the practical application process, when each output pin in the communication module to be tested completes one output cycle, that is, after each output pin outputs one level signal, the corresponding level signal can be read based on the input pin connected with each output pin, specifically, based on the input pin connected with the high level output pin, the high level signal can be read, based on the input pin connected with each output pin outputting the low level signal, the low level signal can be read, when the level signal is read, the corresponding level signal can be sequentially read according to the preset level signal reading sequence, after each level signal is read, one level signal is processed, the next level signal is read, and the cycle is sequentially performed until the last level signal is read, and the test variable value is obtained.

Optionally, based on an input pin connected to at least one output pin, sequentially reading corresponding level signals according to a preset reading sequence, so as to determine a test variable value based on each level signal, including: determining a first input pin according to a preset reading sequence and a preset input pin sequence number, reading a level signal corresponding to the first input pin, determining an initial variable value corresponding to a numerical storage variable based on a test instruction, updating the initial variable value based on a preset numerical value corresponding to the level signal and an input pin sequence number corresponding to the first input pin to obtain a variable value to be processed, and taking the variable value to be processed as an initial variable value of a next input pin of the first input pin; determining the next input pin of the first input pin, and repeating the steps of level signal reading and initial variable value updating until the next input pin is the last input pin, and taking the variable value to be processed corresponding to the last input pin as a test variable value.

In this embodiment, the input pin number may be a number set in advance for each input pin. Optionally, the serial number of the input pin may be a serial number determined according to the arrangement sequence of the input pins in the to-be-tested communication module, or may be a serial number set by the user for each input pin randomly based on own will, which is not specifically limited in this embodiment. Illustratively, with continued reference to FIG. 2, the input pins may be arranged in a top-to-bottom order and the corresponding input pin numbers, i.e., input pin 1, input pin 2, input pin 3, input pin 4, input pin 5, input pin 6, and input pin 7, may be set. The preset value may be a value preset to characterize the high level signal or the low level signal, i.e., the preset value may be divided into a high level preset value corresponding to the high level signal and a low level preset value corresponding to the low level signal. Alternatively, the high level preset value may be 1, and the low level preset value may be 0. The numerical storage variables may be predefined variables used in the test instructions to store values read from the respective input interfaces. The initial variable value may be the value to which the value storage variable corresponds after initialization, and typically the initial variable value is 0.

In a specific implementation, the input pin serial number of each input pin can be determined first, then, the input pin serial number at the first position in each input pin serial number is determined according to a preset reading sequence, the input pin corresponding to the input pin serial number is used as the first input pin, then, a level signal corresponding to the first input pin is read, when a test instruction is received, a value storage variable in the test instruction is obtained through analyzing the result of the test instruction, an initial variable value of the value storage variable is determined, further, the preset value corresponding to the level signal, the input pin serial number of the first input pin and the initial variable value are subjected to operation processing, and a variable value to be processed can be obtained, and at this time, the variable value to be processed can be used as the initial variable value of the next input pin of the first input pin.

Optionally, determining the variable value to be processed based on the preset value corresponding to the level signal, the input pin serial number corresponding to the first input pin, and the initial variable value includes: determining a binary number corresponding to a preset numerical value, and shifting the binary number left by the number of digits identical to the serial number of an input pin to obtain a binary number to be processed; converting the initial variable value into binary numbers according to the number of bits of the binary numbers to be processed to obtain initial binary numbers, and performing OR operation on the initial binary numbers and the binary numbers to be processed according to the bits to obtain binary numbers to be applied; and converting the binary number to be applied into a decimal number to obtain a variable value to be processed.

In this embodiment, the binary number is a number represented by two numbers, 0 and 1, and the corresponding carry criterion is "every two-in-one", and the borrowing rule is "every two-out-one". For example, if the preset value is 0, the corresponding binary number is 000000000; if the preset value is 1, the corresponding binary number is 00000001. Correspondingly, a decimal number is a digital system with a composition based on 10, and has ten basic digital compositions of 0,1,2,3,4,5,6,7,8 and 9. The number of bits may be the number of characters in the corresponding binary number.

In a specific implementation, after determining a preset value corresponding to the level signal, the preset value may be converted into a corresponding binary number, then the binary number is shifted to the left by a number of digits identical to the serial number of the input pin of the corresponding input pin, so as to obtain a binary number to be processed, further, the number of digits of the binary number to be processed is determined, the initial variable value is converted into a binary number with the same number as the binary number to be processed, so as to obtain an initial binary number, then the initial binary number and the binary number to be processed are subjected to OR operation in sequence, at this time, the result after operation may be used as a binary number to be applied, and finally, the binary number to be applied is converted into a decimal number, so as to obtain the variable value to be processed.

Further, the variable value to be processed is used as the initial variable value of the next input pin, the next input pin of the first input pin is determined, the steps of reading the level signal and determining the variable value to be processed are repeatedly executed until the next input pin is the last input pin, and then the variable value to be processed corresponding to the last input pin can be used as the test variable value.

By way of example, the determination of test variable values may be described based on the following execution logic: 1. defining a variable corresponding to the first input pin as num=0, and storing an initial variable value of the variable as value=0; 2. determining whether num (0) is smaller than total (7), if so, executing step 3, and if not, jumping out of the loop; 3. reading the level signal of a num (0) th input pin of the input pins, referring to the example in S110, the level signal of the 0 th input pin is a high level signal, and determining a preset value corresponding to the high level signal to be 1; 5. converting 1 into a binary number 00000001, and shifting the binary number left by num bits, that is, shifting left by 0 bits, at which time the binary number to be processed is 00000001; 6. converting the value into a binary number 00000000, and performing OR operation on the binary number to be processed and the value, namely performing OR operation on 00000001 and 00000000, so that the binary number to be applied can be obtained to be 00000001, the binary number to be applied is converted into a decimal number, namely obtaining a variable value to be processed to be 1, and the variable value to be processed is taken as an initial variable value of a next input pin, namely, the value=1 of the next input pin; 7. num (0) plus 1 is then num (1); 8. if num (1) is smaller than total (8), executing step 9 if yes, and jumping out of the loop if no; 9. reading a level signal of a num (1) th GPIO in each input pin, referring to an example in S110, the level signal of the 1 st input pin is a low level signal, and determining a preset value corresponding to the low level signal to be 0; 10. converting 0 into a binary number 00000000, and shifting the binary number left by num bits, i.e., shifting left by 1 bit, at which time the binary number to be processed is 00000000; 11. converting the value into a binary number 00000001, and performing OR operation on the binary number to be processed and the value, namely performing OR operation on 00000000 and 00000001, so that the binary number to be applied can be obtained to be 00000001, and the binary number to be applied is converted into a decimal number, and the variable value to be processed can be obtained to be 1; 12. num (1) plus 1 is then num (2); 13. cycling until num (6) plus 1 is then num (7); 14. if num (7) is smaller than total (7), if so, the execution is continued, and if not, the loop is jumped out, and at this time, a test variable value value=1 is finally obtained.

S130, determining a single test result based on the test variable value and the preset correct variable value, and updating a preset test value corresponding to the single test result into a preset test array.

In this embodiment, the preset correct variable value may be a preset value for determining whether the test variable value obtained after each cycle is correct or not. The single test result may be a test result determined after the single signal output test and the single signal read test. Correspondingly, the preset test value may be a preset value for representing the result of a single test. For example, if the single test result is that the test is successful, the corresponding preset test value is 1; if the single test result is a test failure, the corresponding preset test value is 0. The test array may be a pre-built array for storing values corresponding to a single test result. The size of the test array may be equal to the total number of input pins or the total number of output pins, where the total number of input pins is equal to the total number of output pins, and thus the size of the test array may be equal to the total number of pins of either type. When the test array is constructed, each unit value in the array is 0. For example, if the total number of output pins is 7, the test array is "0,0,0,0,0,0,0".

It should be noted that, the preset correct variable value corresponding to each cycle test may be represented by a decimal number determined after shifting the binary number of 1 by the same number of bits as the current test cycle number variable control. For example, when con=0, the corresponding preset correct variable value may be a number obtained by shifting 00000001 by 0 bits, and then performing decimal conversion, i.e. 1, or may be expressed as a zero power of 2; if the con=1, the corresponding preset correct variable value may be obtained by shifting 00000001 by 1 bit to the left, then obtaining 00000010, and performing decimal conversion to obtain 2, which may also be expressed as the power of 2.

In a specific implementation, after the test variable value is obtained, the test variable value and a preset correct variable value can be compared, if the test variable value is equal to the preset correct variable value, the single test result can be determined to be successful, and if the test variable value is not equal to the preset correct variable value, the single test result can be determined to be failed, further, a preset test value corresponding to the single test result can be determined, and the preset test value is updated to the test array.

For example, when the test variable value is 1 and the preset correct variable value is 1, it may be determined that the single test result is successful, and at this time, the preset test value 1 corresponding to the successful test may be updated to the preset array, so as to obtain the updated preset array as "1,0,0,0,0,0,0".

And S140, taking an output pin adjacent to the high-level output pin as the high-level output pin, repeatedly executing the output level signals, determining a single test result and updating the test array until the high-level output pin is the last output pin in the communication module to be tested, obtaining a target test array, and determining a test result corresponding to the communication module to be tested based on the target test array so as to process the communication module to be tested based on the test result.

In this embodiment, the target test array may be an array obtained by updating a preset test value corresponding to a single test result obtained by a last cycle test after the last cycle process is completed.

In the practical application process, an output pin adjacent to the high-level output pin can be used as the high-level output pin, the high-level output pin is controlled to output a high-level signal, each output pin different from the high-level output pin outputs a low-level signal, then, based on an input pin connected with at least one output pin, a corresponding level signal is read, and based on each level signal, a test variable value is determined, further, a single test result is determined according to the test variable value and the corresponding preset correct variable value, a preset test value corresponding to the single test result is updated into a test array, then, the output pin adjacent to the high-level output pin is used as the high-level output pin, the process is repeatedly executed until the high-level output pin is the last output pin in the communication module to be tested, and after the steps, the obtained test array is used as a target test array.

Further, according to each character included in the target test array, a test result corresponding to the communication module to be tested is determined.

Optionally, determining, based on the target test array, a test result corresponding to the to-be-tested communication module to process the to-be-tested communication module based on the test result, including: determining the number of characters of preset characters in a target test array, and determining whether the number of characters is equal to the total number of input pins; if yes, determining that the test result is successful, determining the module identifier of the communication module to be tested, and correspondingly storing the target test array and the module identifier into a database; if not, determining that the test result is test failure, and sending the target test array to the target terminal, so that the user to which the target terminal belongs analyzes the communication module to be tested based on the target test array.

In this embodiment, the preset characters may be preset characters for characterizing the test result. The preset character may be 1, for example. The target terminal may be a terminal corresponding to a fault troubleshooting, analyzing, or repairing process.

In the implementation, after the target test array is obtained, the number of characters of preset characters in the target test array can be firstly determined, whether the number of characters is equal to the total number of input pins or not is determined, if so, the test result can be determined to be successful, the module identification of the communication module to be tested can be determined, and the module identification and the target test array are correspondingly stored in a database; if not, the target test array can be sent to a target terminal corresponding to the fault checking, analyzing or repairing process, so that a user to which the target terminal belongs can perform fault checking, analyzing or repairing on the communication module to be tested based on information included in the target test array. The advantages of this arrangement are that: the follow-up procedure related personnel can conduct targeted analysis, investigation, repair and other operations on the fault input pins through the detailed information output when the test fails, so that the communication module to be tested can be accurately, rapidly and rapidly maintained.

It should be noted that, before the to-be-tested communication module is tested, a reset signal can be provided for the to-be-tested communication module based on the external chip, so that the to-be-tested communication module can realize the operation of powering on and automatically powering on. For example, as shown in fig. 3, the to-be-tested communication module and the SGM829 chip are respectively connected with the power supply circuit module, and a reset signal is provided for the to-be-tested communication module by using the SGM829 dedicated reset chip, so as to realize the power-on automatic power-on function. After power-on, the chip starts to work, and the reset chip special for SGM829 controls the duration of the reset signal output NRESET pin to output low level by controlling the size of the external capacitor of the RST pin, so that the reset operation is completed. The signal is sent to the POWE_ON pin of the communication module to be tested, and the POWE_ON pin of the communication module to be tested executes the starting action after receiving the reset signal. Further, after the communication module to be tested is started, the test instruction can be responded, and then, the corresponding test flow is executed.

Example two

Fig. 4 is a schematic structural diagram of a communication module testing device according to a second embodiment of the present invention. As shown in fig. 4, the apparatus includes: test instruction response module 210, test variable value determination module 220, single test result determination module 230, and target test array determination module 240.

Wherein, the test instruction response module 210 is configured to determine a high-level output pin from at least one predetermined output pin corresponding to the to-be-tested communication module in response to a test instruction corresponding to the to-be-tested communication module, and control the high-level output pin to output a high-level signal, and control each output pin different from the high-level output pin to output a low-level signal;

a test variable value determining module 220, configured to read corresponding level signals based on an input pin connected to the at least one output pin, and determine a test variable value based on each of the level signals; the output pins are connected with the connected input pins through resistance elements with preset resistance values;

a single test result determining module 230, configured to determine a single test result based on the test variable value and a corresponding preset correct variable value, and update a preset value corresponding to the single test result to a pre-constructed test array; wherein the preset correct variable value corresponds to the number of test cycles;

And the target test array determining module 240 is configured to take an output pin adjacent to the high-level output pin as a high-level output pin, and repeatedly execute the steps of determining a single test result and updating the test array until the high-level output pin is the last output pin in the communication module to be tested, obtain a target test array, determine a test result corresponding to the communication module to be tested based on the target test array, and process the communication module to be tested based on the test result.

Optionally, the apparatus further includes: the system comprises a closed loop determination module and an operation mode setting module.

The closed loop determining module is used for connecting a plurality of peripheral pins to be tested in the communication module to be tested through resistance elements with preset resistance values in pairs to obtain at least one closed loop;

the working mode setting module is used for setting the working mode of one peripheral pin to be tested in the current closed loop as an input mode and setting the working mode of the other peripheral pin to be tested as an output mode for each closed loop to obtain an input pin and an output pin corresponding to the current closed loop.

Optionally, the test instruction response module 210 includes: and a high level output pin determining unit.

And the high-level output pin determining unit is used for determining a test cycle number variable and an output cycle number variable based on the test instruction and determining the high-level output pin based on the test cycle number variable and the output cycle number variable when the test instruction is received.

Optionally, the high-level output pin determining unit is specifically configured to determine, from among predetermined output pin serial numbers, a target output pin serial number that is the same as the output cycle number variable, and use an output pin corresponding to the target output pin serial number as the high-level output pin when the output cycle number variable is smaller than the total number of output pins and the output cycle number variable is equal to the test cycle number variable.

Optionally, the test variable value determining module 220 includes: the variable value to be processed determines the sub-module and the test variable value determines the sub-module.

The to-be-processed variable value determining submodule is used for determining a first input pin according to a preset reading sequence and a preset input pin sequence number, reading a level signal corresponding to the first input pin, determining an initial variable value corresponding to a numerical value storage variable based on the test instruction, determining a to-be-processed variable value based on a preset numerical value corresponding to the level signal, the input pin sequence number corresponding to the first input pin and the initial variable value, and taking the to-be-processed variable value as an initial variable value of a next input pin of the first input pin;

and the test variable value determining submodule is used for determining the next input pin of the first input pin, repeating the steps of level signal reading and variable value determination to be processed until the next input pin is the last input pin, and taking the variable value to be processed corresponding to the last input pin as the test variable value.

Optionally, the variable value to be processed determining submodule includes: the device comprises a binary number determining unit to be processed, a binary number determining unit to be applied and a variable value determining unit to be processed.

The binary number to be processed determining unit is used for determining binary numbers corresponding to the preset numerical values, and shifting the binary numbers to the left by the number of digits identical to the serial numbers of the input pins to obtain binary numbers to be processed;

the binary number to be applied determining unit is used for converting the initial variable value into a binary number according to the bit number of the binary number to be processed to obtain an initial binary number, and performing OR operation on the initial binary number and the binary number to be processed according to the bit number to obtain the binary number to be applied;

and the variable value to be processed determining unit is used for converting the binary number to be applied into a decimal number to obtain the variable value to be processed.

Optionally, the target test array determining module 240 includes: the device comprises a character number determining unit, a target test array storage unit and a target test array transmitting unit.

The character number determining unit is used for determining the character number of preset characters in the target test array and determining whether the character number is equal to the total number of input pins or not;

the target test array storage unit is used for determining that the test result is successful in test if the test result is successful, determining the module identification of the communication module to be tested, and storing the target test array and the module identification into a database correspondingly;

And the target test array sending unit is used for determining that the test result is test failure if not, and sending the target test array to a target terminal so that a user to which the target terminal belongs analyzes the communication module to be tested based on the target test array.

The communication module testing device provided by the embodiment of the invention can execute the communication module testing method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

Example III

Fig. 5 shows a schematic diagram of the structure of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 5, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 may also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the communication module test method.

In some embodiments, the communication module testing method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the communication module testing method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the communication module testing method in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A method for testing a communication module, comprising:

2. The method as recited in claim 1, further comprising:

Connecting a plurality of peripheral pins to be tested in a communication module to be tested through resistance elements with preset resistance values in pairs to obtain at least one closed loop;

and for each closed loop, setting the working mode of one peripheral pin to be tested in the current closed loop as an input mode, and setting the working mode of the other peripheral pin to be tested as an output mode to obtain an input pin and an output pin corresponding to the current closed loop.

3. The method of claim 1, wherein determining a high level output pin from among the predetermined at least one output pin corresponding to the communication module under test in response to the test instruction corresponding to the communication module under test comprises:

and when the test instruction is received, determining a test cycle number variable and an output cycle number variable based on the test instruction, and determining the high-level output pin based on the test cycle number variable and the output cycle number variable.

4. The method of claim 3, wherein the determining the high level output pin based on the test cycle number variable and the output cycle number variable comprises:

And when the output cycle number variable is smaller than the total number of output pins and the output cycle number variable is equal to the test cycle number variable, determining a target output pin sequence number which is the same as the output cycle number variable from the predetermined output pin sequence numbers, and taking an output pin corresponding to the target output pin sequence number as the high-level output pin.

5. The method of claim 1, wherein reading the corresponding level signals in a preset read order based on the input pins connected to the at least one output pin to determine the test variable value based on each level signal, comprises:

determining a first input pin according to a preset reading sequence and a preset input pin sequence number, reading a level signal corresponding to the first input pin, determining an initial variable value corresponding to a numerical storage variable based on the test instruction, determining a variable value to be processed based on a preset numerical value corresponding to the level signal, the input pin sequence number corresponding to the first input pin and the initial variable value, and taking the variable value to be processed as an initial variable value of a next input pin of the first input pin;

And determining the next input pin of the first input pin, and repeating the steps of level signal reading and variable value determination to be processed until the next input pin is the last input pin, and taking the variable value to be processed corresponding to the last input pin as the test variable value.

6. The method of claim 5, wherein the determining the variable value to be processed based on the preset value corresponding to the level signal, the input pin sequence number corresponding to the first input pin, and the initial variable value comprises:

determining a binary number corresponding to the preset numerical value, and shifting the binary number to the left by the number of digits identical to the serial number of the input pin to obtain a binary number to be processed;

converting the initial variable value into binary numbers according to the digits of the binary numbers to be processed to obtain initial binary numbers, and performing OR operation on the initial binary numbers and the binary numbers to be processed according to the digits to obtain binary numbers to be applied;

and converting the binary number to be applied into a decimal number to obtain the variable value to be processed.

7. The method of claim 1, wherein determining a test result corresponding to the communication module under test based on the target test array to process the communication module under test based on the test result comprises:

Determining the number of characters of preset characters in the target test array, and determining whether the number of characters is equal to the total number of input pins;

if yes, determining that the test result is successful, determining a module identifier of the communication module to be tested, and correspondingly storing the target test array and the module identifier into a database;

if not, determining that the test result is test failure, and sending the target test array to a target terminal, so that a user to which the target terminal belongs analyzes the communication module to be tested based on the target test array.

8. A communication module testing apparatus, comprising:

9. An electronic device, the electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the communication module testing method of any one of claims 1-7.

10. A computer readable storage medium storing computer instructions for causing a processor to perform the method of testing a communication module of any one of claims 1-7.