CN116031201A - Method for preparing metal interconnection structure and method for preparing semiconductor device - Google Patents
Method for preparing metal interconnection structure and method for preparing semiconductor device Download PDFInfo
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- CN116031201A CN116031201A CN202111238163.XA CN202111238163A CN116031201A CN 116031201 A CN116031201 A CN 116031201A CN 202111238163 A CN202111238163 A CN 202111238163A CN 116031201 A CN116031201 A CN 116031201A
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Abstract
The invention provides a preparation method of a metal interconnection structure and a preparation method of a semiconductor device, wherein a first material layer and a second material layer are firstly formed on a semiconductor substrate, the first material layer comprises a mask material layer and a dielectric material layer which are arranged at intervals in a first direction, the second material layer comprises a mask material layer and a dielectric material layer which are arranged at intervals in a second direction which is perpendicular to the first direction, then wet etching and dry etching are sequentially carried out, and as the etching rates of the mask material layer and the dielectric material layer are greatly different, the mask material layer/the dielectric material layer can be etched while the rest part is protected from being damaged, so that a metal interconnection groove is formed, and metal materials are filled in the groove to form the metal interconnection structure. The preparation method of the metal interconnection structure provided by the invention can obtain the metal interconnection groove without multiple exposure and etching, simplifies the process steps, saves the manufacturing cost and improves the accuracy of the formed metal interconnection structure.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a preparation method of a metal interconnection structure and a preparation method of a semiconductor device.
Background
With the increase of the integration level and the increase of the scale of the circuit, the size of unit devices in the circuit is continuously reduced, the requirements on the manufacturing process of the integrated circuit are continuously increased, for example, the critical dimension is continuously reduced, the requirements on the lithography resolution of the chip manufacturing are higher and higher, and the dependence on an extreme ultraviolet lithography machine in the prior process is more and more serious.
However, when the minimum resolution of the design pattern is below the physical resolution limit of the photolithography process, patterning cannot be achieved by one lithography, and dual or even multiple patterning techniques are often required, for example, let (Litho-Etch-Litho-Etch) techniques, which are more commonly used in dual patterning techniques, are used to break the design pattern into two sets of independent low density patterns, and transfer the circuit onto the wafer by two exposures and two etches. However, the method has high cost, and errors are easy to generate in the processes of multiple alignment, exposure and etching, so that the patterns obtained by final etching are different from the target patterns, and the performance of the semiconductor device is influenced.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides a method for manufacturing a metal interconnection structure and a method for manufacturing a semiconductor device, which first provides a semiconductor substrate, forms a first material layer and a second material layer on the semiconductor substrate, the first material layer includes a mask material layer and a dielectric material layer that are disposed at intervals in a first direction, the second material layer includes a mask material layer and a dielectric material layer that are disposed at intervals in a second direction perpendicular to the first direction, and then sequentially performs wet etching and dry etching, and can protect the remaining portion from loss while etching the mask material layer/dielectric material layer due to a large difference in etching rate between the mask material layer and the dielectric material layer, thereby forming a metal interconnection trench, and fills a metal material in the trench to form the metal interconnection structure. The preparation method of the metal interconnection structure provided by the invention can be applied to the advanced process of 14nm and below, the metal interconnection groove can be obtained without multiple exposure and etching, the process steps are simplified, the manufacturing cost is saved, the dependence on an extreme ultraviolet lithography machine in the advanced process is eliminated, and meanwhile, the accuracy of the formed metal interconnection structure is improved, so that the performance of the semiconductor device formed on the basis of the method is more stable.
To achieve the above and other related objects, the present invention provides a method for manufacturing a metal interconnection structure, including the steps of:
providing a semiconductor substrate, wherein a first dielectric layer and a second dielectric layer are formed above the semiconductor substrate;
forming a first material layer on the surface of the second dielectric layer, wherein the first material layer comprises a mask material layer and a dielectric material layer which are arranged at intervals in a first direction;
forming a second material layer on the surface of the first material layer, wherein the second material layer comprises a mask material layer and a dielectric material layer which are arranged at intervals in a second direction perpendicular to the first direction;
removing the mask material layer in the second material layer by wet etching to expose part of the first material layer, wherein the exposed dielectric material layer in the first material layer is a first area, and the exposed mask material layer in the first material layer is a second area;
removing the dielectric material layer in the second material layer, the dielectric material layer in the first region and the second dielectric layer corresponding to the lower part of the first region by dry etching, and forming a first groove in the second dielectric layer;
and continuing to etch the first dielectric layer along the first groove to form a second groove, and forming a metal interconnection line in the second groove.
Optionally, a first etching stop layer is further formed between the semiconductor substrate and the first dielectric layer.
Optionally, a bottom surface of the second trench is located on a surface of the semiconductor substrate.
Optionally, the material of the first dielectric layer is an ultra-low K material.
Optionally, the thickness of the second material layer is equal to the sum of the thicknesses of the first material layer and the second dielectric layer.
Optionally, the material of the second dielectric layer is the same as the material of the dielectric material layer.
Optionally, the gas used for removing the dielectric material layer and the mask material layer by dry etching is CH 3 F or CH 2 F 2 。
Optionally, a dry etching rate ratio of the dielectric material layer to the mask material layer is at least 10:1.
Optionally, the metal interconnection line is a copper interconnection line.
The invention also provides a preparation method of the semiconductor device, which comprises the following steps:
providing a metal interconnection structure;
sequentially forming a second etching stop layer, a third dielectric layer and a hard mask layer with an opening pattern;
etching the third dielectric layer by taking the patterned hard mask layer as a mask, forming a third groove in the third dielectric layer, and forming a metal layer in the third groove;
wherein the metal interconnection structure is formed by adopting the preparation method of the metal interconnection structure in any one of the schemes.
Optionally, the metal layer is a metal copper layer.
The preparation method of the metal interconnection structure and the preparation method of the semiconductor device provided by the invention have at least the following technical effects:
according to the preparation method of the metal interconnection structure, the first material layer and the second material layer are formed on the semiconductor substrate, the first material layer comprises the mask material layer and the dielectric material layer which are arranged at intervals in the first direction, the second material layer comprises the mask material layer and the dielectric material layer which are arranged at intervals in the second direction perpendicular to the first direction, then wet etching and dry etching are sequentially carried out, and as the etching rates of the mask material layer and the dielectric material layer are greatly different, the mask material layer/the dielectric material layer can be etched while the rest part is protected from being damaged, so that a metal interconnection groove is formed, and the metal material is filled in the groove to form the metal interconnection structure. The preparation method of the metal interconnection structure provided by the invention can be applied to the advanced process of 14nm and below, the metal interconnection groove can be obtained without multiple exposure and etching, the process steps are simplified, the manufacturing cost is saved, the dependence on an extreme ultraviolet lithography machine in the advanced process is eliminated, and meanwhile, the accuracy of the formed metal interconnection structure is improved, so that the performance of the semiconductor device formed on the basis of the method is more stable.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a metal interconnection structure according to a first embodiment.
Fig. 2a to 2c are schematic structural views of the embodiment formed in step S2.
Fig. 3 is a schematic structural diagram of the embodiment formed in step S3.
Fig. 4a to 4b are schematic structural views showing the structure formed in step S4 of the embodiment.
Fig. 5a shows a schematic structural diagram of the embodiment formed in step S5.
Fig. 5b shows a schematic cross-section of fig. 5a along A-A.
Fig. 6a to 6b are schematic structural views showing the structure formed in step S6 of the embodiment.
Fig. 7 is a flowchart showing a method for manufacturing a semiconductor device according to the second embodiment.
Fig. 8a to 8c are schematic structural views showing the structure of the second embodiment of steps S101 to S103.
Description of element reference numerals
10. Semiconductor substrate
11. First etching stop layer
12. A first dielectric layer
13. A second dielectric layer
14. A first material layer
15. A second material layer
16. Metal interconnect
17. Second etching stop layer
18. Third dielectric layer
19. Patterning hard mask layer
20. Metal layer
100. Mask material layer
200. Dielectric material layer
101. First region
102. Second region
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that, the illustrations provided in the present embodiment only illustrate the basic concept of the present invention by way of illustration, but only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number, positional relationship and proportion of each component in actual implementation may be changed at will on the premise of implementing the present technical solution, and the layout of the components may be more complex.
Example 1
The embodiment provides a method for preparing a metal interconnection structure, as shown in fig. 1, specifically including the following steps:
step S1: providing a semiconductor substrate, wherein a first dielectric layer and a second dielectric layer are formed above the semiconductor substrate;
as shown in fig. 2a, a semiconductor substrate 10 is provided, and the semiconductor substrate 10 may be a substrate structure known to those skilled in the art as a silicon substrate, a silicon germanium substrate, a silicon carbon substrate, a silicon on insulator Substrate (SOI), or the like. As an example, device structures, such as amplifiers, digital-to-analog converters, analog processing circuits and/or digital processing circuits, interface circuits, etc., may be formed within the semiconductor substrate 10, and the methods of forming these device structures may be CMOS processes.
Next, a first etch stop layer 11 is formed on the surface of the semiconductor substrate 10 for protecting various active devices and substrate materials and the like thereunder during etching. As an example, the first etch stop layer 11 may be one of nitrogen doped carbide (nitrogen doped silicon carbide, NBLoK), siN, siC, NDC.
Next, a first dielectric layer 12 is formed on the surface of the etching stop layer 11, where the material of the first dielectric layer 12 is a low-K material or an ultra-low-K material, for example, an inorganic material such as silicon oxyfluoride (SiOF), hydrogenated silicon oxycarbide (SiCOH), silicon oxycarbide (SiCO), or nitrogen doped silicon carbide (BLoK), or an organic compound such as an aromatic hydrocarbon or xylene plastic.
Next, a second dielectric layer 13 is formed on the surface of the first dielectric layer 12. In this embodiment, the material of the second dielectric layer 13 is tetraethyl orthosilicate (TEOS), so that the TEOS has better adhesion, and can sufficiently adhere the first dielectric layer 12 and the subsequently formed mask material layer 100, and simultaneously, the stress generated by the mask material layer 100 can be relieved, so that the overall structure is more stable.
Step S2: forming a first material layer on the surface of the second dielectric layer, wherein the first material layer comprises a mask material layer and a dielectric material layer which are arranged at intervals in a first direction;
as shown in fig. 2a, a mask material is deposited on the surface of the second dielectric layer 13, and the mask material is patterned into a mask material layer 100 with a strip structure extending in the second direction (i.e., the Y direction shown in fig. 2 c) by using a photolithography technique; then depositing a dielectric material on the surface of the structure and removing the dielectric material on the surface of the mask material layer 100 by using an etching technology, wherein the dielectric material on both sides of the mask material layer 100 is remained due to different etching rates in different directions, so as to form a dielectric material layer 200, as shown in fig. 2 b; next, a mask material is deposited on the surface of the structure, and the structure shown in fig. 2c is finally formed through a chemical mechanical polishing process, where the mask material layer 100 and the dielectric material layer 200 together form the first material layer 14, and the mask material layer 100 and the dielectric material layer 200 are arranged at intervals in the first direction (i.e. the X direction shown in fig. 2 c).
As an example, the wet etching rate of the mask material layer 100 is far greater than that of the dielectric material layer 200, and the dry etching rate ratio of the dielectric material layer 200 to the mask material layer 100 is at least 10:1, in this embodiment, siN is selected for the mask material layer 100, and SiO is selected for the dielectric material layer 200 2 。
Step S3: forming a second material layer on the surface of the first material layer, wherein the second material layer comprises a mask material layer and a dielectric material layer which are arranged at intervals in a second direction perpendicular to the first direction;
as shown in fig. 3, a second material layer 15 is formed on the surface of the first material layer 14 by the same method as in step S2, and the second material layer also includes a mask material layer 100 and a dielectric material layer 200, unlike the first material layer 14, the mask material layer 100 and the dielectric material layer 200 in the second material layer 15 are arranged at intervals in a second direction (i.e., Y direction shown in fig. 3) perpendicular to the first direction.
Step S4: removing the mask material layer in the second material layer by wet etching to expose part of the first material layer, wherein the exposed dielectric material layer in the first material layer is a first area, and the exposed mask material layer in the first material layer is a second area;
referring to fig. 4a to 4b, the mask material layer 100 in the second material layer 15 is removed by a wet etching method, exposing a portion of the first material layer 14, where the exposed dielectric material layer 200 is the first region 101, and the exposed mask material layer 100 is the second region 102.
In this embodiment, the phosphoric acid solution is selected for wet etching, and the wet etching rate of the mask material layer 100 is far greater than that of the dielectric material layer 200, so that only the mask material layer 100 can be removed in the etching process, and the dielectric material layer 200 is not damaged.
Step S5: and removing the dielectric material layer in the second material layer, the dielectric material layer in the first region and the second dielectric layer corresponding to the lower part of the first region by dry etching, and forming a first groove in the second dielectric layer.
As an example, the dielectric material layer 200 in the second material layer 15 is removed by dry etching, in this embodiment, the thickness of the second material layer 15 is equal to the sum of the thicknesses of the first material layer 14 and the second dielectric layer 13, so that the dielectric material layer 200 in the first region 101 and the corresponding second dielectric layer 13 under the first region are simultaneously etched and removed, and the first trench 110 is formed in the second dielectric layer 13, as shown in fig. 5a to 5 b.
In the present embodiment, the gas used for dry etching is CH 3 F or CH 2 F 2 The dry etching rate of the dielectric material layer 200 and the mask material layer 100 is at least 10:1, so that the method can be used for forming the mask material layerIt can be ensured that only the dielectric material layer 200 is removed during the dry etching process, and the mask material layer 100 is not damaged.
Step S6: and continuing etching along the first groove to form a second groove, and forming a metal interconnection line in the second groove.
As shown in fig. 6a, etching is continued along the first trench 110, the corresponding first dielectric layer 12 and the first etching stop layer 11 are removed, a second trench 120 is formed, and the bottom surface of the second trench 120 is located on the surface of the semiconductor substrate 10.
Next, the second trench 120 is filled with a metal material, which in this embodiment is copper, to form the metal interconnect 16. Finally, the second dielectric layer 13 on the surface of the first dielectric layer 12 and the remaining mask material layer 100 in the first material layer are removed, so as to form the metal interconnection structure shown in fig. 6 b.
According to the preparation method of the metal interconnection structure, the first material layer and the second material layer are formed on the semiconductor substrate, the first material layer comprises the mask material layer and the dielectric material layer which are arranged at intervals in the first direction, the second material layer comprises the mask material layer and the dielectric material layer which are arranged at intervals in the second direction perpendicular to the first direction, then wet etching and dry etching are sequentially carried out, and as the etching rates of the mask material layer and the dielectric material layer are greatly different, the mask material layer/the dielectric material layer can be etched while the rest part is protected from being damaged, so that the metal interconnection groove is formed, and the metal material is filled in the groove to form the metal interconnection structure. The preparation method of the metal interconnection structure provided by the invention can be applied to the advanced process of 14nm and below, the metal interconnection groove can be obtained without multiple exposure and etching, the process steps are simplified, the manufacturing cost is saved, the dependence on an extreme ultraviolet lithography machine in the advanced process is eliminated, and the accuracy of the formed metal interconnection structure is improved.
Example two
The embodiment provides a method for manufacturing a semiconductor device, as shown in fig. 7, including the following steps:
step S101: providing a metal interconnection structure;
as an example, the metal interconnection structure is the metal interconnection structure provided in the first embodiment, and the description of the first embodiment is specifically referred to, and will not be repeated herein.
Step S102: sequentially forming a second etching stop layer, a third dielectric layer and a hard mask layer with an opening pattern;
as shown in fig. 8a, a second etch stop layer 17 is formed on the surface of the metal interconnect structure, and the second etch stop layer 17 may be one of nitrogen doped carbide (nitrogen doped silicon carbide, NBLoK), siN, siC, NDC, as an example.
Next, a third dielectric layer 18 is formed on the surface of the second etching stop layer 17, and the material of the third dielectric layer 18 is the same as that of the first dielectric layer 12, and is a low-K material or an ultra-low-K material, for example, an inorganic material such as silicon oxyfluoride (SiOF), hydrogenated silicon oxycarbide (SiCOH), silicon oxycarbide (SiCO), or nitrogen-doped silicon carbide (BLoK), or an organic compound such as an aromatic hydrocarbon or xylene plastic.
Next, a hard mask layer is deposited on the surface of the third dielectric layer 18, a photoresist (not shown in the figure) is coated on the surface of the hard mask layer, the photoresist is patterned, and the hard mask layer is etched using the photoresist pattern as a mask layer, so as to form a patterned hard mask layer 19 having an opening, as shown in fig. 8 a.
Step S103: and etching the third dielectric layer by taking the patterned hard mask layer as a mask, forming a third groove in the third dielectric layer, and forming a metal layer in the third groove.
As shown in fig. 8b, the third dielectric layer 18 and the second etching stop layer 17 are etched using the patterned hard mask layer 19 as a mask, so as to form a third trench 130, exposing the metal interconnection structure; next, as shown in fig. 8c, a metal material is filled in the third trench 130 to form a metal layer 20, and the metal layer 20 is electrically connected to the metal interconnection line 16, in this embodiment, the metal layer 20 is a copper material layer; finally, the hard mask layer on the surface of the third dielectric layer 18 is removed by chemical mechanical polishing, thereby forming the semiconductor device shown in fig. 8 c.
In summary, the present invention provides a method for manufacturing a metal interconnection structure and a method for manufacturing a semiconductor device, which firstly provides a semiconductor substrate, forms a first material layer and a second material layer on the semiconductor substrate, wherein the first material layer includes a mask material layer and a dielectric material layer which are arranged at intervals in a first direction, the second material layer includes a mask material layer and a dielectric material layer which are arranged at intervals in a second direction perpendicular to the first direction, and then sequentially performs wet etching and dry etching. The preparation method of the metal interconnection structure provided by the invention can be applied to the advanced process of 14nm and below, the metal interconnection groove can be obtained without multiple exposure and etching, the process steps are simplified, the manufacturing cost is saved, the dependence on an extreme ultraviolet lithography machine in the advanced process is eliminated, and meanwhile, the accuracy of the formed metal interconnection structure is improved, so that the performance of the semiconductor device formed on the basis of the method is more stable.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (11)
1. The preparation method of the metal interconnection structure is characterized by comprising the following steps of:
providing a semiconductor substrate, wherein a first dielectric layer and a second dielectric layer are formed above the semiconductor substrate;
forming a first material layer on the surface of the second dielectric layer, wherein the first material layer comprises a mask material layer and a dielectric material layer which are arranged at intervals in a first direction;
forming a second material layer on the surface of the first material layer, wherein the second material layer comprises a mask material layer and a dielectric material layer which are arranged at intervals in a second direction perpendicular to the first direction;
removing the mask material layer in the second material layer by wet etching to expose part of the first material layer, wherein the exposed dielectric material layer in the first material layer is a first area, and the exposed mask material layer in the first material layer is a second area;
removing the dielectric material layer in the second material layer, the dielectric material layer in the first region and the second dielectric layer corresponding to the lower part of the first region by dry etching, and forming a first groove in the second dielectric layer;
and continuing to etch the first dielectric layer along the first groove to form a second groove, and forming a metal interconnection line in the second groove.
2. The method of manufacturing a metal interconnect structure of claim 1, wherein a first etch stop layer is further formed between the semiconductor substrate and the first dielectric layer.
3. The method of claim 1, wherein a bottom surface of the second trench is located on a surface of the semiconductor substrate.
4. The method for manufacturing a metal interconnection structure according to claim 1, wherein the material of the first dielectric layer is an ultra-low K material.
5. The method of claim 1, wherein the thickness of the second material layer is equal to the sum of the thicknesses of the first material layer and the second dielectric layer.
6. The method of claim 1, wherein the material of the second dielectric layer is the same as the material of the dielectric material layer.
7. The method of claim 1, wherein the gas used for dry etching to remove the dielectric material layer and the mask material layer is CH 3 F or CH 2 F 2 。
8. The method of claim 7, wherein a dry etching rate ratio of the dielectric material layer to the mask material layer is at least 10:1.
9. The method of claim 1, wherein the metal interconnect line is a copper interconnect line.
10. A method of manufacturing a semiconductor device, comprising the steps of:
providing a metal interconnection structure;
sequentially forming a second etching stop layer, a third dielectric layer and a hard mask layer with an opening pattern;
etching the third dielectric layer by taking the patterned hard mask layer as a mask, forming a third groove in the third dielectric layer, and forming a metal layer in the third groove;
wherein the metal interconnect structure is formed using the method of manufacturing a metal interconnect structure as claimed in any one of claims 1 to 9.
11. The method of manufacturing a semiconductor device according to claim 10, wherein the metal layer is a metal copper layer.
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| CN202111238163.XA CN116031201A (en) | 2021-10-25 | 2021-10-25 | Method for preparing metal interconnection structure and method for preparing semiconductor device |
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