CN116027930B

CN116027930B - Dynamic frame rate control method and device

Info

Publication number: CN116027930B
Application number: CN202310139121.3A
Authority: CN
Inventors: 陈婷; 黄志文; 赖志业
Original assignee: Shenzhen Xihua Technology Co Ltd
Current assignee: Shenzhen Xihua Technology Co Ltd
Priority date: 2023-02-21
Filing date: 2023-02-21
Publication date: 2023-08-08
Anticipated expiration: 2043-02-21
Also published as: CN116027930A

Abstract

The embodiment of the application discloses a dynamic frame rate control method and a device, which are applied to electronic equipment, wherein the electronic equipment comprises: VIDC, LCDC, double buffer memory module, AP and display screen, double buffer memory module includes first buffer memory unit and second buffer memory unit, and the method includes: acquiring a current first refresh frequency f1 of a display screen; acquiring a second refresh frequency f2, f1 > f2, of the display screen to be converted; reading data from the second cache unit through LCDC fixation; wherein, a frame of data is divided into k TE signals to generate, k is a/f2, a is the least common multiple between f1 and f2; before the LCDC reads and while generating a first TE signal, the VIDC is designated to write data in the second buffer unit, the first TE signal being the first TE signal of the k TE signals. By adopting the embodiment of the application, after the frame rate is reduced, obvious clamping caused by touch sliding is eliminated, so that the screen display effect is improved.

Description

Dynamic frame rate control method and device

Technical Field

The application relates to the technical field of chips or the technical field of image processing, in particular to a dynamic frame rate control method and a dynamic frame rate control device.

Background

In practical application, mipi Command mode refers to sending image data to a display module through dcscenmmand, where the image data is temporarily stored in a Frame Buffer of a screen end, and a common mode is to synchronize a TE (TE) signal through a tearing effect, and most of the screen end chips can control an input Frame rate of an application processor (application processor, AP) by controlling a frequency of the TE signal, for example, the AP supports 120Hz input, but with a 60Hz screen, and a method of generating a 60Hz TE signal can achieve a Frame rate reduction.

The current electronic equipment can reduce the frame rate through TE signals, but the touch sliding after the frame rate is reduced has obvious clamping and is used for influencing the screen display effect, so that the obvious clamping and the clamping caused by the touch sliding are eliminated after the frame rate is reduced, and the screen display effect is improved.

Disclosure of Invention

The embodiment of the application provides a dynamic frame rate control method and device, which can eliminate obvious clamping caused by touch sliding after the frame rate is reduced so as to improve the screen display effect.

In a first aspect, an embodiment of the present application provides a dynamic frame rate control method, which is applied to an electronic device, where the electronic device includes: the method comprises the steps of an image processing module VIDC, an image display processing module LCDC, a double-buffer module, an application processor AP and a display screen, wherein the double-buffer module comprises a first buffer unit and a second buffer unit, the writing rate of the AP is larger than the reading rate of the LCDC, and the method comprises the following steps:

acquiring a current first refresh frequency f1 of the display screen;

acquiring a second refresh frequency f2 to be converted of the display screen, wherein f1 is more than f2;

reading data from the second cache unit through the LCDC fixation; wherein, a frame of data is divided into k TE signals to generate, k is a/f2, a is the least common multiple between f1 and f2;

and before the LCDC reads and when a first TE signal is generated, designating the VIDC to write the data in the second buffer unit, wherein the first TE signal is the first TE signal in the k TE signals.

In a second aspect, an embodiment of the present application provides a dynamic frame rate control device, which is applied to an electronic device, where the electronic device includes: the device comprises an image processing module VIDC, an image display processing module LCDC, a double-buffer module, an application processor AP and a display screen, wherein the double-buffer module comprises a first buffer memory unit and a second buffer memory unit, the writing rate of the AP is larger than the reading rate of the LCDC, and the device comprises: an acquisition unit, a reading unit and a writing unit, wherein,

the acquisition unit is used for acquiring the current first refresh frequency f1 of the display screen; obtaining a second refresh frequency f2 to be converted of the display screen, wherein f1 is more than f2;

the reading unit is used for fixedly reading data from the second cache unit through the LCDC; wherein, a frame of data is divided into k TE signals to generate, k is a/f2, a is the least common multiple between f1 and f2;

the writing unit is configured to specify, before the LCDC reads and when a first TE signal is generated, the VIDC to write data in the second buffer unit, where the first TE signal is a first TE signal of the k TE signals.

In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a memory, a communication interface, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the processor, and the programs include instructions for performing the steps in the first aspect of the embodiment of the present application.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, where the computer-readable storage medium stores a computer program for electronic data exchange, where the computer program causes a computer to perform some or all of the steps as described in the first aspect of the embodiments of the present application.

In a fifth aspect, embodiments of the present application provide a computer program product, wherein the computer program product comprises a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps described in the first aspect of the embodiments of the present application. The computer program product may be a software installation package.

By implementing the embodiment of the application, the following beneficial effects are achieved:

it can be seen that the dynamic frame rate control method and apparatus described in the embodiments of the present application are applied to an electronic device, where the electronic device includes: the method comprises the steps that an image processing module VIDC, an image display processing module LCDC, a double-buffer module, an application processor AP and a display screen are adopted, the double-buffer module comprises a first buffer unit and a second buffer unit, the writing rate of the AP is larger than the reading rate of the LCDC, the current first refresh frequency f1 of the display screen is obtained, the second refresh frequency f2 of the display screen to be converted is obtained, wherein f1 is larger than f2, and data are fixedly read from the second buffer unit through the LCDC; the frame data is divided into k TE signals to be generated, k is a/f2, a is the least common multiple between f1 and f2, the VIDC is assigned to write the data in the second Buffer unit before the LCDC reads and when the first TE signal is generated, the first TE signal is the first TE signal in the k TE signals, therefore, the LCDC fixedly reads the data from the second Buffer unit, and the AP write is faster than the LCDC output, therefore, the VIDC is assigned to write the data of the same Buffer (the second Buffer unit) when the first TE signal is generated before the LCDC reads, at the moment, the VIDC writes one frame without tearing, and therefore, obvious clamping caused by touch sliding can be eliminated after the frame rate is reduced, and the screen display effect is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a chip structure of an electronic device provided in the present application;

FIG. 2 is a schematic diagram of a chip display data path provided herein;

FIG. 3 is a schematic illustration of a partial update location demonstration of a continuous 3-frame input image provided herein;

fig. 4 is a schematic diagram showing a local update position of a continuous 3-frame input image after frame loss;

FIG. 5 is a schematic diagram of a dual Buffer dynamic TE flow provided in an embodiment of the present application;

fig. 6 is a flowchart of a dynamic frame rate control method according to an embodiment of the present application;

fig. 7 is a flowchart of another dynamic frame rate control method according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 9 is a functional unit composition block diagram of a dynamic frame rate control device according to an embodiment of the present application.

Detailed Description

The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to the list of steps or elements but may include, in one possible example, other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The electronic device described in the embodiments of the present application may be an electronic device including chips, where the electronic device may include a smart Phone (such as an Android mobile Phone, iOS mobile Phone, windows Phone mobile Phone, etc.), a tablet computer, a palm computer, a walkie-talkie, a notebook computer, a mobile internet device (MID, mobileInternet Devices) or a wearable device, chips, etc., which are merely examples, but not exhaustive, including but not limited to the above-mentioned Devices, and of course, the above-mentioned electronic device may also be a server, a cloud platform, etc. The electronic device may also include chips, which may be chips or other forms, e.g., the electronic device may include a multi-screen display system or a multi-screen display device.

Referring to fig. 1, fig. 1 is a schematic diagram of a chip structure of an electronic device according to an embodiment of the present application. The electronic device comprises an application processor AP, a chip 100 and a display module (LCD), wherein the AP is in communication connection with the chip 100, and the chip 100 is in communication connection with the display module.

As shown in fig. 1, the chip 100 includes a mobile industry processor interface receiving MIPI RX module 101, a Video pre-processing VPRE module 102, an image processing module VIDC103, an image display processing module LCDC104, and a MIPI TX module 105, the MIPI RX module 101 is connected to the VPRE module 102, the VPRE module 102 is connected to the VIDC103, the VIDC103 is connected to the LCDC104, the LCDC104 is connected to the MIPI TX module 105, and the Video mode means that the output mode of the chip is a Video mode. In the Video mode, the VIDC is informed to carry out data synchronous transmission by the VIDC through a frame start signal, and the LCDC data processing is completed and is informed to the MIPI TX module to carry out data synchronous transmission through an output end frame synchronization Vsync_out signal.

Referring to fig. 2, fig. 2 provides a schematic diagram of a chip display data path, where MIPI RX is connected to MIPI tx module through two channels, a first channel is provided with a display processing module, where the display processing module may be different according to different functions or different manufacturers, for example, a microprocessor MCU, a control module, etc., the application is not limited to the specific expression form of the display processing module, a second channel is provided with a display module and LCDC, and a dual buffer module is connected to the two channels respectively.

Based on the above-mentioned chips in fig. 1 or fig. 2, in practical application, since a part of APs support specific area update image data or non-global area update image data (PU), when a frame is actively lost from the front end, local important data may be lost, resulting in abnormal display of a picture.

For example, as shown in fig. 3, when the input image is 120Hz- >60Hz, 3 frames of input images are continuously input, wherein the first frame is globally updated, the local update position above the second frame is updated, the local update position below the third frame is updated, further, as shown in fig. 4, since the input of the second frame is discarded, the observed data is abnormal, that is, the display image is expected to be updated by dividing the display image into two local update positions up and down, and in fact, only the lower local update position is updated since the display image is updated after the second frame is discarded.

In a specific implementation, for the dual Buffer dynamic TE flow, as shown in fig. 5, when the dual Buffer is used (FB 0, FB 1), and a PU appears, the image processing module must make a PU from another Buffer copy base data (partial update base data), for example, when the PU is FB0, the PU needs to carry the base data from FB1 to FB0 first, and then make an update of the PU. In practical application, the situation that the same frame buffer cannot be written 2 times can occur, so that the previous PU data is covered.

Referring to fig. 6, fig. 6 is a flowchart of a dynamic frame rate control method according to an embodiment of the present application, as shown in the drawing, applied to an electronic device, where the electronic device includes: the method for controlling the dynamic frame rate comprises the following steps of:

601. and acquiring the current first refresh frequency f1 of the display screen.

In this embodiment of the present application, f1 may be preset or default.

602. And acquiring a second refresh frequency f2 which needs to be converted of the display screen, wherein f1 is larger than f2.

In a specific implementation, the current second refresh frequency may be related to a display requirement of the user, and different display requirements may correspond to different f2. Of course, f2 may be preset or default.

Optionally, when the number of the display screens is plural, the step 602 of obtaining the second refresh frequency f2 to be converted for the display screen may include the following steps:

621. acquiring n refreshing frequencies of which the refreshing frequencies supported by the display screens in the display screens are smaller than f1, wherein n is a positive integer;

622. acquiring target display parameters of the content to be displayed;

623. determining a refresh frequency range corresponding to the target display parameter;

624. determining an intersection between the refresh frequency range and the n refresh frequencies to obtain m refresh frequencies, wherein m is a positive integer less than or equal to n;

625. and determining f2 according to the m refresh frequencies.

In an embodiment of the present application, the target display parameter may include at least one of the following: display resolution, display frame rate, data format of display data, etc., are not limited herein. Different display parameters can correspond to different refresh frequency ranges, namely, the mapping relation between the preset display parameters and the refresh frequency ranges can be preset.

In this embodiment of the present application, n refresh frequencies supported by a display screen in a plurality of display screens may be obtained, where n is a positive integer, and then a target display parameter of a content to be displayed may be obtained, a refresh frequency range corresponding to the target display parameter may be determined according to a preset mapping relationship between the display parameter and the refresh frequency range, and then an intersection between the refresh frequency range and the n refresh frequencies may be determined, so as to obtain m refresh frequencies, where m is a positive integer less than or equal to n, and then f2 may be determined according to the m refresh frequencies, for example, one refresh frequency of the m refresh frequencies may be selected as f2, and further, a refresh frequency corresponding to a user display requirement may be obtained, which is helpful to select a suitable display screen to meet a visual requirement and a display requirement of a user.

603. Reading data from the second cache unit through the LCDC fixation; wherein, a frame of data is divided into k TE signal generation, k is a/f2, a is the least common multiple between f1 and f2.

In a specific implementation, the data may be read from the second buffer unit through LCDC fixing, for example, LCDC may read data from the second buffer unit according to a preset time interval, where the preset time interval may be preset or default in the system.

Wherein, a frame of data is divided into k TE signal generation, k is a/f2, a is the least common multiple between f1 and f2, and a frame of data can refer to image data.

604. And before the LCDC reads and when a first TE signal is generated, designating the VIDC to write the data in the second buffer unit, wherein the first TE signal is the first TE signal in the k TE signals.

In this embodiment, before LCDC reading and when a first TE signal is generated, the VIDC is specified to write data in the second buffer unit, where the first TE signal is the first TE signal in the k TE signals, so that after the frame rate is reduced, obvious jamming caused by touch sliding is eliminated, so as to improve the screen display effect.

For example, in the embodiment of the present application, the software may use a method of dynamically adjusting TE by using a fixed output Buffer, taking f1 as 120Hz and f2 as 60Hz as an example, where the first Buffer unit may be denoted as FB0, and the second Buffer unit may be denoted as FB2. Specifically, the output frame data may be divided into 2 TE generation, i.e., TE0 and TE1, similar to a single Buffer, where one TE data is received (denoted as TE 0) and another TE data may not be displayed (denoted as TE 1). Specifically, the LCDC may fix the data read from FB1, and since the AP writes faster than the LCDC outputs, when TE0 is generated before LCDC reads, the VIDC is specified to write the data of the same Buffer (FB 1), and when the VIDC writes one frame, no tear will occur.

Optionally, the method further comprises the following steps:

and in the process of outputting the same frame of data, before the generation of a second TE signal, writing the VIDC to the first buffer unit, and keeping the LCDC to continuously read the data of the second buffer unit, wherein the second TE signal is a non-first TE signal in the k TE signals.

In this embodiment of the present application, before the second TE signal is generated in outputting the same frame of data, writing of the VIDC may be directed to the first buffer unit, so that the LCDC is kept to continuously read the data of the second buffer unit, where the second TE signal is a non-first TE signal of the k TE signals, so that the situation that the same frame buffer is written for 2 times can be avoided, the situation that the previous PU data is covered can occur, after the frame rate is reduced, obvious clamping caused by touch sliding can be eliminated, so as to improve the screen display effect.

For example, taking f1 as 120Hz and f2 as 60Hz as an example, the first buffer unit may be denoted as FB0, the second buffer unit may be denoted as FB2, and the VIDC write cannot lose frames, needs to be stored in FB0, so as to prevent the Partial update base data from losing frames. In a specific implementation, during the same output frame, the second frame data written by the AP tends to catch up with the read, the writing of the VIDC needs to be pointed to FB0 before TE1 is generated, and the LCDC continues to read the data of FB 1.

Optionally, the method further comprises the following steps:

a1, when TE signals need to be generated, detecting the position of a target cache unit to be written by the VICC;

a2, if the target cache unit position is the same as the reference cache unit position of the LCDC current reading operation, controlling not to generate TE signals.

In the embodiment of the present application, when a TE signal needs to be generated, the target buffer unit position where the VIDC is to be written is detected, and if the target buffer unit position is the same as the reference buffer unit position of the LCDC in the current reading operation, the TE signal is controlled not to be generated, so that after the frame rate is reduced, obvious jamming caused by touch sliding is eliminated, and the screen display effect is improved.

For example, taking f1 as 120Hz and f2 as 60Hz, the first buffer unit may be referred to as FB0 and the second buffer unit may be referred to as FB2. Before TE1 needs to be generated, checking the Buffer position to be written by the VIDC, and if the Buffer position is the same as the current read FB position of the LCDC, not generating the TE.

Alternatively, when f1=120 HZ and f2=60 HZ, k=2, the first TE signal is denoted as TE0, and the second TE signal is denoted as TE1;

the step of designating the VIDC to write the data in the second buffer unit before the LCDC reads and when the first TE signal is generated, includes:

before the LCDC reads and while generating the TE0, the VIDC is designated to write data in the second cache location, where the TE0 is received and the TE1 is allowed to be undisplayed.

In a specific implementation, since the AP writes in faster than the LCDC outputs, before LCDC reads and when TE0 is generated, the data written in the second buffer unit by the VIDC is designated, where TE0 is received and TE1 is allowed to be not displayed, and no tear will be generated when the VIDC writes in a frame, so that after the frame rate is reduced, obvious jamming caused by touch sliding can be eliminated, so as to improve the screen display effect.

It can be seen that the dynamic frame rate control method described in the embodiments of the present application is applied to an electronic device, where the electronic device includes: the method comprises the steps that an image processing module VIDC, an image display processing module LCDC, a double-buffer module, an application processor AP and a display screen are adopted, the double-buffer module comprises a first buffer unit and a second buffer unit, the writing rate of the AP is larger than the reading rate of the LCDC, the current first refresh frequency f1 of the display screen is obtained, the second refresh frequency f2 of the display screen to be converted is obtained, wherein f1 is larger than f2, and data are fixedly read from the second buffer unit through the LCDC; the frame data is divided into k TE signals to be generated, k is a/f2, a is the least common multiple between f1 and f2, the VIDC is assigned to write the data in the second Buffer unit before the LCDC reads and when the first TE signal is generated, the first TE signal is the first TE signal in the k TE signals, therefore, the LCDC fixedly reads the data from the second Buffer unit, and the AP write is faster than the LCDC output, therefore, the VIDC is assigned to write the data of the same Buffer (the second Buffer unit) when the first TE signal is generated before the LCDC reads, at the moment, the VIDC writes one frame without tearing, and therefore, obvious clamping caused by touch sliding can be eliminated after the frame rate is reduced, and the screen display effect is improved.

In accordance with the embodiment shown in fig. 1, please refer to fig. 7, fig. 7 is a flowchart of a dynamic frame rate control method according to an embodiment of the present application, which is applied to an electronic device, and the electronic device includes: the method for controlling the dynamic frame rate comprises the following steps of:

701. and acquiring the current first refresh frequency f1 of the display screen.

702. And acquiring a second refresh frequency f2 which needs to be converted of the display screen, wherein f1 is larger than f2.

703. Reading data from the second cache unit through the LCDC fixation; wherein, a frame of data is divided into k TE signal generation, k is a/f2, a is the least common multiple between f1 and f2.

704. And before the LCDC reads and when a first TE signal is generated, designating the VIDC to write the data in the second buffer unit, wherein the first TE signal is the first TE signal in the k TE signals.

705. And in the process of outputting the same frame of data, before the generation of a second TE signal, writing the VIDC to the first buffer unit, and keeping the LCDC to continuously read the data of the second buffer unit, wherein the second TE signal is a non-first TE signal in the k TE signals.

706. And when the TE signal is required to be generated, detecting the target cache unit position to be written by the VICC.

707. And if the target cache unit position is the same as the reference cache unit position of the LCDC current reading operation, controlling not to generate a TE signal.

The specific description of steps 701 to 707 may refer to the corresponding steps of the dynamic frame rate control method described in fig. 1, and are not repeated herein.

It can be seen that the dynamic frame rate control method described in the embodiments of the present application is applied to an electronic device, where the electronic device includes: the method comprises the steps that an image processing module VIDC, an image display processing module LCDC, a double-buffer module, an application processor AP and a display screen are adopted, the double-buffer module comprises a first buffer unit and a second buffer unit, the writing rate of the AP is larger than the reading rate of the LCDC, the current first refresh frequency f1 of the display screen is obtained, the second refresh frequency f2 of the display screen to be converted is obtained, wherein f1 is larger than f2, and data are fixedly read from the second buffer unit through the LCDC; the method comprises the steps that a frame of data is divided into k TE signals to be generated, k is a/f2, a is the least common multiple between f1 and f2, when a first TE signal is generated before LCDC reading, the VIDC is assigned to write data in a second buffer unit, the first TE signal is the first TE signal in the k TE signals, therefore, the LCDC fixedly reads the data from the second buffer unit, when the same frame of data is output, before the second TE signal is generated, the writing of the VIDC is directed to the first buffer unit, the LCDC is kept to continuously read the data of the second buffer unit, the second TE signal is the non-first TE signal in the k TE signals, when the TE signal is required to be generated, the position of a target buffer unit to be written by the VIDC is detected, if the position of the target buffer unit is the same as the position of a reference buffer unit of the current reading operation of the LCDC, the first TE signal is not generated, and obvious blocking caused by touch sliding can be eliminated after the frame rate is reduced, so that the screen display effect is improved.

In accordance with the above embodiments, referring to fig. 8, fig. 8 is a schematic structural diagram of an electronic device provided in the embodiment of the present application, as shown in the fig. 8, the electronic device includes a processor, a memory, a communication interface, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the processor, and the electronic device further includes: the image processing module VIDC, the image display processing module LCDC, the dual buffer module comprising a first buffer unit and a second buffer unit, and the processor may comprise an application processor AP, the writing rate of which is greater than the reading rate of the LCDC, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and in the embodiment of the present application, the programs comprise instructions for executing the following steps:

acquiring a current first refresh frequency f1 of the display screen;

Optionally, the above program further comprises instructions for performing the steps of:

when a TE signal is required to be generated, detecting the position of a target cache unit to be written by the VICC;

and if the target cache unit position is the same as the reference cache unit position of the LCDC current reading operation, controlling not to generate a TE signal.

the method further includes, prior to the LCDC reading and upon generation of a first TE signal, designating the VIDC to write data in the second cache element, the method comprising instructions for:

Optionally, when the number of the display screens is plural, in the aspect of obtaining the second refresh frequency f2 that the display screens need to be converted, the program further includes instructions for executing the following steps:

acquiring n refreshing frequencies of which the refreshing frequencies supported by the display screens in the display screens are smaller than f1, wherein n is a positive integer;

acquiring target display parameters of the content to be displayed;

determining a refresh frequency range corresponding to the target display parameter;

determining an intersection between the refresh frequency range and the n refresh frequencies to obtain m refresh frequencies, wherein m is a positive integer less than or equal to n;

and determining f2 according to the m refresh frequencies.

It can be seen that, in the dynamic frame rate control method described in the embodiments of the present application, since the AP writing is faster than the LCDC output, when the LCDC reads the first TE signal, the VIDC is designated to write the data of the same Buffer (second Buffer unit), and at this time, the VIDC writes one frame without tearing, so that after the frame rate is reduced, obvious clamping caused by touch sliding can be eliminated, so as to improve the screen display effect.

Fig. 9 is a functional block diagram of a dynamic frame rate control apparatus 900 according to an embodiment of the present application, where the dynamic frame rate control apparatus 900 is applied to an electronic device, and the electronic device includes: the dynamic frame rate control device 900 includes: an acquisition unit 901, a reading unit 902, and a writing unit 903, wherein,

the acquiring unit 901 is configured to acquire a current first refresh frequency f1 of the display screen; obtaining a second refresh frequency f2 to be converted of the display screen, wherein f1 is more than f2;

the reading unit 902 is configured to fixedly read data from the second buffer unit through the LCDC; wherein, a frame of data is divided into k TE signals to generate, k is a/f2, a is the least common multiple between f1 and f2;

the writing unit 903 is configured to specify, before the LCDC reads and when a first TE signal is generated, the VIDC to write data in the second buffer unit, where the first TE signal is a first TE signal of the k TE signals.

Optionally, the dynamic frame rate control device 900 is further specifically configured to:

the writing unit 903 is specifically configured to, before the LCDC reads and when the first TE signal is generated, specify that the VIDC writes data in the second buffer unit:

Optionally, when the number of the display screens is plural, in the aspect of acquiring the second refresh frequency f2 that the display screens need to be converted, the acquiring unit 901 is specifically configured to:

acquiring target display parameters of the content to be displayed;

and determining f2 according to the m refresh frequencies.

It can be seen that the dynamic frame rate control device described in the embodiments of the present application is applied to an electronic device, where the electronic device includes: the method comprises the steps that an image processing module VIDC, an image display processing module LCDC, a double-buffer module, an application processor AP and a display screen are adopted, the double-buffer module comprises a first buffer unit and a second buffer unit, the writing rate of the AP is larger than the reading rate of the LCDC, the current first refresh frequency f1 of the display screen is obtained, the second refresh frequency f2 of the display screen to be converted is obtained, wherein f1 is larger than f2, and data are fixedly read from the second buffer unit through the LCDC; the method comprises the steps that a frame of data is divided into k TE signals to be generated, k is a/f2, a is the least common multiple between f1 and f2, when a first TE signal is generated before LCDC reading, the VIDC is assigned to write data in a second buffer unit, the first TE signal is the first TE signal in the k TE signals, therefore, the LCDC fixedly reads the data from the second buffer unit, when the same frame of data is output, before the second TE signal is generated, the writing of the VIDC is directed to the first buffer unit, the LCDC is kept to continuously read the data of the second buffer unit, the second TE signal is the non-first TE signal in the k TE signals, when the TE signal is required to be generated, the position of a target buffer unit to be written by the VIDC is detected, if the position of the target buffer unit is the same as the position of a reference buffer unit of the current reading operation of the LCDC, the first TE signal is not generated, and obvious blocking caused by touch sliding can be eliminated after the frame rate is reduced, so that the screen display effect is improved.

It may be understood that the functions of each program module of the dynamic frame rate control apparatus of the present embodiment may be specifically implemented according to the method in the foregoing method embodiment, and the specific implementation process may refer to the relevant description of the foregoing method embodiment, which is not repeated herein.

The embodiment of the application also provides a computer storage medium, where the computer storage medium stores a computer program for electronic data exchange, where the computer program causes a computer to execute part or all of the steps of any one of the methods described in the embodiments of the method, where the computer includes an electronic device.

Embodiments of the present application also provide a computer program product comprising a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any one of the methods described in the method embodiments above. The computer program product may be a software installation package, said computer comprising an electronic device.

It should be noted that, for simplicity of description, the foregoing method embodiments are all expressed as a series of action combinations, but it should be understood by those skilled in the art that the present application is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required in the present application.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, such as the above-described division of units, merely a division of logic functions, and there may be additional manners of dividing in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a memory, including several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the above-mentioned method of the various embodiments of the present application. And the aforementioned memory includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the above embodiments may be implemented by a program that instructs associated hardware, and the program may be stored in a computer readable memory, which may include: flash disk, read-Only Memory (ROM), random access Memory (RandomAccess Memory, RAM), magnetic disk or optical disk.

The foregoing has outlined rather broadly the more detailed description of embodiments of the present application, wherein specific examples are provided herein to illustrate the principles and embodiments of the present application, the above examples being provided solely to assist in the understanding of the methods of the present application and the core ideas thereof; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A dynamic frame rate control method, applied to an electronic device, the electronic device comprising: the method comprises the steps of an image processing module VIDC, an image display processing module LCDC, a double-buffer module, an application processor AP and a display screen, wherein the double-buffer module comprises a first buffer unit and a second buffer unit, the writing rate of the AP is larger than the reading rate of the LCDC, and the method comprises the following steps:

acquiring a current first refresh frequency f1 of the display screen;

designating the VIDC to write the data in the second buffer unit before the LCDC reads and when a first TE signal is generated, wherein the first TE signal is the first TE signal in the k TE signals;

2. The method according to claim 1, wherein the method further comprises:

3. The method of claim 1, wherein when f1=120 HZ, f2=60 HZ, k=2, the first TE signal is denoted TE0, and the second TE signal is denoted TE1;

4. A method according to claim 3, wherein, when the number of the display screens is plural, the obtaining the second refresh frequency f2 that the display screens need to switch includes:

acquiring target display parameters of the content to be displayed;

and determining f2 according to the m refresh frequencies.

5. A dynamic frame rate control apparatus, characterized by being applied to an electronic device, the electronic device comprising: the device comprises an image processing module VIDC, an image display processing module LCDC, a double-buffer module, an application processor AP and a display screen, wherein the double-buffer module comprises a first buffer memory unit and a second buffer memory unit, the writing rate of the AP is larger than the reading rate of the LCDC, and the device comprises: an acquisition unit, a reading unit and a writing unit, wherein,

the writing unit is configured to designate, before the LCDC reads and when a first TE signal is generated, the VIDC to write data in the second buffer unit, where the first TE signal is a first TE signal of the k TE signals;

6. The device according to claim 5, characterized in that it is also specifically adapted to:

7. An electronic device comprising a processor, a memory for storing one or more programs and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-4.

8. A computer-readable storage medium, characterized in that a computer program for electronic data exchange is stored, wherein the computer program causes a computer to perform the method according to any of claims 1-4.