CN116015287B - Method and device for correcting TDC stepping based on frequency-to-voltage circuit - Google Patents
Method and device for correcting TDC stepping based on frequency-to-voltage circuit Download PDFInfo
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Abstract
The invention discloses a method and a device for correcting TDC stepping based on a frequency-to-voltage circuit, wherein the method comprises the following steps: generating N second time-digital converters based on the copying of the K first time-digital converters, connecting the N second time-digital converters to oscillate in a negative feedback mode through path control, and outputting oscillation frequency pulses; the frequency-to-voltage circuit converts oscillation frequency pulses into voltages and outputs converted voltages, and the voltage control circuit compares the converted voltages with reference voltages to determine control voltages and outputs the control voltages to the first time-to-digital converter and the second time-to-digital converter; after the phase-locked loop circuit starts to work, the voltage control circuit enables the converted voltage to be equal to the reference voltage through the control voltage and the second time-to-digital converter, so that the delay of the first time-to-digital converter, namely the stepping precision, is corrected and fixed. The invention can efficiently correct the TDC stepping precision by converting oscillation frequency pulses output by the TDC into voltage for control.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method and a device for correcting TDC stepping based on a frequency-to-voltage circuit.
Background
In the phase-locked loop circuit, a time-to-digital converter (TDC, time to Digital Converter) is a key element for testing the phase difference, but the TDC is greatly affected by process fluctuation, and has a great influence on the locking and performance of the phase-locked loop, particularly an all-digital phase-locked loop (ADPLL).
The invention patent with publication number CN102916693B discloses an all-digital phase-locked loop, which comprises an analog-digital conversion circuit ADC, an automatic gain control circuit AGC, a digital low-pass filter DLPF, a synchronous head separation circuit, a frequency discriminator FD, a time-digital conversion circuit TDC, a coarse tuning filter, a phase discriminator PD, a fine tuning filter, an adder, a digital controlled oscillator DCO and a pixel frequency division circuit. The frequency discriminator, the time-digital conversion circuit, the coarse tuning filter, the numerical control oscillator and the pixel frequency divider circuit form a frequency locking loop, so that the locking process of the all-digital phase-locked loop is quickened. The analog-digital conversion circuit, the automatic gain control circuit, the digital low-pass filter, the phase frequency detector, the fine-tuning filter, the digital controlled oscillator and the pixel frequency divider circuit form a phase-locked loop for accurately locking the phase of the synchronous head in the analog video signal.
The invention patent with publication number CN113098497B discloses an all-digital phase-locked loop low-noise digital phase discriminator based on an adaptive Kalman filter, which comprises: a multistage-adjusting all-digital phase-locked loop based on a phase accumulator and an adaptive Kalman filter arranged in the multistage-adjusting all-digital phase-locked loop and used for reducing noise, wherein: the input end of the self-adaptive Kalman filter receives the DCO control word of the previous period and the phase information of the DCO output signal measured in the current period respectively, and the estimation information of quantization noise is utilized for filtering, so that the phase information of the optimized DCO output signal is obtained. According to the invention, noise optimization is performed on all noise sources of the all-digital phase-locked loop, and the quantization noise of the TDC and the quantization noise of the DCO in the phase discrimination process are optimized by utilizing the self-adaptive Kalman filter, so that the noise component in the phase discrimination result is reduced, and the noise performance of the loop is optimized.
The invention patent application with publication number CN106209080A discloses an all-digital phase-locked loop with low jitter and wide capture frequency range, which comprises a TDC module, a digital filter, a DCO module, a frequency divider and a variable mode frequency divider; the TDC module compares the phases of the input reference clock and the feedback clock and outputs a phase error signal; the digital filter converts the phase error signal into a group of control words, and the DCO module adjusts the frequency and the phase of the output clock according to the group of control words; the frequency of the output clock is reduced by half by the two frequency dividers, and a feedback clock is generated for comparison of the TDC module after the frequency is divided according to a preset modulus value by the variable modulus frequency divider; and the full digital phase-locked loop is locked until the frequencies of the reference clock and the feedback clock are consistent and the phase reaches the preset error. The TDC module reduces output jitter; the DCO module is adjusted to widen the capture frequency range of the phase-locked loop, and solves the problems of higher jitter value and narrower capture frequency range of the existing all-digital phase-locked loop.
Disclosure of Invention
In order to solve the above-mentioned problems, the present invention provides a method and apparatus for correcting the step of a TDC based on a frequency-to-voltage circuit, which can efficiently and accurately correct the step accuracy of a time-to-digital converter by converting an oscillation frequency pulse output from the time-to-digital converter into a voltage for control.
The technical scheme adopted by the invention is as follows:
a method for correcting TDC stepping based on a frequency to voltage circuit, comprising the steps of:
s1, based on K first time digital converters in a phase-locked loop circuit, copying to generate N second time digital converters, connecting the N second time digital converters to oscillate in a negative feedback mode through access control, and outputting oscillation frequency pulses to a frequency-to-voltage circuit; wherein K, N >1;
s2, the frequency-to-voltage circuit converts the oscillation frequency pulse into voltage and outputs the converted voltage to a voltage control circuit, and the voltage control circuit compares the converted voltage with a reference voltage to determine a control voltage and outputs the control voltage to the first time-to-digital converter and the second time-to-digital converter;
s3, after the phase-locked loop circuit starts to work, the voltage control circuit enables the conversion voltage output by the frequency-to-voltage conversion circuit to be equal to the reference voltage through the control voltage and the second time-to-digital converter, so that delay, namely stepping accuracy, of the first time-to-digital converter is corrected and fixed.
Further, the frequency-to-voltage circuit comprises a switching pulse conversion circuit, a bias circuit, a frequency conversion circuit and a low-pass filter circuit, wherein the switching pulse conversion circuit, the frequency conversion circuit and the low-pass filter circuit are electrically connected in sequence, and the bias circuit is electrically connected with the frequency conversion circuit; the switching pulse conversion circuit is configured to convert an input pulse into two paths of differential switching control signals; the bias circuit is configured to provide a bias current; the frequency to voltage circuit is configured to form a charge transfer through a complementary switch and bypass capacitor based on the switch control signal and a bias current provided by the bias circuit, and to output a node voltage; the low pass filter circuit is configured to filter out high frequency ripple in the node voltage to obtain a final voltage, thereby converting the input pulse frequency into a voltage.
Further, the frequency conversion circuit comprises a mirror constant current source, a first MOS tube switch, a second MOS tube switch, a first resistor, a first capacitor and a second capacitor, wherein the first end of the first resistor is electrically connected with a working power supply, the second end of the first resistor is electrically connected with the mirror constant current source input end, the first MOS tube switch and the first end of the first capacitor, the second end of the first MOS tube switch is electrically connected with the second MOS tube switch and the first end of the second capacitor, and the second end of the mirror constant current source output end, the second MOS tube switch, the first capacitor and the second capacitor is grounded.
Further, the frequency conversion circuit comprises a mirror constant current source, a first MOS tube switch, a second MOS tube switch, a first resistor, a first capacitor and a second capacitor, wherein the input end of the mirror constant current source is electrically connected with a working power supply, the output end of the mirror constant current source is electrically connected with the first ends of the first MOS tube switch, the first resistor and the first capacitor, the second end of the first MOS tube switch is electrically connected with the first ends of the second MOS tube switch and the second capacitor, and the second ends of the second MOS tube switch, the first resistor, the first capacitor and the second capacitor are grounded.
Further, the voltage control circuit comprises a low dropout linear voltage regulator, a signal input end of the low dropout linear voltage regulator is electrically connected with a signal output end of the frequency-to-voltage conversion circuit, and a signal output end of the low dropout linear voltage regulator is electrically connected with signal input ends of the first time-to-digital converter and the second time-to-digital converter.
The device for correcting the TDC stepping based on the frequency-to-voltage circuit comprises K first time-to-digital converters, N second time-to-digital converters, a frequency-to-voltage circuit and a voltage control circuit, wherein the second time-to-digital converters, the frequency-to-voltage circuit and the voltage control circuit are electrically connected in sequence, and the voltage control circuit is electrically connected with the first time-to-digital converters and the second time-to-digital converters respectively; wherein K, N >1;
the second time-digital converters are duplicated and generated by the first time-digital converters in the phase-locked loop circuit, and the N second time-digital converters are connected and oscillated in a negative feedback mode and can output oscillation frequency pulses to the frequency-to-voltage conversion circuit;
the frequency-to-voltage circuit is configured to convert the oscillation frequency pulse into a voltage and output the converted voltage to the voltage control circuit;
the voltage control circuit is configured to compare the converted voltage with a reference voltage, determine a control voltage and output the control voltage to the first time-to-digital converter and the second time-to-digital converter; after the phase-locked loop circuit starts to work, the voltage control circuit can make the conversion voltage output by the frequency-to-voltage conversion circuit equal to the reference voltage through the control voltage and the second time-to-digital converter, so that the delay, namely the stepping precision, of the first time-to-digital converter is corrected and fixed.
Further, the frequency-to-voltage circuit comprises a switching pulse conversion circuit, a bias circuit, a frequency conversion circuit and a low-pass filter circuit, wherein the switching pulse conversion circuit, the frequency conversion circuit and the low-pass filter circuit are electrically connected in sequence, and the bias circuit is electrically connected with the frequency conversion circuit; the switching pulse conversion circuit is configured to convert an input pulse into two paths of differential switching control signals; the bias circuit is configured to provide a bias current; the frequency to voltage circuit is configured to form a charge transfer through a complementary switch and bypass capacitor based on the switch control signal and a bias current provided by the bias circuit, and to output a node voltage; the low pass filter circuit is configured to filter out high frequency ripple in the node voltage to obtain a final voltage, thereby converting the input pulse frequency into a voltage.
Further, the frequency conversion circuit comprises a mirror constant current source, a first MOS tube switch, a second MOS tube switch, a first resistor, a first capacitor and a second capacitor, wherein the first end of the first resistor is electrically connected with a working power supply, the second end of the first resistor is electrically connected with the mirror constant current source input end, the first MOS tube switch and the first end of the first capacitor, the second end of the first MOS tube switch is electrically connected with the second MOS tube switch and the first end of the second capacitor, and the second end of the mirror constant current source output end, the second MOS tube switch, the first capacitor and the second capacitor is grounded.
Further, the frequency conversion circuit comprises a mirror constant current source, a first MOS tube switch, a second MOS tube switch, a first resistor, a first capacitor and a second capacitor, wherein the input end of the mirror constant current source is electrically connected with a working power supply, the output end of the mirror constant current source is electrically connected with the first ends of the first MOS tube switch, the first resistor and the first capacitor, the second end of the first MOS tube switch is electrically connected with the first ends of the second MOS tube switch and the second capacitor, and the second ends of the second MOS tube switch, the first resistor, the first capacitor and the second capacitor are grounded.
Further, the voltage control circuit comprises a low dropout linear voltage regulator, a signal input end of the low dropout linear voltage regulator is electrically connected with a signal output end of the frequency-to-voltage conversion circuit, and a signal output end of the low dropout linear voltage regulator is electrically connected with signal input ends of the first time-to-digital converter and the second time-to-digital converter.
The invention has the beneficial effects that:
according to the method and the device for correcting the TDC stepping based on the frequency-to-voltage circuit, the oscillation frequency pulse output by the time-to-digital converter is converted into the voltage to be controlled, so that the stepping precision of the time-to-digital converter can be accurately corrected.
Drawings
The typical time-to-digital converter delay of fig. 1 is a schematic diagram of process fluctuations.
FIG. 2 is a flow chart of a method for correcting TDC stepping based on a frequency-to-voltage circuit according to the present invention.
FIG. 3 is a schematic diagram of a method for correcting TDC stepping based on a frequency-to-voltage circuit according to the present invention.
FIG. 4 is a schematic diagram of a plurality of time-to-digital converter connections according to the present invention
Fig. 5 is a schematic diagram of a frequency-to-voltage circuit of the present invention.
Fig. 6 is a schematic diagram before and after input pulse processing.
Fig. 7 is a waveform diagram at node voltages VA, VB.
Fig. 8 is a schematic diagram of the frequency vs. voltage of the present invention.
Fig. 9 is a schematic diagram of a low pass filter circuit of the present invention.
Fig. 10 is a schematic diagram of a complete circuit for implementing a preferred frequency to voltage conversion in accordance with the present invention.
One of the waveforms at each node of fig. 11.
Second, the waveforms at each node of fig. 12.
Fig. 13 is a schematic diagram of a voltage control circuit of the present invention.
Detailed Description
Specific embodiments of the present invention will now be described in order to provide a clearer understanding of the technical features, objects and effects of the present invention. It should be understood that the particular embodiments described herein are illustrative only and are not intended to limit the invention, i.e., the embodiments described are merely some, but not all, of the embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Example 1
As shown in fig. 1, which shows the delay of a typical time-to-digital converter (TDC, time to Digital Converter) as a process fluctuates, it can be seen that the delay times in the typical case, slow case (SS), and fast case (FF) are not fixed.
Accordingly, the present embodiment provides a method for correcting TDC stepping based on a frequency-to-voltage circuit, as shown in fig. 2 and 3, comprising the steps of:
s1, based on K first time digital converters in a phase-locked loop circuit, copying to generate N second time digital converters, connecting the N second time digital converters to oscillate in a negative feedback mode through access control, and outputting oscillation frequency pulses to a frequency-to-voltage circuit; wherein K, N >1;
s2, converting oscillation frequency pulses into voltage by the frequency-to-voltage conversion circuit and outputting a converted voltage Vout to the voltage control circuit, comparing the converted voltage Vout with a reference voltage Vref by the voltage control circuit, determining a control voltage Vcont and outputting the control voltage Vcont to the first time digital converter and the second time digital converter;
s3, after the PLL circuit starts to work, the voltage control circuit equalizes the converted voltage Vout outputted by the frequency-to-voltage conversion circuit with the reference voltage Vref through the control voltage Vcont and the second time-to-digital converter, and the frequency of the oscillation frequency pulse is indirectly informed to be fixed frequency fx, and frequency fx=N×T delay So the frequency fx fixes, i.e. fixes, the delay T of the time-to-digital converter delay . Since the first and second time-to-digital converters are identical, the delay of the control voltage Vcont after being sent to the K bit first time-to-digital converter is corrected to be T delay 。
As shown in fig. 4, the N time-to-digital converters are connected end to end, and the negative feedback can make the time-to-digital converters oscillate, so that a stable oscillation frequency can be obtained after a period of time.
Preferably, as shown in fig. 5, the frequency-to-voltage circuit includes a switching pulse conversion circuit, a bias circuit, a frequency conversion circuit, and a low-pass filter circuit, which are electrically connected in sequence, the bias circuit being electrically connected to the frequency conversion circuit; the switching pulse conversion circuit is configured to convert an input pulse into two paths of differential switching control signals; the bias circuit is configured to provide a bias current; the frequency-to-voltage circuit is configured to form charge transport through the complementary switch and the bypass capacitor based on the switch control signal and the bias current provided by the bias circuit, and to output a node voltage; the low pass filter circuit is configured to filter out high frequency ripple in the node voltage to obtain a final voltage, thereby converting the input pulse frequency into a voltage.
Preferably, as shown in fig. 6, the switching pulse converting circuit converts the input pulse into two differential switching control signals, and there are various ways to implement the switching pulse converting circuit, in which the input pulse can be directly used as a driving signal, and one path of the driving signal passes through the inverter, and the other path of the driving signal passes through the transmission gate to implement single-ended to differential switching.
Preferably, the frequency conversion circuit comprises a mirror constant current source, a first MOS tube switch, a second MOS tube switch, a first resistor, a first capacitor and a second capacitor, and the specific implementation mode and the circuit structure of the frequency conversion circuit have two types:
(1) As shown in fig. 7, the first end of the first resistor is electrically connected to the working power supply, the second end of the first resistor is electrically connected to the mirror constant current source input end, the first MOS transistor switch and the first end of the first capacitor, the second end of the first MOS transistor switch is electrically connected to the second MOS transistor switch and the first end of the second capacitor, and the mirror constant current source output end, the second MOS transistor switch, the second end of the first capacitor and the second capacitor are grounded.
(2) The input end of the mirror constant current source is electrically connected with the working power supply, the output end of the mirror constant current source is electrically connected with the first ends of the first MOS tube switch, the first resistor and the first capacitor, the second end of the first MOS tube switch is electrically connected with the first ends of the second MOS tube switch and the second capacitor, and the second ends of the second MOS tube switch, the first resistor, the first capacitor and the second capacitor are grounded.
Specifically, as shown in fig. 7, the implementation principle of the present embodiment for converting the input pulse frequency to the voltage is described by taking the implementation mode (1) as an example as follows:
i1 is a mirror constant current source, which allows a substantially constant current in the working interval.
And R1 is a first resistor, C1 and C2 are a first capacitor and a second capacitor respectively, the capacitance value of C1 is much larger than that of C2, and S1B are a first MOS tube switch and a second MOS tube switch respectively.
The VB node voltage is an output node of the frequency-to-voltage circuit.
4. After the switching starts, S1 and S1B are connected with a switch control signal of the switch pulse switching circuit, and S1B are conducted in turn:
(1) When S1 is on, S1B is off. The S1 switch resistance is very small, and C1 and C2 can rapidly realize va≡vb, and charge on C2=c×vb.
(2) When S1B is on, S1 is off. The low on-resistance of S1B will rapidly pull VB voltage close to ground, i.e., VB≡0.
(3) After long-term operation is stable, in one period of the pulse period, the circuit realizes the process of charging the C2 voltage to VB and then to 0, and the process realizes the charge carrying. In the long term, the process of transporting charges can be equivalent to an average current, and the principle of average current if=f×c2×vb is equivalent to that of a switched capacitor as a resistor.
(4) Based on the calculation in step (3), in the long term, according to KCL (kirchhoff current law), the current flowing through the resistor R1=i1+if, so the average voltage across the resistor is:
VR＝(I1+If)*R1 (1)
(5) Substituting vb=vdd-VR into equation (1) yields:
VB average voltage ＝＝(VDD-I1*R1)/(1+R1*f*C2) (2)
When I1 and R, C2 are both circuit control values, VB is an expression that is monotonic with frequency, and the fluctuation of frequency can be converted into the fluctuation of voltage.
In particular, the current source I1, i.e. i1=0 in equation (2), may not be required, and the equation may be simplified as:
VB average voltage ＝(VDD)/(1+R1*f*C2) (3)
As can be seen from the circuit analysis of fig. 7, the average voltage of VB and the input pulse frequency f are the relationship of formula (2), i.e., the higher the input pulse frequency, the lower the output voltage. Although the average voltage of VB is substantially inversely proportional to the input pulse frequency f, the transient voltage has a high frequency ripple and the actual VA/VB waveform is shown in FIG. 8.
Since too large ripple is unfavorable for accurate control, attenuation of ripple can be achieved by passing the signal VB through a large low-pass filter, which can be realized by RC as shown in fig. 9. A preferred complete circuit for implementing the frequency to voltage conversion in this embodiment is shown in fig. 10.
One of the waveforms at each node is shown in fig. 11, where frequency f=1/150 ns. As shown in fig. 12, which shows a second waveform at each node, where f=1/300 ns, it is seen that the frequency decreases and VOUT increases, i.e., the input pulse frequency is inversely proportional to the output voltage, and the result is consistent with the functional description.
Preferably, the voltage control circuit can be implemented by a low dropout linear regulator (LDO), and the common similar LDOs have the capability of locking the output voltage to the reference voltage, as shown in the common LDO structure in fig. 13, after stabilizing the circuit of the operational amplifier OPA and the power transistor MP will lock the Vout output to the circuit of Vref1p1, and the principle of the voltage control circuit is similar. Wherein Vref1p1 is the corrected reference voltage Vref, vfb is the voltage signal after receiving the converted voltage, and Vout is the Vcont voltage signal.
Example 2
The embodiment provides a device for correcting TDC stepping based on a frequency-to-voltage circuit, which comprises K first time-to-digital converters, N second time-to-digital converters, a frequency-to-voltage circuit and a voltage control circuit, wherein the second time-to-digital converters, the frequency-to-voltage circuit and the voltage control circuit are electrically connected in sequence, and the voltage control circuit is electrically connected with the first time-to-digital converters and the second time-to-digital converters respectively; wherein K, N >1.
The second time digital converters are duplicated and generated by the first time digital converters in the phase-locked loop circuit, and the N second time digital converters are connected with the oscillation in a negative feedback mode and can output oscillation frequency pulses to the frequency-to-voltage conversion circuit. As shown in fig. 4, the N time-to-digital converters are connected end to end, and the negative feedback can make the time-to-digital converters oscillate, so that a stable oscillation frequency can be obtained after a period of time.
The frequency-to-voltage circuit is configured to convert the oscillation frequency pulse into a voltage and output the converted voltage Vout to the voltage control circuit.
The voltage control circuit is configured to compare the converted voltage Vout with a reference voltage Vref to determine a control voltage Vcont and outputting to the first time-to-digital converter and the second time-to-digital converter; after the pll circuit starts to operate, the voltage control circuit can make the converted voltage Vout output by the frequency-to-voltage conversion circuit equal to the reference voltage Vref by controlling the voltage Vcont and the second time-to-digital converter, and indirectly notify that the frequency of the oscillating frequency pulse is a fixed frequency fx, and that the frequency fx=n×t delay So the frequency fx fixes, i.e. fixes, the delay T of the time-to-digital converter delay . Since the first and second time-to-digital converters are identical, the delay of the control voltage Vcont after being sent to the K bit first time-to-digital converter is corrected to be T delay 。
Preferably, as shown in fig. 5, the frequency-to-voltage circuit includes a switching pulse conversion circuit, a bias circuit, a frequency conversion circuit, and a low-pass filter circuit, which are electrically connected in sequence, the bias circuit being electrically connected to the frequency conversion circuit; the switching pulse conversion circuit is configured to convert an input pulse into two paths of differential switching control signals; the bias circuit is configured to provide a bias current; the frequency-to-voltage circuit is configured to form charge transport through the complementary switch and the bypass capacitor based on the switch control signal and the bias current provided by the bias circuit, and to output a node voltage; the low pass filter circuit is configured to filter out high frequency ripple in the node voltage to obtain a final voltage, thereby converting the input pulse frequency into a voltage.
Preferably, as shown in fig. 6, the switching pulse converting circuit converts the input pulse into two differential switching control signals, and there are various ways to implement the switching pulse converting circuit, in which the input pulse can be directly used as a driving signal, and one path of the driving signal passes through the inverter, and the other path of the driving signal passes through the transmission gate to implement single-ended to differential switching.
Preferably, the frequency conversion circuit comprises a mirror constant current source, a first MOS tube switch, a second MOS tube switch, a first resistor, a first capacitor and a second capacitor, and the specific implementation mode and the circuit structure of the frequency conversion circuit have two types:
(1) As shown in fig. 7, the first end of the first resistor is electrically connected to the working power supply, the second end of the first resistor is electrically connected to the mirror constant current source input end, the first MOS transistor switch and the first end of the first capacitor, the second end of the first MOS transistor switch is electrically connected to the second MOS transistor switch and the first end of the second capacitor, and the mirror constant current source output end, the second MOS transistor switch, the second end of the first capacitor and the second capacitor are grounded.
(2) The input end of the mirror constant current source is electrically connected with the working power supply, the output end of the mirror constant current source is electrically connected with the first ends of the first MOS tube switch, the first resistor and the first capacitor, the second end of the first MOS tube switch is electrically connected with the first ends of the second MOS tube switch and the second capacitor, and the second ends of the second MOS tube switch, the first resistor, the first capacitor and the second capacitor are grounded.
Specifically, as shown in fig. 7, the implementation principle of the present embodiment for converting the input pulse frequency to the voltage is described by taking the implementation mode (1) as an example as follows:
i1 is a mirror constant current source, which allows a substantially constant current in the working interval.
And R1 is a first resistor, C1 and C2 are a first capacitor and a second capacitor respectively, the capacitance value of C1 is much larger than that of C2, and S1B are a first MOS tube switch and a second MOS tube switch respectively.
The VB node voltage is an output node of the frequency-to-voltage circuit.
4. After the switching starts, S1 and S1B are connected with a switch control signal of the switch pulse switching circuit, and S1B are conducted in turn:
(1) When S1 is on, S1B is off. The S1 switch resistance is very small, and C1 and C2 can rapidly realize va≡vb, and charge on C2=c×vb.
(2) When S1B is on, S1 is off. The low on-resistance of S1B will rapidly pull VB voltage close to ground, i.e., VB≡0.
(3) After long-term operation is stable, in one period of the pulse period, the circuit realizes the process of charging the C2 voltage to VB and then to 0, and the process realizes the charge carrying. In the long term, the process of transporting charges can be equivalent to an average current, and the principle of average current if=f×c2×vb is equivalent to that of a switched capacitor as a resistor.
(4) Based on the calculation in step (3), in the long term, according to KCL (kirchhoff current law), the current flowing through the resistor R1=i1+if, so the average voltage across the resistor is:
VR＝(I1+If)*R1 (1)
(5) Substituting vb=vdd-VR into equation (1) yields:
VB average voltage ＝＝(VDD-I1*R1)/(1+R1*f*C2) (2)
When I1 and R, C2 are both circuit control values, VB is an expression that is monotonic with frequency, and the fluctuation of frequency can be converted into the fluctuation of voltage.
In particular, the current source I1, i.e. i1=0 in equation (2), may not be required, and the equation may be simplified as:
VB average voltage ＝(VDD)/(1+R1*f*C2) (3)
As can be seen from the circuit analysis of fig. 7, the average voltage of VB and the input pulse frequency f are the relationship of formula (2), i.e., the higher the input pulse frequency, the lower the output voltage. Although the average voltage of VB is substantially inversely proportional to the input pulse frequency f, the transient voltage has a high frequency ripple and the actual VA/VB waveform is shown in FIG. 8.
Since too large ripple is unfavorable for accurate control, attenuation of ripple can be achieved by passing the signal VB through a large low-pass filter, which can be realized by RC as shown in fig. 9. A preferred complete circuit for implementing the frequency to voltage conversion in this embodiment is shown in fig. 10.
One of the waveforms at each node is shown in fig. 11, where frequency f=1/150 ns. As shown in fig. 12, which shows a second waveform at each node, where f=1/300 ns, it is seen that the frequency decreases and VOUT increases, i.e., the input pulse frequency is inversely proportional to the output voltage, and the result is consistent with the functional description.
Preferably, the voltage control circuit can be implemented by a low dropout linear regulator (LDO), and the common similar LDOs have the capability of locking the output voltage to the reference voltage, as shown in the common LDO structure in fig. 13, after stabilizing the circuit of the operational amplifier OPA and the power transistor MP will lock the Vout output to the circuit of Vref1p1, and the principle of the voltage control circuit is similar. Wherein Vref1p1 is the corrected reference voltage Vref, vfb is the voltage signal after receiving the converted voltage, and Vout is the Vcont voltage signal.
It should be noted that, for the sake of simplicity of description, the foregoing method embodiments are expressed as a series of combinations of actions, but it should be understood by those skilled in the art that the present application is not limited by the order of actions described, as some steps may be performed in other order or simultaneously according to the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required in the present application.
Claims (4)
1. A method for correcting TDC stepping based on a frequency to voltage circuit, comprising the steps of:
s1, based on K first time digital converters in a phase-locked loop circuit, copying to generate N second time digital converters, connecting the N second time digital converters to oscillate in a negative feedback mode through access control, and outputting oscillation frequency pulses to a frequency-to-voltage circuit; wherein K, N >1;
s2, the frequency-to-voltage circuit converts the oscillation frequency pulse into voltage and outputs the converted voltage to a voltage control circuit, and the voltage control circuit compares the converted voltage with a reference voltage to determine a control voltage and outputs the control voltage to the first time-to-digital converter and the second time-to-digital converter;
s3, after the phase-locked loop circuit starts to work, the voltage control circuit enables the conversion voltage output by the frequency-to-voltage conversion circuit to be equal to the reference voltage through the control voltage and the second time-to-digital converter, so that the delay of the first time-to-digital converter, namely, the stepping precision is corrected and fixed;
the frequency-to-voltage circuit comprises a switching pulse conversion circuit, a bias circuit, a frequency conversion circuit and a low-pass filter circuit, wherein the switching pulse conversion circuit, the frequency conversion circuit and the low-pass filter circuit are electrically connected in sequence, and the bias circuit is electrically connected with the frequency conversion circuit; the switching pulse conversion circuit is configured to convert an input pulse into two paths of differential switching control signals; the bias circuit is configured to provide a bias current; the frequency to voltage circuit is configured to form a charge transfer through a complementary switch and bypass capacitor based on the switch control signal and a bias current provided by the bias circuit, and to output a node voltage; the low-pass filter circuit is configured to filter out high-frequency ripple in the node voltage to obtain a final voltage, so that the input pulse frequency is converted into the voltage;
the frequency conversion circuit comprises a mirror constant current source, a first MOS tube switch, a second MOS tube switch, a first resistor, a first capacitor and a second capacitor, and two modes and circuit structures of the frequency conversion circuit are realized:
the first end of the first resistor is electrically connected with a working power supply, the second end of the first resistor is electrically connected with the input end of the mirror constant current source, the first MOS tube switch and the first end of the first capacitor, the second end of the first MOS tube switch is electrically connected with the first ends of the second MOS tube switch and the second capacitor, and the second ends of the mirror constant current source output end, the second MOS tube switch, the first capacitor and the second capacitor are grounded;
the input end of the mirror constant current source is electrically connected with a working power supply, the output end of the mirror constant current source is electrically connected with the first ends of the first MOS tube switch, the first resistor and the first capacitor, the second end of the first MOS tube switch is electrically connected with the first ends of the second MOS tube switch and the second capacitor, and the second ends of the second MOS tube switch, the first resistor, the first capacitor and the second capacitor are grounded.
2. The method of correcting TDC stepping based on a frequency-to-voltage circuit according to claim 1, wherein the voltage control circuit comprises a low dropout linear regulator having a signal input electrically connected to the signal output of the frequency-to-voltage circuit, and a signal output electrically connected to the signal inputs of the first and second time-to-digital converters.
3. The device for correcting the TDC stepping based on the frequency-to-voltage circuit is characterized by comprising K first time-to-digital converters, N second time-to-digital converters, a frequency-to-voltage circuit and a voltage control circuit, wherein the second time-to-digital converters, the frequency-to-voltage circuit and the voltage control circuit are electrically connected in sequence, and the voltage control circuit is electrically connected with the first time-to-digital converters and the second time-to-digital converters respectively; wherein K, N >1;
the second time-digital converters are duplicated and generated by the first time-digital converters in the phase-locked loop circuit, and the N second time-digital converters are connected and oscillated in a negative feedback mode and can output oscillation frequency pulses to the frequency-to-voltage conversion circuit;
the frequency-to-voltage circuit is configured to convert the oscillation frequency pulse into a voltage and output the converted voltage to the voltage control circuit;
the voltage control circuit is configured to compare the converted voltage with a reference voltage, determine a control voltage and output the control voltage to the first time-to-digital converter and the second time-to-digital converter; after the phase-locked loop circuit starts to work, the voltage control circuit can make the conversion voltage output by the frequency-to-voltage conversion circuit equal to the reference voltage through the control voltage and the second time-to-digital converter, so that the delay of the first time-to-digital converter, namely, the stepping precision is corrected and fixed;
the frequency-to-voltage circuit comprises a switching pulse conversion circuit, a bias circuit, a frequency conversion circuit and a low-pass filter circuit, wherein the switching pulse conversion circuit, the frequency conversion circuit and the low-pass filter circuit are electrically connected in sequence, and the bias circuit is electrically connected with the frequency conversion circuit; the switching pulse conversion circuit is configured to convert an input pulse into two paths of differential switching control signals; the bias circuit is configured to provide a bias current; the frequency to voltage circuit is configured to form a charge transfer through a complementary switch and bypass capacitor based on the switch control signal and a bias current provided by the bias circuit, and to output a node voltage; the low-pass filter circuit is configured to filter out high-frequency ripple in the node voltage to obtain a final voltage, so that the input pulse frequency is converted into the voltage;
the frequency conversion circuit comprises a mirror constant current source, a first MOS tube switch, a second MOS tube switch, a first resistor, a first capacitor and a second capacitor, and two modes and circuit structures of the frequency conversion circuit are realized:
the first end of the first resistor is electrically connected with a working power supply, the second end of the first resistor is electrically connected with the input end of the mirror constant current source, the first MOS tube switch and the first end of the first capacitor, the second end of the first MOS tube switch is electrically connected with the first ends of the second MOS tube switch and the second capacitor, and the second ends of the mirror constant current source output end, the second MOS tube switch, the first capacitor and the second capacitor are grounded;
the input end of the mirror constant current source is electrically connected with a working power supply, the output end of the mirror constant current source is electrically connected with the first ends of the first MOS tube switch, the first resistor and the first capacitor, the second end of the first MOS tube switch is electrically connected with the first ends of the second MOS tube switch and the second capacitor, and the second ends of the second MOS tube switch, the first resistor, the first capacitor and the second capacitor are grounded.
4. The device for correcting TDC stepping based on a frequency-to-voltage circuit according to claim 3, wherein the voltage control circuit comprises a low dropout linear regulator, the signal input terminal of the low dropout linear regulator being electrically connected to the signal output terminal of the frequency-to-voltage circuit, the signal output terminal of the low dropout linear regulator being electrically connected to the signal input terminals of the first time-to-digital converter and the second time-to-digital converter.
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