CN116013885A - Chip heat dissipation packaging structure and forming method thereof - Google Patents
Chip heat dissipation packaging structure and forming method thereof Download PDFInfo
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- CN116013885A CN116013885A CN202310012352.8A CN202310012352A CN116013885A CN 116013885 A CN116013885 A CN 116013885A CN 202310012352 A CN202310012352 A CN 202310012352A CN 116013885 A CN116013885 A CN 116013885A
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Abstract
The invention relates to a chip heat dissipation packaging structure, which comprises: a micro flow channel cover plate arranged above the chip and configured to radiate heat for the chip and protect the chip; the lower micro-channel plate is connected with the micro-channel cover plate and is configured to perform multi-surface heat dissipation on the chip; a chip disposed in the lower micro flow channel plate; and the substrate structure is connected with the lower micro-channel plate. In the chip heat dissipation packaging structure, the six sides of the chip are provided with the micro-channels, so that six sides of the chip can be dissipated, and the chip with higher heat flux density can be comprehensively dissipated.
Description
Technical Field
The present disclosure relates to semiconductor packaging technology, and more particularly, to a heat dissipation packaging structure for a chip and a method for forming the same.
Background
Along with the continuous reduction of the chip size, the chip integration level is continuously improved, the functions are more and more powerful, and the packaging density is also higher and higher. This causes a sharp increase in power consumption per unit volume of the chip, and a sharp increase in temperature of the chip, resulting in a decrease in reliability of the chip, affecting normal operation of the chip. It was found that the system reliability would be reduced by half for every 10 c increase in the temperature of the active device. While failure of more than 55% of the electronic devices is due to excessive temperatures. It follows that heat dissipation from the chip has become a key element in the normal operation of electronic devices, and micro-channel heat dissipation is a very efficient solution. At present, three common micro-channel assembly schemes are adopted, one is that a micro-channel cold plate is attached to the back surface of a packaging cover through a thermal interface, and the scheme has the advantages of easy realization, oversized and larger thermal resistance; secondly, a micro-channel is directly manufactured on the back of the heat source chip, so that the thermal resistance is minimum, but the manufacturing difficulty is high; and the third is to integrate the micro-channel cold plate in the packaging cover, the scheme is simple to realize and has smaller thermal resistance. In addition, most of the existing heat dissipation schemes are single-sided or double-sided heat dissipation, six sides of the chips are lack of heat dissipation, and heat dissipation capability of the chips with high performance is insufficient.
Disclosure of Invention
In order to solve at least a part of the problems in the prior art, the invention provides a chip heat dissipation packaging structure and a forming method thereof, wherein micro flow channels are arranged on six sides of a chip in the chip heat dissipation packaging structure, so that six sides of the chip can be dissipated, and heat can be directly and rapidly transferred outwards by directly contacting a heating surface of the chip by utilizing a metal heat conducting rod, so that the chip with higher heat flux density can be comprehensively dissipated.
In a first aspect of the present invention, the present invention provides a chip heat dissipation package structure, including:
a micro flow channel cover plate arranged above the chip and configured to radiate heat for the chip and protect the chip;
the lower micro-channel plate is connected with the micro-channel cover plate and is configured to perform multi-surface heat dissipation on the chip;
a chip disposed in the lower micro flow channel plate;
and the substrate structure is connected with the lower micro-channel plate.
Further, the micro flow channel cover plate includes:
a first wafer having a first microchannel groove;
the second wafer is provided with a second micro-channel groove, wherein the second wafer is bonded with the first wafer, and the first micro-channel groove and the second micro-channel groove are combined to form a first micro-channel structure;
the first liquid inlet penetrates through the second wafer and is communicated with the first micro-channel structure;
the first liquid outlet penetrates through the second wafer and is communicated with the first micro-channel structure;
and the first through hole penetrates through the first wafer and the second wafer.
Further, the lower micro flow channel plate includes:
a third wafer;
a recess located on the front side of the third wafer;
a third microchannel groove positioned on the back surface of the third wafer;
a conductive through silicon via penetrating the third wafer;
the third through hole is positioned below the groove and communicated with the groove;
the second liquid inlet penetrates through the third wafer and is communicated with the first liquid inlet;
the second liquid outlet penetrates through the third wafer and is communicated with the first liquid outlet.
Further, the substrate structure includes: a substrate;
the total liquid inlet is positioned on the back surface of the substrate;
the liquid inlet branches are positioned on the front surface of the substrate and are communicated with the total liquid inlet;
the total liquid outlet is positioned on the back surface of the substrate;
the liquid outlet branches are positioned on the front surface of the substrate and are communicated with the total liquid outlet;
a fourth through hole penetrating the substrate and coaxial with the third through hole;
and a second redistribution line disposed on the front surface of the substrate.
Further, the method further comprises the following steps:
the first heat conduction structure is connected with the micro-channel cover plate and the lower micro-channel plate;
the first sealing structure is connected with the micro-channel cover plate and the lower micro-channel plate and is configured to seal the liquid inlet and the liquid outlet;
the first heat conduction rod is inserted into the micro-channel cover plate and the first heat conduction structure through the first through hole and the second through hole;
the second sealing structure is connected with the lower micro-channel plate and the substrate structure and is configured to seal the liquid inlet and the liquid outlet;
the second heat conduction structure is connected with the lower micro-channel plate and the substrate structure;
the second heat conduction rod is inserted into the lower micro-channel plate and the substrate structure through the third through hole and the fourth through hole and is contacted with the back surface of the chip.
Further, the method further comprises the following steps:
an insulating layer disposed on the front surface of the lower micro flow channel plate and in a gap between the chip and the groove sidewall;
the first rewiring is arranged on the front surface of the lower micro-channel plate and is electrically connected with the chip and the conductive through silicon vias;
and a dielectric layer disposed on the insulating layer and covering the first re-wiring.
In a second aspect of the present invention, the present invention provides a method for forming a heat dissipation package structure of a chip, including:
preparing a micro-channel cover plate;
preparing a lower micro-channel plate, arranging a chip in the lower micro-channel plate, and then connecting the micro-channel cover plate with the lower micro-channel plate;
and connecting the prepared lower micro-channel plate with a substrate structure.
Further, the preparing the micro flow channel cover plate includes:
etching a first micro-channel groove and a second micro-channel groove on the front surfaces of a first wafer and a second wafer respectively through dry etching, and then bonding the front surfaces of the first wafer and the second wafer, wherein the first micro-channel groove and the second micro-channel groove are combined to form a first micro-channel;
etching a first liquid inlet and a first liquid outlet for cooling liquid to enter and exit from the back of the second wafer, and preparing a first sealing ring and a first metal heat conduction pad on the back of the second wafer;
manufacturing a first through hole penetrating through the first wafer and the second wafer and a second through hole penetrating through the first metal heat conducting pad; and/or
The preparation of the lower micro-channel plate, the arrangement of chips in the lower micro-channel plate, and the connection of the micro-channel cover plate and the lower micro-channel plate comprise the following steps:
etching a groove on the front surface of the third wafer, arranging the chip in the groove, and arranging an insulating layer in a gap between the chip and the groove and the front surface of the third wafer;
etching the insulating layer to form a circuit pattern, and electroplating metal filling the circuit pattern to obtain a first rewiring which is electrically connected with the chip and the conductive through silicon vias in the third wafer;
preparing a second sealing ring and a second metal heat conduction pad on the front surface of the third wafer, and manufacturing a second through hole penetrating through the second metal heat conduction pad;
etching a third micro-channel groove on the back surface of the third wafer by dry etching, and manufacturing a third through hole on the back surface of the third wafer;
preparing a third sealing ring and a third metal heat conduction pad on the back surface of the third wafer;
and bonding the first metal heat conduction pad and the second metal heat conduction pad, and bonding the first sealing ring and the second sealing ring to connect the micro-channel cover plate with the lower micro-channel plate.
Further, the connecting the prepared lower micro flow channel plate with the substrate structure includes:
preparing a fourth sealing ring and a fourth metal heat conduction pad on the front surface of the substrate structure;
connecting the third sealing ring with the fourth sealing ring, and connecting the third metal heat conduction pad with the fourth metal heat conduction pad to connect the lower micro-channel plate with the substrate structure, wherein the substrate structure comprises:
a substrate;
the total liquid inlet is positioned on the back surface of the substrate;
the liquid inlet branches are positioned on the front surface of the substrate and are communicated with the total liquid inlet, the second liquid inlet and the third micro-channel groove;
the total liquid outlet is positioned on the back surface of the substrate;
the liquid outlet branches are positioned on the front surface of the substrate and are communicated with the total liquid outlet, the second liquid outlet and the third micro-channel groove;
a fourth through hole penetrating the substrate and coaxial with the third through hole;
and a second redistribution line disposed on the front surface of the substrate.
Further, the method further comprises the following steps:
inserting the first heat conducting rod into the micro-channel cover plate and the first heat conducting structure;
and inserting the second heat conduction rod into the lower micro-channel plate and the substrate structure.
The invention has at least the following beneficial effects: the six sides of the chip are provided with micro-channels, so that six sides of the chip can be subjected to heat radiation, and the heat can be more directly and rapidly transferred outwards by directly contacting a heating surface of the chip through the metal heat conducting rod, so that the chip with higher heat flux density can be subjected to comprehensive heat radiation; the micro-channel cover plate is utilized, so that the heat dissipation function is enhanced, and meanwhile, the active chip can be protected; the total liquid inlet, the total liquid outlet, the liquid inlet branch and the liquid outlet branch are arranged in the substrate, so that the smooth injection and outflow of the cooling liquid can be realized, the additionally arranged metal module is omitted, and the packaging size can be greatly reduced.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
FIG. 1 is a schematic diagram of a prior art silicon-based fan-out package with integrated heat spreading structure; and
fig. 2 is a schematic cross-sectional view of a chip heat dissipation package structure according to an embodiment of the invention.
Detailed Description
It should be noted that the components in the figures may be shown exaggerated for illustrative purposes and are not necessarily to scale.
In the present invention, the embodiments are merely intended to illustrate the scheme of the present invention, and should not be construed as limiting.
In the present invention, the adjectives "a" and "an" do not exclude a scenario of a plurality of elements, unless specifically indicated.
It should also be noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that the components or assemblies may be added as needed for a particular scenario under the teachings of the present invention.
It should also be noted herein that, within the scope of the present invention, the terms "identical", "equal" and the like do not mean that the two values are absolutely equal, but rather allow for some reasonable error, that is, the terms also encompass "substantially identical", "substantially equal".
It should also be noted herein that in the description of the present invention, the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not explicitly or implicitly indicate that the apparatus or element in question must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as limiting or implying any relative importance.
In addition, the embodiments of the present invention describe the process steps in a specific order, however, this is only for convenience of distinguishing the steps, and not for limiting the order of the steps, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
Fig. 1 shows a schematic structure diagram of a silicon-based fan-out package of a conventional integrated heat dissipation structure.
As shown in fig. 1, the existing silicon-based fan-out package structure integrated with a heat dissipation structure comprises a silicon substrate 1, wherein the silicon substrate is provided with a first surface and a second surface, the first surface of the silicon substrate is provided with a groove extending towards the second surface, a chip 2 is arranged in the groove through an adhesion layer 6, a bonding pad is arranged on a bonding pad surface of the chip, at least one bonding pad is electrically fanned onto the first surface of the silicon substrate through a conductive fan-out structure 3, and the second surface of the silicon substrate is directly provided with the heat dissipation structure. The conductive fan-out structure includes a dielectric layer 301, solder balls 302, metal wiring 303, and passivation layer 304. The heat dissipation structure comprises a plurality of micro-channels 4 which are directly manufactured on the second surface of the silicon substrate and are arranged at intervals. The micro-channels include a first micro-channel 401 located above the bottom of the groove and a second micro-channel 402 located outside the extension of the side walls of the groove. The heat dissipation structure fabricated on the second surface of the silicon substrate is suitable for air cooling (natural or forced convection).
The heat radiation structure is suitable for air cooling, has limited heat radiation capacity, is only positioned on one side of the chip, cannot carry out multi-surface heat radiation on the chip, and is not suitable for chips with higher heat flux density.
The invention provides a chip heat dissipation packaging structure, which is characterized in that micro flow channels are arranged on six sides of a chip, so that six sides of the chip can be dissipated, heat can be directly and rapidly transferred outwards by directly contacting a heating surface of the chip by utilizing a metal heat conducting rod, and the chip with higher heat flux can be comprehensively dissipated.
Fig. 2 is a schematic cross-sectional view of a chip heat dissipation package structure according to an embodiment of the invention.
As shown in fig. 2, a chip heat dissipation package structure includes: the micro-channel plate comprises a micro-channel cover plate, a first heat conduction structure, a first heat conduction rod, a lower micro-channel plate, a chip, an insulating layer, a first rewiring, a first sealing structure, a medium layer, a substrate structure, a second sealing structure, a second heat conduction structure and a second heat conduction rod.
The micro flow channel cover plate is arranged above the chip and is configured to radiate heat for the chip and protect the chip. The fluidic channel cover plate comprises a first wafer 10 with a first fluidic channel 11 and a second wafer 12 with a second fluidic channel 13. Wherein the first wafer 10 and the second wafer 12 are bonded, and the first micro flow channel groove 11 and the second micro flow channel groove 13 are combined to form a first micro flow channel structure. The micro-channel cover plate further comprises a first liquid inlet 14 and a first liquid outlet 15, and the first liquid inlet 14 and the first liquid outlet 15 penetrate through the second wafer and are communicated with the first micro-channel structure. The first liquid inlet 14 and the first liquid outlet 15 are located at two sides of the second wafer 12. The micro-channel cover plate further comprises a first through hole penetrating through the first wafer and the second wafer.
The first heat conducting structure 16 connects the micro flow channel cover plate with the lower micro flow channel plate. The first thermally conductive structure 16 has a second through hole, wherein the first through hole is coaxial with the second through hole. The first heat conducting structure 16 is connected to the second wafer 12 and the lower micro flow channel plate. The first thermally conductive structure 16 includes a first metal thermal pad on the back side of the second wafer and a second metal thermal pad on the front side of the lower micro-fluidic channel plate. The first metal heat conduction pad and the second metal heat conduction pad are connected to form a first heat conduction structure.
The first heat conduction rod 17 is inserted into the micro flow channel cover plate and the first heat conduction structure 16 through the first through hole and the second through hole.
The lower micro flow channel plate is configured to multi-face heat dissipation to the chip. The lower micro fluidic channel plate comprises a third wafer 18; a recess located on the front side of the third wafer 18; a third microchannel groove 19 located on the back surface of the third wafer 18; a conductive through silicon via 20 extending through the third wafer; the third through hole is positioned below the groove and communicated with the groove; a second liquid inlet 21 penetrating the third wafer 18 and communicating with the first liquid inlet 14; the second liquid outlet 22 penetrates through the third wafer and is communicated with the first liquid outlet 15. The second liquid inlet 21 and the second liquid outlet 22 are positioned at two sides of the third micro-channel groove. The third microchannel grooves 19 are positioned below and around the grooves.
The chip 23 is arranged in a recess of the lower micro flow channel plate.
The insulating layer is arranged on the front surface of the lower micro-channel plate and is used for forming a gap between the chip and the side wall of the groove.
The first rewiring is disposed on the front side of the lower micro-fluidic channel plate and electrically connected to the chip 23 and the conductive through-silicon vias 20.
The first sealing structure 24 connects the micro flow channel cover plate and the lower micro flow channel plate, and is configured to seal the liquid inlet and the liquid outlet. The 2 first sealing structures 24 are respectively communicated with the first liquid inlet 14, the second liquid inlet 21, the first liquid outlet 15 and the second liquid outlet 22. The first seal structure 24 includes a first seal ring located on the back side of the second wafer and a second seal ring located on the front side of the lower micro fluidic channel plate. The first sealing ring and the second sealing ring are connected to form a first sealing structure.
The dielectric layer is disposed on the insulating layer and covers the first re-wiring. The first heat conducting structure 16 is connected with the dielectric layer and the second wafer 12; the first seal structure 24 is connected to the dielectric layer and the second wafer 12.
The substrate structure and the lower micro flow channel plate are connected through a second sealing structure 25 and a second heat conducting structure 26.
A substrate structure is connected with the lower micro-fluidic channel, the substrate structure comprising a substrate 27; a total liquid inlet 28 located on the back surface of the substrate 27; a plurality of liquid inlet branches 29 which are positioned on the front surface of the base plate 27 and are communicated with the total liquid inlet 28; a total liquid outlet 30 located on the back surface of the substrate 27; a plurality of liquid outlet branches 31, which are positioned on the front surface of the base plate 27 and are communicated with the total liquid outlet 30; a fourth through hole penetrating the substrate 27 and coaxial with the third through hole; the second redistribution line 32 is disposed on the front side of the substrate. The plurality of liquid inlet branches 29 are respectively communicated with the second liquid inlet 21 and the third microchannel groove 19. The plurality of liquid outlet branches 31 are respectively communicated with the second liquid outlet 22 and the third micro-channel groove 19.
The second sealing structure 25 connects the back surface of the lower micro flow channel plate with the front surface of the substrate structure. The second sealing structure 25 includes a third sealing ring located on the back surface of the lower micro flow channel plate and a fourth sealing ring located on the front surface of the substrate structure. The third sealing ring and the fourth sealing ring are connected in a looped manner to form a second sealing structure. The second sealing structure 25 connects the second redistribution line 32 on the front side of the substrate structure. The second sealing structure 25 is located between the liquid inlet branch 29 and the second liquid inlet 21 or between the liquid outlet branch 31 and the second liquid outlet 22, so that at least one liquid inlet branch is communicated with the second liquid inlet and at least one liquid outlet branch is communicated with the second liquid outlet.
The second thermally conductive structure 26 connects the back side of the lower micro-fluidic channel plate with the front side of the substrate structure and with the conductive through-silicon vias 20. The second thermal conductive structure 26 includes a third metal thermal conductive pad located on the back side of the lower micro-fluidic channel plate and a fourth metal thermal conductive pad located on the front side of the substrate structure. The third metal heat conduction pad and the fourth metal heat conduction pad are connected to form a second heat conduction structure. The second thermally conductive structure 26 is electrically connected to the second redistribution line 32.
The lower micro-channel plate is connected with the substrate structure below, and the third micro-channel groove 19 is sealed by the substrate structure and the second heat conduction structure, so that the second micro-channel structure is formed.
The second heat conductive rod 33 is inserted into the substrate structure and the lower micro flow channel plate through the third through hole and the fourth through hole, and contacts the back surface of the chip. The second heat conduction rod can transfer the heat of the chip to the outside more directly and rapidly.
The cooling liquid enters from the main liquid inlet and is divided into a plurality of paths through the liquid inlet branch; at least one path of cooling liquid enters the second liquid inlet, flows into the first micro-channel structure through the first liquid inlet, flows out of the first liquid outlet, enters the liquid outlet branch through the second liquid outlet, and finally flows out of the main liquid outlet; at least one path of cooling liquid enters the third micro-channel groove and then flows out from the liquid outlet branch into the total liquid outlet.
The chip in the chip heat dissipation packaging structure is surrounded by six sides of the micro-channel structure, six sides of heat dissipation can be realized, and enough heat dissipation capacity is provided for the chip.
The forming method of the fan-out packaging structure comprises the following steps:
and step 1, preparing a micro-channel cover plate. Firstly, etching a first micro-channel groove and a second micro-channel groove on the front surfaces of a first wafer and a second wafer respectively through dry etching, and then bonding the front surfaces of the first wafer and the second wafer, wherein the first micro-channel groove and the second micro-channel groove are combined to form a first micro-channel; etching a first liquid inlet and a first liquid outlet for cooling liquid to enter and exit from the back of the second wafer, and preparing a first sealing ring and a first metal heat conduction pad on the back of the second wafer through electroplating and other processes; then, first through holes penetrating the first wafer and the second wafer and second through holes penetrating the first metal heat conducting pad are manufactured. Firstly, photoresist is arranged on the back surface of the second wafer, then a pattern is formed by photoetching, a first sealing ring and a first metal heat conduction pad are formed by filling metal in the pattern through electroplating, and finally, the photoresist is removed.
And 2, preparing a lower micro-channel plate, arranging chips in the lower micro-channel plate, and then connecting the micro-channel cover plate with the lower micro-channel plate. Etching a groove on the front surface of the third wafer, arranging the chip in the groove, and arranging an insulating layer in a gap between the chip and the groove and the front surface of the third wafer; etching the insulating layer to form a circuit pattern, and electroplating metal filling the circuit pattern to obtain a first rewiring which is electrically connected with the chip and the conductive through silicon vias in the third wafer; preparing a second sealing ring and a second metal heat conduction pad on the front surface of the third wafer through electroplating and other processes, and manufacturing a second through hole penetrating through the second metal heat conduction pad; etching a third micro-channel groove on the back surface of the third wafer by dry etching, and manufacturing a third through hole on the back surface of the third wafer, wherein the third micro-channel groove is distributed around and below the chip; and preparing a third sealing ring and a third metal heat conduction pad on the back surface of the third wafer through electroplating and other processes. And bonding the first metal heat conduction pad and the second metal heat conduction pad, and bonding the first sealing ring and the second sealing ring to connect the micro-channel cover plate with the lower micro-channel plate. The first metal heat conduction pad and the second metal heat conduction pad are bonded to form a first heat conduction structure. The first sealing ring and the second sealing ring are bonded to form a first sealing structure.
And 3, connecting the prepared lower micro-channel plate with the substrate structure through a second sealing structure and a second heat conduction structure. Preparing a fourth sealing ring and a fourth metal heat conduction pad on the front surface of the substrate structure; and connecting the third sealing ring with the fourth sealing ring, and connecting the third metal heat conduction pad with the fourth metal heat conduction pad so as to connect the lower micro-channel plate with the substrate structure. The third metal heat conduction pad and the fourth metal heat conduction pad are bonded to form a second heat conduction structure. The third sealing ring and the fourth sealing ring are bonded to form a second sealing structure. The substrate structure includes: a substrate; the total liquid inlet is positioned on the back surface of the substrate; the liquid inlet branches are positioned on the front surface of the substrate and are communicated with the total liquid inlet; the total liquid outlet is positioned on the back surface of the substrate; the liquid outlet branches are positioned on the front surface of the substrate and are communicated with the total liquid outlet; a fourth through hole penetrating the substrate and coaxial with the third through hole; and a second redistribution line disposed on the front surface of the substrate. The liquid inlet branches are respectively communicated with the second liquid inlet and the third micro-channel groove. The liquid outlet branches are respectively communicated with the second liquid outlet and the third micro-channel groove.
And 4, inserting the first heat conduction rod into the micro-channel cover plate and the first heat conduction structure. The first heat conduction rod is inserted into the micro-channel cover plate through the first through hole and is inserted into the first heat conduction structure through the second through hole.
And 5, inserting the second heat conduction rod into the substrate structure and the lower micro-channel plate through the fourth through hole and the third through hole.
The invention has at least the following beneficial effects: the six sides of the chip are provided with micro-channels, so that six sides of the chip can be subjected to heat radiation, and the heat can be more directly and rapidly transferred outwards by directly contacting a heating surface of the chip through the metal heat conducting rod, so that the chip with higher heat flux density can be subjected to comprehensive heat radiation; the micro-channel cover plate is utilized, so that the heat dissipation function is enhanced, and meanwhile, the active chip can be protected; the total liquid inlet, the total liquid outlet, the liquid inlet branch and the liquid outlet branch are arranged in the substrate, so that the smooth injection and outflow of the cooling liquid can be realized, the additionally arranged metal module is omitted, and the packaging size can be greatly reduced.
While certain embodiments of the present invention have been described herein, those skilled in the art will appreciate that these embodiments are shown by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the present teachings without departing from the scope of the invention. The appended claims are intended to define the scope of the invention and to cover such methods and structures within the scope of these claims themselves and their equivalents.
Claims (10)
1. The utility model provides a chip heat dissipation packaging structure which characterized in that includes:
a micro flow channel cover plate arranged above the chip and configured to radiate heat for the chip and protect the chip;
the lower micro-channel plate is connected with the micro-channel cover plate and is configured to perform multi-surface heat dissipation on the chip;
a chip disposed in the lower micro flow channel plate;
and the substrate structure is connected with the lower micro-channel plate.
2. The chip heat dissipation package as defined in claim 1, wherein the micro flow channel cover plate comprises:
a first wafer having a first microchannel groove;
the second wafer is provided with a second micro-channel groove, wherein the second wafer is bonded with the first wafer, and the first micro-channel groove and the second micro-channel groove are combined to form a first micro-channel structure;
the first liquid inlet penetrates through the second wafer and is communicated with the first micro-channel structure;
the first liquid outlet penetrates through the second wafer and is communicated with the first micro-channel structure;
and the first through hole penetrates through the first wafer and the second wafer.
3. The chip heat dissipation package as defined in claim 2, wherein the lower micro flow channel plate comprises:
a third wafer;
a recess located on the front side of the third wafer;
a third microchannel groove positioned on the back surface of the third wafer;
a conductive through silicon via penetrating the third wafer;
the third through hole is positioned below the groove and communicated with the groove;
the second liquid inlet penetrates through the third wafer and is communicated with the first liquid inlet;
the second liquid outlet penetrates through the third wafer and is communicated with the first liquid outlet.
4. The chip heat spreader package as recited in claim 3, wherein the substrate structure comprises: a substrate;
the total liquid inlet is positioned on the back surface of the substrate;
the liquid inlet branches are positioned on the front surface of the substrate and are communicated with the total liquid inlet;
the total liquid outlet is positioned on the back surface of the substrate;
the liquid outlet branches are positioned on the front surface of the substrate and are communicated with the total liquid outlet;
a fourth through hole penetrating the substrate and coaxial with the third through hole;
and a second redistribution line disposed on the front surface of the substrate.
5. The chip heat spreader package as recited in claim 4, further comprising:
the first heat conduction structure is connected with the micro-channel cover plate and the lower micro-channel plate;
the first sealing structure is connected with the micro-channel cover plate and the lower micro-channel plate and is configured to seal the liquid inlet and the liquid outlet;
the first heat conduction rod is inserted into the micro-channel cover plate and the first heat conduction structure through the first through hole and the second through hole;
the second sealing structure is connected with the lower micro-channel plate and the substrate structure and is configured to seal the liquid inlet and the liquid outlet;
the second heat conduction structure is connected with the lower micro-channel plate and the substrate structure;
the second heat conduction rod is inserted into the lower micro-channel plate and the substrate structure through the third through hole and the fourth through hole and is contacted with the back surface of the chip.
6. The chip heat spreader package as recited in claim 4, further comprising:
an insulating layer disposed on the front surface of the lower micro flow channel plate and in a gap between the chip and the groove sidewall;
the first rewiring is arranged on the front surface of the lower micro-channel plate and is electrically connected with the chip and the conductive through silicon vias;
and a dielectric layer disposed on the insulating layer and covering the first re-wiring.
7. The method for forming the chip heat dissipation packaging structure is characterized by comprising the following steps of:
preparing a micro-channel cover plate;
preparing a lower micro-channel plate, arranging a chip in the lower micro-channel plate, and then connecting the micro-channel cover plate with the lower micro-channel plate;
and connecting the prepared lower micro-channel plate with a substrate structure.
8. The method for forming a heat dissipation package structure of a chip as defined in claim 7, wherein the preparing a micro flow channel cover plate comprises:
etching a first micro-channel groove and a second micro-channel groove on the front surfaces of a first wafer and a second wafer respectively through dry etching, and then bonding the front surfaces of the first wafer and the second wafer, wherein the first micro-channel groove and the second micro-channel groove are combined to form a first micro-channel;
etching a first liquid inlet and a first liquid outlet for cooling liquid to enter and exit from the back of the second wafer, and preparing a first sealing ring and a first metal heat conduction pad on the back of the second wafer;
manufacturing a first through hole penetrating through the first wafer and the second wafer and a second through hole penetrating through the first metal heat conducting pad; and/or
The preparation of the lower micro-channel plate, the arrangement of chips in the lower micro-channel plate, and the connection of the micro-channel cover plate and the lower micro-channel plate comprise the following steps:
etching a groove on the front surface of the third wafer, arranging the chip in the groove, and arranging an insulating layer in a gap between the chip and the groove and the front surface of the third wafer;
etching the insulating layer to form a circuit pattern, and electroplating metal filling the circuit pattern to obtain a first rewiring which is electrically connected with the chip and the conductive through silicon vias in the third wafer;
preparing a second sealing ring and a second metal heat conduction pad on the front surface of the third wafer, and manufacturing a second through hole penetrating through the second metal heat conduction pad;
etching a third micro-channel groove on the back surface of the third wafer by dry etching, and manufacturing a third through hole on the back surface of the third wafer;
preparing a third sealing ring and a third metal heat conduction pad on the back surface of the third wafer;
and bonding the first metal heat conduction pad and the second metal heat conduction pad, and bonding the first sealing ring and the second sealing ring to connect the micro-channel cover plate with the lower micro-channel plate.
9. The method of claim 8, wherein the connecting the prepared lower micro flow channel plate with the substrate structure comprises:
preparing a fourth sealing ring and a fourth metal heat conduction pad on the front surface of the substrate structure;
connecting the third sealing ring with the fourth sealing ring, and connecting the third metal heat conduction pad with the fourth metal heat conduction pad to connect the lower micro-channel plate with the substrate structure, wherein the substrate structure comprises:
a substrate;
the total liquid inlet is positioned on the back surface of the substrate;
the liquid inlet branches are positioned on the front surface of the substrate and are communicated with the total liquid inlet, the second liquid inlet and the third micro-channel groove;
the total liquid outlet is positioned on the back surface of the substrate;
the liquid outlet branches are positioned on the front surface of the substrate and are communicated with the total liquid outlet, the second liquid outlet and the third micro-channel groove;
a fourth through hole penetrating the substrate and coaxial with the third through hole;
and a second redistribution line disposed on the front surface of the substrate.
10. The method of forming a heat spreader package according to claim 9, further comprising:
inserting the first heat conducting rod into the micro-channel cover plate and the first heat conducting structure;
and inserting the second heat conduction rod into the lower micro-channel plate and the substrate structure.
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| Application Number | Priority Date | Filing Date | Title |
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