CN116013769A - Wafer structure and method for regulating and controlling wafer curvature thereof - Google Patents

Abstract

The invention provides a wafer structure and a method for regulating and controlling the curvature of a wafer, wherein the method for regulating and controlling the curvature of the wafer comprises the following steps: providing a wafer comprising a dielectric layer and a wiring layer, measuring the curvature value of the wafer by using a curvature measuring instrument, obtaining a difference value between the curvature value and a preset curvature value, forming a curvature correction layer for generating corresponding stress based on the difference value, repeating the steps of measuring the curvature value of the wafer and forming the curvature correction layer for corresponding stress based on the difference value until the difference value is zero, and conveying the wafer with the zero difference value to the next process section. According to the invention, the curvature value of the wafer after the subsequent polishing process is measured, the corresponding stress curvature correction layer is formed based on the difference value between the curvature value and the preset curvature value, and the steps of measuring the curvature value and forming the curvature correction layer based on the difference value are repeated until the wafer is flat, so that the photoetching alignment of the subsequent process is ensured, the performance of devices in the wafer is ensured, and the yield of the wafer of the subsequent process is improved.

Description

Wafer structure and method for regulating and controlling wafer curvature thereof

Technical Field

The invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a wafer structure and a method for regulating and controlling wafer bending thereof.

Background

Along with the improvement of the integrated circuit integration level, the doped region, the metal interconnection layer and the dielectric film layer formed in the wafer are increased, so that the stress on each part of the wafer is uneven, the wafer is deformed, and the surface of the wafer becomes uneven, namely, warpage occurs. As shown in fig. 1 and 2, the schematic structural diagram of wafer bending in the back-end process and the schematic sectional structural diagram of the stacked structure in the wafer respectively include a wafer 01, a first dielectric layer 011, a first wiring layer 012, a first etching stop layer 02, a first nitrogen-doped silicon carbide layer 021, a first barrier layer 022, a second dielectric layer 03, a second wiring layer 031, a second etching stop layer 04, a second nitrogen-doped silicon carbide layer 041, a second barrier layer 042, a third dielectric layer 05 and a third wiring layer 051, and the combined action of the stress in the dielectric layer and the wiring layer makes the whole structure of the wafer show a middle-downward protruding bending due to the tensile stress characteristic of the nitrogen-doped silicon carbide layer in general cases, so that the wafer is warped. The warpage can cause a plurality of problems, in the process of fixing the wafer by using the adsorption tool, the wafer is difficult to adsorb and fix, the process cannot be carried out, the stacked film layer falls off, the wafer breaks, the layout alignment performance of the later stage process is unstable, the photoetching precision is poor, the photoetching pattern is deformed, the product performance is unstable, and the product yield and the yield are reduced.

Therefore, there is an urgent need to find a method for adjusting and controlling wafer bow to correct wafer bow, ensure lithography alignment, and avoid pattern deformation.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a wafer structure and a method for adjusting and controlling the bending degree of a wafer, which are used for solving the problems of difficult alignment of a photolithography layout, deformation of a pattern, and difficulty in adsorbing equipment during a subsequent process step caused by bending of a wafer after multi-layer wiring in the prior art.

To achieve the above and other related objects, the present invention provides a method for controlling wafer bow, comprising the steps of:

providing a wafer, wherein the wafer comprises a dielectric layer and a wiring layer embedded in the upper surface layer of the dielectric layer, and the dielectric layer is positioned on the upper surface layer of the wafer;

providing a wafer bending degree measuring instrument, measuring a bending value of the surface of the wafer, which reveals the wiring layer, by using the wafer bending degree measuring instrument, and comparing the bending value with a preset bending value to obtain a difference value between the bending value and the preset bending value;

judging the numerical value of the difference, when the difference is not equal to zero, placing the wafer in a film plating device, forming a curvature correction layer covering the dielectric layer on the upper surface of the wafer, wherein the curvature correction layer comprises at least one of a first correction layer and a second correction layer, the difference is smaller than zero, forming a first correction layer above the wafer, the difference is larger than zero, and forming a second correction layer above the wafer;

repeating the steps of obtaining the difference value and forming the curvature correction layer based on the difference value until the difference value is equal to zero;

and when the difference value is zero, conveying the wafer with the zero difference value to the next working procedure.

Optionally, the preset curvature value is zero.

Optionally, the material of the first correction layer includes nitrogen doped silicon carbide, and the type of stress generated by the first correction layer is compressive stress.

Optionally, the difference is smaller than zero, and based on the absolute value of the difference, the compressive stress required for correcting the curvature value of the wafer is estimated, so as to adjust the curvature of the wafer to enable the surface of the wafer to tend to be flattened.

Optionally, the magnitude of the compressive stress generated by the first correction layer is regulated and controlled by adjusting the power, the reaction temperature, the reaction pressure and the proportion of the gas components forming the first correction layer of the coating equipment.

Optionally, the material of the second dielectric layer includes nitrogen doped silicon carbide, and the type of stress generated by the first correction layer is tensile stress.

Optionally, the difference is greater than zero, and based on the absolute value of the difference, the tensile stress required for correcting the wafer bow is estimated to adjust the bow of the wafer 1 and to planarize the surface of the wafer.

Optionally, the tensile stress generated by the second correction layer is regulated and controlled by adjusting the power, the reaction temperature, the reaction pressure and the proportion of the gas components forming the second correction layer of the coating equipment.

Optionally, after repeatedly measuring the difference, the difference is changed from less than zero to greater than zero, and the second correction layer with a preset thickness is formed above the wafer, so as to planarize the wafer.

The invention also provides a wafer structure, which comprises:

the wafer comprises a dielectric layer and a wiring layer embedded in the dielectric layer, wherein the dielectric layer is positioned on the upper surface layer of the wafer;

and the curvature correction layer comprises at least one of a first correction layer and a second correction layer.

As described above, in the wafer structure and the method for controlling wafer bow thereof according to the present invention, the difference between the bow value and the preset bow value is obtained by measuring the bow value of the wafer, the bow correction layer is formed based on the difference, the bow correction layer includes at least one of the first correction layer generating compressive stress and the second correction layer generating tensile stress, and the bow value of the wafer after the bow correction layer is formed is measured again to obtain a new difference, the corresponding bow correction layer is formed based on the difference again, and the steps of measuring the bow value of the wafer and forming the bow correction layer based on the difference are repeated until the value of the difference is zero, so that the wafer is flat, the bow of the wafer is corrected, the process precision and the photolithography alignment of the subsequent process are ensured, the performance of devices in the wafer is ensured, the yield of the wafer in the subsequent process is improved, and simultaneously, the problem of difficulty in using equipment for the subsequent process of the wafer is solved due to the high industrial warp value.

Drawings

Fig. 1 is a schematic view of a wafer bending structure in a back-end process.

Fig. 2 is a schematic cross-sectional view of a stacked structure in a wafer.

FIG. 3 is a process flow diagram of a method for controlling wafer bow in accordance with the present invention.

Fig. 4 is a schematic cross-sectional view of a dielectric layer of a method for controlling wafer bow according to the present invention.

Fig. 5 is a schematic cross-sectional view illustrating a wafer bow control method according to the present invention after forming a first correction layer.

Fig. 6 is a schematic cross-sectional view of a wafer after forming a second correction layer according to the method for controlling wafer bow of the present invention.

Fig. 7 is a schematic structural diagram of a wafer after forming a correction layer according to the method for controlling wafer bow of the present invention.

Description of the reference numerals

01. Wafer with a plurality of wafers

01. A first dielectric layer

011. First wiring layer

02. First etching stop layer

021. First nitrogen-doped silicon carbide layer

022. First barrier layer

03. Second dielectric layer

031. Second wiring layer

04. Second etching stop layer

041. Second nitrogen-doped silicon carbide layer

042. Second barrier layer

05. Third dielectric layer

051. Third wiring layer

1. Wafer with a plurality of wafers

11. Dielectric layer

12. Wiring layer

2. Curvature correction layer

21. First correction layer

22. Second correction layer

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 3 to fig. 7. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Example 1

The embodiment provides a method for adjusting and controlling the bending of a wafer, as shown in fig. 3, which is a process flow chart of the method for adjusting and controlling the bending of the wafer, and includes the following steps:

s1: providing a wafer, wherein the wafer comprises a dielectric layer and a wiring layer embedded in the upper surface layer of the dielectric layer, and the dielectric layer is positioned on the upper surface layer of the wafer;

s2: providing a wafer bending degree measuring instrument, measuring a bending value of the surface of the wafer, which reveals the wiring layer, by using the wafer bending degree measuring instrument, and comparing the bending value with a preset bending value to obtain a difference value between the bending value and the preset bending value;

s3: judging the numerical value of the difference, when the difference is not equal to zero, placing the wafer in a film plating device, forming a curvature correction layer covering the dielectric layer on the upper surface of the wafer, wherein the curvature correction layer comprises at least one of a first correction layer and a second correction layer, the difference is smaller than zero, forming a first correction layer above the wafer, the difference is larger than zero, and forming a second correction layer above the wafer;

s4: repeating the steps of obtaining the difference value and forming the curvature correction layer based on the difference value until the difference value is equal to zero;

s5: and when the difference value is zero, conveying the wafer with the zero difference value to the next working procedure.

Referring to fig. 4, the steps S1 and S2 are performed: providing a wafer 1, wherein the wafer 1 comprises a dielectric layer 11 and a wiring layer 12 embedded in the upper surface layer of the dielectric layer 11, and the dielectric layer 11 is positioned on the upper surface layer of the wafer 1; and measuring a curvature value of the surface of the wafer 11, which exposes the wiring layer 12, by using a wafer curvature measuring instrument, and comparing the curvature value with a preset curvature value to obtain a difference value between the curvature value and the preset curvature value.

Specifically, as shown in fig. 4, the cross-sectional structure of the dielectric layer 11 is schematically shown, and the dielectric layer 11 includes an organic, inorganic or hybrid polymer with a dielectric constant less than 3.0, and may be any other suitable low-dielectric-constant dielectric material.

Specifically, a contact hole (not shown) is further provided in the dielectric layer 11, the contact hole penetrates through the dielectric layer 11, and the wiring layer 12 fills the contact hole.

Specifically, the opening size of the contact hole may be selected according to the actual situation, without limitation, while ensuring the device performance.

Specifically, the material of the wiring layer 12 includes titanium, titanium nitride, tantalum nitride, silver, gold, copper, aluminum, tungsten, or other suitable conductive material.

Specifically, the wafer bending degree measuring instrument is not damaged in the process of measuring the bending degree of the wafer 1, and the wafer bending degree measuring instrument can be a laser bending degree measuring instrument, an infrared bending degree measuring instrument and other suitable nondestructive measuring instruments. In this embodiment, a laser warp measuring apparatus is used to measure the curvature of the polished surface of the wafer 1, where the wiring layer 12 is exposed, so as to ensure the measurement efficiency and the measurement accuracy.

As an example, the preset curvature value is zero, that is, the wafer 1 has no warpage and a flat surface.

Specifically, in order to ensure the production efficiency, the preset curvature value may be a small floating range, for example, may be-1 μm to 1 μm, under the condition that the curvature degree of the wafer 1 is ensured to have no influence on the alignment of the lithography layout and the shape of the pattern.

Specifically, the preset curvature value is a range, the curvature value of the wafer 1 measured is within the range, the difference value is zero, when the curvature value of the wafer 1 is greater than the upper limit of the preset curvature value, the difference value is obtained by subtracting the upper limit of the preset curvature value from the curvature value, and when the curvature value of the wafer 1 is less than the lower limit of the preset curvature value, the difference value is obtained by subtracting the lower limit of the preset curvature value from the curvature value.

Referring to fig. 5 to fig. 7, the steps S3, S4 and S5 are performed: judging the value of the difference, when the difference is not equal to zero, placing the wafer 1 in a film plating device, forming a curvature correction layer 2 covering the dielectric layer 11 on the upper surface of the wafer 1, wherein the curvature correction layer 2 comprises at least one of a first correction layer 21 and a second correction layer 22, the difference is smaller than zero, forming a first correction layer 21 above the wafer 1, the difference is larger than zero, and forming a second correction layer 22 above the wafer 1; repeating the steps of obtaining the difference value and forming the curvature correction layer based on the difference value until the difference value is equal to zero; and when the difference value is zero, conveying the wafer 1 with the zero difference value to the next process.

Specifically, after the curvature correction layer 2 is required to be formed in batches in production to obtain the difference value, the method further comprises a step of screening the wafers 1 corresponding to the difference value, and the wafers 1 with similar difference values are screened into one batch, so that the curvature correction layer 2 is formed in batches, and the production efficiency is improved.

Specifically, under the condition of guaranteeing the performance of the device, the difference value is screened, zero can be used as a starting point, or the upper limit or the lower limit of the preset curvature value can be used as a starting point, the difference value is respectively oriented to the minimum value and the maximum value of the difference value and is divided into a plurality of interval sections, the wafer 1 with the difference value in the same interval section is screened into one batch, the wafer 1 is divided into a plurality of batches to form the curvature correction layer 2, the consistency of a later-stage process is guaranteed while the production efficiency is guaranteed, and then the performance of the device is guaranteed.

Specifically, the interval length of each of the intervals may be selected according to the actual situation, without limitation, while ensuring the device performance. The interval length here refers to the absolute value of the numerical difference between the upper limit of the interval section and the lower limit of the interval section.

Specifically, since the power during forming the film has a great influence on the stress characteristics of the film, the type of stress generated by the film can be changed by adjusting the power of the film, namely the film can be changed from the film generating compressive stress to the film generating tensile stress, the film can be changed from the film generating tensile stress to the film generating compressive stress by changing the pressure of the film, the pressure or the tensile stress generated by the film can be changed by adjusting the temperature, and the gas composition and the ratio of the film can be adjusted, so that the film is changed from the film generating tensile stress to the film generating compressive stress. Thus, the first correction layer 21 and the second correction layer 22 can be controlled by controlling the power, pressure, temperature, gas composition and ratio of the curvature correction layer 2.

As an example, the material of the first correction layer 21 includes silicon carbide doped with nitrogen or other suitable dielectric materials, and the type of stress generated by the first correction layer 21 is compressive stress, so as to correct tensile stress generated by each film layer in the wafer 1.

Specifically, the method of forming the first correction layer 21 includes chemical vapor deposition or other suitable methods. In this embodiment, the first correction layer 21 is formed by a plasma enhanced chemical vapor deposition (PECVD, one of chemical vapor deposition) method.

As an example, the difference is smaller than zero, and the range of compressive stress required for correcting the bow value of the wafer 1 is estimated based on the magnitude of the absolute value of the difference, so as to adjust the bow of the wafer 1 and make the wafer 1 tend to be flattened.

As an example, the magnitude of the compressive stress generated by the first correction layer 21 is regulated by adjusting the power, the reaction temperature, the reaction pressure of the coating apparatus, and the proportion of the gas components forming the first correction layer 21.

Specifically, since the deposition speed has an effect on the magnitude of the compressive stress generated by the first correction layer 21 during the formation of the first correction layer 21, and the dose of the doping particles in the first correction layer 21 has an effect on the magnitude of the compressive stress generated by the first correction layer 21, the magnitude of the compressive stress generated by the first correction layer 21 can be regulated by regulating the power of the coating apparatus and the proportion of the components forming the first correction layer 21, or the magnitude of the compressive stress generated by the first correction layer 21 can be regulated by regulating the power of the first correction layer 21, or the proportion of each component in the first correction layer 21 can be regulated. In this embodiment, a nitrogen doped silicon carbide (SiCN) film layer is used as the first correction layer 21, and the magnitude of the compressive stress generated by forming the first correction layer 21 is controlled by controlling the proportion of nitrogen doping and the power of the coating apparatus.

Specifically, in the process of forming the first correction layer 21, as the pressure of the formed first correction layer 21 gradually increases, the compressive stress generated by the first correction layer 21 becomes smaller and larger, when the compressive stress generated by the first correction layer 21 reaches a peak value, the magnitude of the compressive stress generated by the first correction layer 21 gradually decreases as the pressure increases, so that the magnitude of the compressive stress of the first correction layer 21 can be controlled by controlling the pressure of the formed first correction layer 21, the magnitude of the compressive stress generated by the first correction layer 21 can be controlled by controlling the pressure of the formed first correction layer 21 and the power of the coating device, the magnitude of the compressive stress generated by the first correction layer 21 can be controlled by controlling the pressure of the formed first correction layer 21 and the proportion of components in the first correction layer 21, and the magnitude of the compressive stress generated by the first correction layer 21 can also be controlled by controlling the pressure of the formed first correction layer 21, the power of the coating device, the temperature and the proportion of components in the first correction layer 21.

As an example, the material of the second dielectric layer 22 includes silicon carbide doped with nitrogen or other suitable dielectric materials, and the type of stress generated by the second correction layer 22 is tensile stress, so as to correct the compressive stress generated by each film layer in the wafer 1.

Specifically, the method of forming the second correction layer 22 includes chemical vapor deposition or other suitable method. In this embodiment, the second correction layer 22 is formed by a plasma enhanced chemical vapor deposition (PECVD, one of chemical vapor deposition) method.

As an example, the difference is smaller than zero, and based on the magnitude of the absolute value of the difference, the tensile stress required for correcting the bow value of the wafer 1 is estimated to adjust the bow of the wafer 1 and to make the surface of the wafer tend to be flat.

As an example, the tensile stress generated by the second correction layer 22 is controlled by adjusting the power, the reaction temperature, the reaction pressure of the coating apparatus, and the proportion of the gas components forming the second correction layer 22.

Specifically, since the deposition speed has an effect on the tensile stress generated by the second correction layer 22 during the formation of the second correction layer 22, and the concentration of the doping particles in the second correction layer 22 has an effect on the tensile stress generated by the second correction layer 22, the tensile stress generated by the second correction layer 22 can be regulated by regulating the power of the coating device and the proportion of the components forming the second correction layer 21, the tensile stress generated by the second correction layer 22 can be regulated by regulating the power of the second correction layer 22, or the tensile stress generated by the second correction layer 22 can be regulated by regulating the proportion of each component in the second correction layer 22. In this embodiment, since a nitrogen doped silicon carbide (SiCN) film layer is used as the second correction layer 22, the tensile stress generated by forming the second correction layer 22 is controlled by controlling the proportion of nitrogen doping and the power of the coating apparatus.

Specifically, in the process of forming the second correction layer 22, as the pressure of the formed second correction layer 22 gradually increases, the tensile stress generated by the second correction layer 22 is changed from small to large, when the tensile stress generated by the second correction layer 22 reaches a peak value, as the pressure increases, the magnitude of the compressive stress generated by the second correction layer 22 gradually decreases, so that the magnitude of the compressive stress of the second correction layer 22 can be controlled by controlling the pressure of the formed second correction layer 22, the magnitude of the tensile stress generated by the second correction layer 22 can be controlled by controlling the pressure of the formed second correction layer 22 and the power of the coating device, the magnitude of the tensile stress generated by the second correction layer 22 can be controlled by controlling the pressure of the formed second correction layer 22 and the proportion of components in the second correction layer 22, and the magnitude of the tensile stress generated by the second correction layer 22 can also be controlled by controlling the pressure of the formed second correction layer 22, the power of the temperature of the coating device and the proportion of components in the second correction layer 22.

As an example, as shown in fig. 5 and 6, the schematic cross-sectional structure after forming the first correction layer 21 and the schematic cross-sectional structure after forming the second correction layer 22 stacked on the upper surface of the first correction layer 21 are respectively, after repeatedly measuring the difference, the difference is changed from less than zero to greater than zero, and the second correction layer 22 with a predetermined thickness is formed above the wafer 1, so that the wafer tends to be planarized.

Specifically, since the difference is changed from less than zero to greater than zero, the compressive correction stress generated by the first correction layer 21 is greater than the tensile stress generated by each film layer in the wafer 1, so that the wafer 1 is raised upwards, the film layer generating tensile stress is required to correct the excessive compressive stress, and the second correction layer 22 generating tensile stress is formed on the upper surface of the first correction layer 21 to correct the excessive compressive stress generated by the first correction layer 21, so that the wafer 1 tends to be flat.

Specifically, after repeatedly measuring the difference, the difference is changed from greater than zero to less than zero, and the first correction layer 21 having a predetermined thickness is formed over the wafer 1, so that the wafer tends to be planarized.

Specifically, since the difference is changed from greater than zero to less than zero, the tensile correction stress generated by the two dielectric layers 22 is greater than the compressive stress generated by each film layer in the wafer 1 and the film layers stacked on the surface of the wafer, so that the wafer 1 is concave, the film layers generating the compressive stress are required to correct the excessive tensile stress, and the first correction layer 21 generating the compressive stress is formed on the upper surface of the second correction layer 22 to correct the excessive tensile stress generated by the second correction layer 22, so that the wafer 1 tends to be flat.

Specifically, after the difference is repeatedly measured, the wafer 1 needs to be subjected to batch-section processing again according to the value of the difference measured each time, that is, the wafer 1 with the value of the difference in the same interval section is divided into a plurality of interval sections according to the value range of the difference, so that the curvature correction layer 2 is formed in batch conveniently, and the production efficiency is improved.

Specifically, in the process of performing batch separation on the wafers 1 each time the difference value is obtained, when the curvature value of the wafers 1 is the same in the same interval section and the process section of the wafers 1, the wafers 1 forming the curvature correction layer 2 for the first time may be screened from the wafers 1 not subjected to curvature correction or the wafers 1 subjected to correction for multiple times to the same batch, so as to improve correction efficiency.

Specifically, the curvature value of the wafer 1 after the curvature correction layer 2 is formed is repeatedly measured, the curvature correction layer 2 with corresponding stress is formed based on the obtained difference value until the difference value is zero, the wafer 1 is corrected to be flat, and the wafer 1 is transmitted to the next process, so that the process precision of the next process is ensured, and meanwhile, the problem that equipment is difficult to adsorb when the subsequent process is performed due to the warping of the wafer 1 is solved.

Specifically, in the curvature correction layer 2, the first correction layer 21 corrects tensile stress generated by each film layer in the wafer 1, or corrects tensile stress generated by the combined action of each film layer in the wafer 1 and each film layer stacked on the upper surface of the wafer 1 by using the first correction layer 21; the second correction layer 22 corrects the compressive stress generated by each film layer in the wafer 1, or corrects the compressive stress generated by the combined action of each film layer in the wafer 1 and each film layer stacked on the upper surface of the wafer 1 by using the second correction layer 22. Here, each film layer stacked on the upper surface of the wafer 1 refers to the first correction layer 21, the second correction layer 22, or a stacked structure formed by the first correction layer 21 and the second correction layer 22.

Specifically, as shown in fig. 7, in order to form the schematic view of the wafer 1 after the correction layer 2 is formed, the curvature correction layer 2 including at least one of the first correction layer and the second correction layer is formed on the surface of the dielectric layer 11, the tensile stress is corrected by using the compressive stress generated by the first correction layer 21, the tensile stress is corrected by using the tensile stress generated by the second correction layer 22, or the tensile stress or the compressive stress generated by the wafer 1 is corrected by using the stacked structure of the first correction layer 21 and the second correction layer 22, so that the wafer 1 is flat, the alignment of the photolithography layout in the subsequent process is ensured, and the formed pattern is not deformed, thereby ensuring the performance of the device.

According to the wafer bow regulating method, the bow value of the wafer 1 is measured, the difference between the bow and the preset bow is obtained, the stress generated by the bow correcting layer 2 is estimated based on the difference, the bow correcting layer 2 comprises at least one of the first correcting layer 21 and the second correcting layer 22, the tensile stress generated by each film layer in the wafer 1 is corrected by using the compressive stress generated by the first correcting layer 21, the compressive stress generated by each film layer in the wafer 1 is corrected by using the tensile stress generated by the second correcting layer 22, or the compressive stress or the tensile stress generated by each film layer in the wafer 1 is corrected by using the laminated structure consisting of the first correcting layer 21 and the second correcting layer 22, and the bow value of the wafer 1 and the step of forming the corresponding bow correcting layer 2 based on the difference are repeatedly measured until the difference is zero.

Example two

The present embodiment provides a wafer structure, as shown in fig. 5 and 6, which are a schematic cross-sectional structure of one structure of the wafer structure and another schematic cross-sectional structure of the wafer structure, respectively, including a wafer 1 and a bow correcting layer 2, wherein the wafer 1 includes a dielectric layer 11 and a wiring layer 12 embedded in the dielectric layer 11; the curvature correction layer 2 includes at least one of a first correction layer 21 and a second correction layer 22.

Specifically, the wafer 1 includes a wafer after any one section of wiring layer is formed and polished in a later stage of a device manufacturing process, where the later stage refers to a stage of the formation process of the wiring layer of the device in the wafer.

Specifically, the thickness of the dielectric layer 11 may be selected according to practical situations, while ensuring the device performance, and is not limited herein.

Specifically, the wiring layer 12 is a wiring layer of each device in the wafer 1.

Specifically, under the condition that the device performance and the curvature of the wafer 1 can be corrected by the curvature correction layer 2 are ensured, the thickness of the curvature correction layer 2 can be set according to the time condition, and the limitation is not limited; the thickness of the first correction layer 21 may be set according to practical situations, and is not limited herein; the thickness of the second correction layer 22 may be set according to practical situations, and is not limited herein.

Specifically, the type of stress generated by the first correction layer 21 is compressive stress, and is used for correcting tensile stress generated by each film layer in the wafer 1 or by each film layer in the wafer 1 and the film layer stacked on the upper surface of the wafer 1.

Specifically, the type of stress generated by the second correction layer 22 is tensile stress, and is used for correcting the compressive stress generated by each film layer in the wafer 1 or by each film layer in the wafer 1 and the film layer stacked on the upper surface of the wafer 1.

Specifically, by setting the curvature correction layer 2, the compressive stress generated by the first correction layer 21 and the tensile stress generated by the second correction layer 22 are used to correct the tensile stress or the compressive stress generated by each film layer in the wafer 1, so that the wafer 1 tends to be flat, the photoetching alignment of the subsequent process is ensured, the performance of devices in the wafer 1 is ensured, and the yield of the wafer 1 in the subsequent process is improved.

According to the wafer structure, the curvature correction layer 2 is arranged on the upper surface of the wafer 1, the tensile stress generated by each film layer in the wafer 1 is corrected by using the compressive stress generated by the first correction layer 21 in the curvature correction layer 2, and the compressive stress generated by each film layer in the wafer 1 is corrected by using the tensile stress generated by the second correction layer 22, so that the wafer 1 tends to be flat, the photoetching alignment of the subsequent process is ensured, the performance of devices in the wafer 1 is ensured, and the yield of the wafer 1 in the subsequent process is improved.

In summary, the wafer structure and the method for controlling wafer bow according to the present invention measure the bow value of the wafer to obtain the difference between the bow value and the preset bow value, predict the stress generated by forming the bow correction layer based on the difference, correct the tensile stress generated by each film layer in the wafer by using the compressive stress generated by the first correction layer in the bow correction layer, correct the compressive stress generated by each film layer in the wafer by using the tensile stress generated by the second correction layer in the bow correction layer, measure the bow value again for the wafer after forming the bow correction layer to obtain a new difference, form the bow correction layer based on the difference again, repeat the steps of measuring the bow value and forming the corresponding bow correction layer based on the difference until the difference is zero, i.e. the wafer is flat, and transfer the wafer to the next process segment, thereby ensuring the process precision and the photolithography alignment of the next process, preventing the photolithography pattern from deforming, and then ensuring the performance of devices in the wafer, improving the yield of the wafer in the subsequent process, and simultaneously solving the problem of equipment adsorption difficulty occurring when the subsequent process is performed due to wafer warpage. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The method for regulating and controlling the wafer curvature is characterized by comprising the following steps of:

providing a wafer, wherein the wafer comprises a dielectric layer and a wiring layer embedded in the upper surface layer of the dielectric layer, and the dielectric layer is positioned on the upper surface layer of the wafer;

providing a wafer bending degree measuring instrument, measuring a bending value of the surface of the wafer, which reveals the wiring layer, by using the wafer bending degree measuring instrument, and comparing the bending value with a preset bending value to obtain a difference value between the bending value and the preset bending value;

judging the numerical value of the difference, when the difference is not equal to zero, placing the wafer in a film plating device, forming a curvature correction layer covering the dielectric layer on the upper surface of the wafer, wherein the curvature correction layer comprises at least one of a first correction layer and a second correction layer, the difference is smaller than zero, forming a first correction layer above the wafer, the difference is larger than zero, and forming a second correction layer above the wafer;

repeating the steps of obtaining the difference value and forming the curvature correction layer based on the difference value until the difference value is equal to zero;

and when the difference value is zero, conveying the wafer with the zero difference value to the next working procedure.

2. The method for controlling wafer bow according to claim 1, wherein: the preset curvature value is zero.

3. The method for controlling wafer bow according to claim 1, wherein: the material of the first correction layer comprises nitrogen-doped silicon carbide, and the type of stress generated by the first correction layer is compressive stress.

4. The method for controlling wafer bow according to claim 1, wherein: and the difference value is smaller than zero, and based on the absolute value of the difference value, the compressive stress required for correcting the curvature value of the wafer is estimated so as to adjust the curvature of the wafer to enable the surface of the wafer to tend to be flattened.

5. The method for controlling wafer bow according to claim 1, wherein: the pressure stress generated by the first correction layer is regulated and controlled by adjusting the power, the reaction temperature and the reaction pressure of the coating equipment and the proportion of the components of the gas forming the first correction layer.

6. The method for controlling wafer bow according to claim 1, wherein: the material of the two dielectric layers comprises nitrogen-doped silicon carbide, and the type of stress generated by the first correction layer is tensile stress.

7. The method for controlling wafer bow according to claim 1, wherein: the difference is larger than zero, and the tensile stress required for correcting the wafer bending degree is estimated based on the absolute value of the difference, so as to adjust the bending degree of the wafer 1 and enable the surface of the wafer to tend to be flattened.

8. The method for controlling wafer bow according to claim 1, wherein: the tensile stress generated by the second correction layer is regulated and controlled by adjusting the power, the reaction temperature and the reaction pressure of the coating equipment and the proportion of the components of the gas forming the second correction layer.

9. The method for controlling wafer bow according to claim 1, wherein: and repeatedly measuring the difference value, and then converting the difference value from less than zero to greater than zero, and forming the second correction layer with a preset thickness above the wafer so as to planarize the wafer.

10. A wafer structure, comprising:

the wafer comprises a dielectric layer and a wiring layer embedded in the dielectric layer, wherein the dielectric layer is positioned on the upper surface layer of the wafer;

and the curvature correction layer comprises at least one of a first correction layer and a second correction layer.

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