CN116010327B - PCIe Switch automatic configuration system and method - Google Patents
PCIe Switch automatic configuration system and method Download PDFInfo
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Abstract
The application discloses a PCIES switch automatic configuration system and a PCIES switch automatic configuration method, wherein the system comprises a main board and an adapter card corresponding to the main board; the transfer card is provided with a storage chip; the memory chip is connected with the main board through the switching slot; the memory chip stores configuration information corresponding to the adapter card; a PCIES switch chip is arranged on the main board; the PCIe switch chip is configured to perform PCIe port configuration according to the configuration information on the storage chip and the corresponding switch card slot. According to the method, the memory chip is arranged on the adapter card, configuration information in the memory chip changes along with the change of the adapter card, the fact that the same main board or PCIES switch chip can be automatically adapted to different adapter cards is achieved, the scheme adaptability is strong, the design is simple and stable, and the cost is low, and the method can be achieved without depending on a third-party logic controller.
Description
Technical Field
The application relates to the technical field of communication interfaces, in particular to a PCIe Switch automatic configuration system and method.
Background
PCIe (peripheral component interconnect express) is a high-speed serial computer expansion bus standard. PCIe Switch chips are a type of high-speed PCIe switching device that is often placed on a server for expansion of the host-side PCIe interface to support more PCIe devices.
In the design of the server system, the device of the expansion of the PCIe port of the motherboard is not invariable, but varies according to the actual application scenario, such as the variation of the PCIe slot bit width, changing the PCIe protocol transmitted on the physical channel into SATA (SerialATA) protocol, etc. These changes are designed in the basic input output system program (Basic Input Output System, BIOS) and executed by the CPU: the CPU obtains external configuration information through interfaces such as General-purpose input/output (GPIO) and I2C bus (Inter-Integrated Circuit), and then selects a corresponding configuration mode according to the external configuration information. However, with PCIe Switch, a PCIe expansion chip is not flexibly configured due to the limitation of the device itself (dynamic monitoring is not supported or the workload of programming and development is large).
Therefore, in the above scheme, because the PCIe Switch chip cannot be dynamically adjusted according to the back-end PCIe device, the commonality of the server motherboard is greatly reduced, and the product maintenance cost is increased.
Disclosure of Invention
The application provides a PCIe Switch automatic configuration system and method, which realize that the same main board can automatically adapt to different adapter cards so as to adapt to different application scenes.
In one aspect, there is provided a PCIe Switch automatic configuration system, the system comprising: a motherboard and a transfer card corresponding to the motherboard;
the transfer card is provided with a storage chip;
the memory chip is connected with the main board through the switching clamping groove; the memory chip stores configuration information corresponding to the transfer card;
the main board is provided with a PCIe Switch chip; and the PCIe Switch chip is used for performing PCIe port configuration according to the configuration information on the memory chip and the corresponding adapter card slot.
In one possible implementation manner, the main board is correspondingly provided with a plurality of corresponding adapter cards, and each adapter card is provided with the memory chip corresponding to the adapter card one to one.
In one possible implementation manner, a signal relay chip is arranged on a transmission link between the PCIe Switch chip and the memory chip, and the signal relay chip is used for improving signal transmission quality between the PCIe Switch chip and the memory chip.
In one possible implementation, the signal relay chip is a driver chip.
In one possible implementation, the configuration information includes port bit width information, port connector type, and physical link drive setup information.
In one possible implementation, the port bit width information includes at least one of a PCIe X16 lane, a PCIe X8 lane, a PCIe X4 lane, and a PCIe X2 lane.
In one possible implementation, the port connector type is determined based on a corresponding riser card; the port connector types include SHPC connector type, U.2 connector type, SFF-8644 connector type, and SFF-8643 connector type.
In a possible implementation manner, when the Riser card is a Riser card, the type of the port connector corresponding to the Riser card is the SHPC connector type;
the type of the port connector corresponding to the adapter card being an NVMe card is the U.2 connector type;
the port connector type corresponding to the external IO card is the SFF-8644 connector type or the SFF-8643 connector type;
and when the transfer card type is a hybrid card, the port connector type corresponding to the transfer card type is the hybrid application of the SHPC connector type and the U.2 connector type.
In one possible implementation, the physical link drive setup information is determined based on chassis height and the port connector type.
In yet another aspect, a PCIe Switch automatic configuration method is provided, where the method is applied to a PCIe Switch automatic configuration system, and the method includes:
acquiring configuration information in a memory chip corresponding to a main board; the memory chips are arranged on the corresponding transfer cards, and the configuration information in the memory chips corresponds to the transfer cards one by one;
and configuring the PCIe Switch chip on the main board according to the configuration information and the corresponding switching card slot so as to realize PCIe port configuration.
In yet another aspect, there is provided a PCIe Switch automatic configuration device, the device comprising:
the configuration information acquisition module is used for acquiring configuration information in the memory chip corresponding to the main board; the memory chips are arranged on the corresponding transfer cards, and the configuration information in the memory chips corresponds to the transfer cards one by one;
and the PCIe port configuration module is used for configuring the PCIe Switch chip on the main board according to the configuration information and the corresponding switching card slot bit so as to realize PCIe port configuration.
In yet another aspect, a computer device is provided that includes a processor and a memory having at least one instruction stored therein that is loaded and executed by the processor to implement a PCIe Switch auto-configuration method as described above.
In yet another aspect, a computer-readable storage medium having stored therein at least one instruction that is loaded and executed by a processor to implement a PCIe Switch auto-configuration method as described above is provided.
The technical scheme that this application provided can include following beneficial effect:
the memory chip is arranged on the adapter card, the configuration information in the memory chip changes along with the change of the adapter card, so that the same main board or PCIe Switch chip can be automatically adapted to different adapter cards, the scheme is simple in design, small in development amount and stable, and a third-party logic controller is not required to be relied on; based on the configuration information in the memory chip, not only PCIe port allocation can be flexibly adjusted according to the adapter card, but also the switching can be performed aiming at the application scene of the rear end, and the connector type is adjusted according to the adapter card, so that more protocols are supported, the configuration is richer and more flexible; the system can be configured according to the actual physical link conditions, so that the system can adapt to applications of different chassis heights or cables with different lengths, the signal transmission of each port is optimal, and the stability and the performance of the system are ensured to be optimal.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram illustrating the architecture of a PCIe Switch auto-configuration system in accordance with an exemplary embodiment.
Fig. 2 is a schematic diagram showing connection relationships between a rediver chip and PCIe Switch chips and memory chips, respectively, according to an exemplary embodiment.
FIG. 3 is a method flow diagram illustrating a PCIe Switch auto-configuration method in accordance with an exemplary embodiment.
FIG. 4 is a block diagram illustrating the structure of a PCIe Switch auto-configuration device in accordance with an exemplary embodiment.
Fig. 5 shows a block diagram of a computer device according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
It should be understood that, in the description of the embodiments of the present application, the term "corresponding" may indicate that there is a direct correspondence or an indirect correspondence between the two, or may indicate that there is an association between the two, or may indicate a relationship between the two and the indicated, configured, or the like.
FIG. 1 is a schematic diagram illustrating the architecture of a PCIe Switch auto-configuration system in accordance with an exemplary embodiment. As shown in fig. 1, the system includes: a motherboard and a transfer card corresponding to the motherboard;
the transfer card is provided with a storage chip;
the memory chip is connected with the main board through the switching card slot; the memory chip stores configuration information corresponding to the transfer card;
the main board is provided with a PCIe Switch chip; the PCIe Switch chip is configured to perform PCIe port configuration according to the configuration information on the memory chip and the corresponding Switch card slot.
For example, as shown in fig. 1, the type of the transit card may include a Riser card, an NVMe card, an external IO card, and a hybrid card.
In one possible implementation manner, the motherboard is correspondingly provided with a plurality of corresponding adapter cards, and each adapter card is provided with the memory chip corresponding to the adapter card one by one.
Further, as shown in fig. 1, the motherboard is mounted with a CPU in addition to the PCie Switch chip, and the motherboard is provided with a golden finger connector for connecting with a golden finger on the adapter card.
Further, as shown in fig. 1, the switch card is configured with pcie 3.0X 16 Slot, pcie 3.0X 8Slot, pcie 3.0X 4 Slot, pcie 3.0X 2 Slot, and SlimSAS X8 connectors singly or in combination according to the functions thereof; the adapter card is provided with a golden finger, and the golden finger is matched with a golden finger connector on the main board to achieve the function of connecting signals.
Further, currently, the memory chip of the PCIe Switch chip memory configuration is usually placed near the PCIe Switch chip, that is, the PCIe Switch chip and the memory chip are disposed on the same motherboard. Since PCIe Switch chip configuration is fixed, assuming configuration 1, the type of adapter card that is adapted is a Riser card, which can only adapt to Riser card 1, but cannot adapt to Riser card 2, which limits flexibility and adaptability of the product. Therefore, in this embodiment, the memory chip is disposed on the corresponding adapter card, and the internal configuration information is set according to the slot allocation of the adapter card, where the configuration corresponds to the adapter card one by one. The memory chip is connected with the main board through the switching card slot, when the system is initialized, the PCIe Switch chip loads the memory chip designed on the switching card, so that the memory chip is initialized according to the corresponding switching card slot allocation, and the fact that the same main board or the PCIe Switch chip can be automatically adapted to different switching cards is realized.
As shown in fig. 1, the same motherboard can automatically adapt to 6 different cards, namely the card 1: riser card-1, riser card 2: riser card-2, riser card 3: riser card-3, riser card 4: NVMe card, adapter card 5: external IO card and transfer 6: a hybrid card. Each adapter card is single or combined with a channel connector, for example, channels corresponding to Riser-1 are combined into PCIE3.0X16 Slot 01 and PCIE3.0X16 Slot 02; the channel combination corresponding to the Riser-2 is PCIE3.0X106 Slot 01, PCIE3.0X18 Slot 02 and PCIE3.0X18 Slot 03; the channel combinations corresponding to the Riser-3 are PCIE3.0X8Slot 01, PCIE3.0X8Slot 02, PCIE3.0X8Slot 03 and PCIE3.0X8Slot 04; the channel combinations corresponding to the NVMe card-1 are SlimSAS X8J01, slimSAS X8J 02, slimSAS X8J 03 and SlimSAS X8J 04, and numbers are represented by 01 to 04 and J01 to J04; the channel combinations corresponding to the external IO card are SFF-8644X8J01, SFF-8644X8J 02, SFF-8644X8J 03 and SFF-8644X8J 04, and the numbers are represented by J01 to J04; the corresponding channel combinations of the hybrid card are PCIE3.0X16 Slot1, SFF-8644X8J01 and SFF-8644X8J 02, and 01 and J01 to J02 represent numbers.
In one possible implementation manner, the PCIe Switch chip and the memory chip are provided with a signal relay chip on a transmission link, and the signal relay chip is used for improving signal transmission quality between the PCIe Switch chip and the memory chip.
In one possible implementation, the signal relay chip is a driver chip (i.e., a redrive chip).
The signal relay chip may also be a Buffer/line driver (Buffer Gate chip), a Level Shift chip (Level Shift), etc. as an example, and in this application, a driver chip is the optimal choice.
Further, in practical applications, PCIe Switch chips require a minimum of 0.4 feet and a maximum of 5 feet of configured memory chip to its SPI BUS trace distance. When the PCIe Switch chip and the memory chip are on the same motherboard, this specification is easily met. However, the wiring distance specification of more than 5 feet is easy to place the memory chip on another board card; in addition, as the wiring length of the SPI BUS increases, the problems of insufficient driving capability, asynchronous signals, crosstalk between signals, external interference and the like are caused, the poor signal quality and the reliability are reduced, and even the chip cannot work normally due to the fact that the configuration memory chip cannot be read. Therefore, to solve the problem of signal overlength, a rediver chip is added to the link, and the model of the rediver chip may be FXLA108. For example, please refer to the schematic connection diagram of the rediver chip shown in fig. 2 with the PCIe Switch chip and the memory chip, respectively. Wherein, each QSPI port of the PCIe Switch chip is connected with each A port of the FXLA108, and each B port of the FXLA108 is connected with each port of the memory chip.
In one possible implementation, the configuration information includes port bit width information, port connector type, and physical link drive setup information.
In one possible implementation, the port bit width information includes at least one of a PCIe X16 lane, a PCIe X8 lane, a PCIe X4 lane, and a PCIe X2 lane.
Furthermore, the PCIe Switch chip reads configuration information in the corresponding memory chip when the PCIe Switch chip is powered on, where the configuration information includes all settings related to the PCIe Switch chip. The different cards described in this application are primarily differentiated by the configuration information above. Compared with the existing configuration method, which can only adjust the port bit width, the configuration of the port connector type, the physical link drive setting and the like can be further adjusted, so that more specific setting is realized, and different adapter cards are better controlled.
Similarly, the same motherboard may be adapted to different cards, and in theory, the cards are more configured, and fig. 1 only shows some of the more typical configurations, and exemplary, the cards 1 in fig. 1: riser card-1 is a dual GPU configuration; adapter card 2: riser card-2 is 2U general configuration and 4U general configuration; adapter card 3: riser card-3 is a 4U universal configuration; adapter card 4: NVMe card-1 is a high performance storage configuration; adapter card 5: the external IO card is configured for external IO BOX; adapter card 6: the hybrid card is configured for a hybrid application. The channel combinations corresponding to the Riser card-2 may be, in addition to the above-mentioned pcie 3.0X 16 Slot 01, pcie 3.0X 8Slot 02 and pcie 3.0X 8Slot 03, pcie 3.0X 8Slot 01, pcie 3.0X 8Slot 02 and pcie 3.0X 16 Slot 03, which are both configured in 2U general and 4U general.
In one possible implementation, the port connector type is determined based on the corresponding riser card; the port connector types include SHPC connector type, U.2 connector type, SFF-8644 connector type, and SFF-8643 connector type.
In one possible implementation, the port connector type corresponding to the Riser card is the SHPC connector type;
the type of the port connector corresponding to the adapter card being an NVMe card is U.2 connector type;
the port connector type corresponding to the external IO card is the SFF-8644 connector type or the SFF-8643 connector type;
the port connector type corresponding to the case that the adapter card type is a hybrid card is a hybrid application of the SHPC connector type and the U.2 connector type.
Further, for the case of the adapter card, the following types of configuration can be made: PCIe Slot of the direct-use configuration; the applied NVMe Riser is stored. When the adapter card is a standard PCIe Slot device, the corresponding PCIe port is configured into an SHPC connector type; when the switch card is an NVMe SSD, the corresponding PCIe port is configured as a U.2 connector type; when the switch card is an IO BOX, the corresponding PCIe port is configured with an SFF-8644 connector type and an SFF-8643 connector type.
Therefore, the adapter card of the prior proposal is a Riser card, so that the adapter card can only be adapted to the SHPC type connector, and the adapter card can be adapted to various types of connectors, and has richer configuration and more flexibility.
In one possible implementation, the physical link drive setup information is determined based on chassis height, and the port connector type.
Further, as in the typical application configuration described above, the trace lengths corresponding to the chassis with the chassis height of 2U and the chassis with the chassis height of 4U are different, and the interfaces corresponding to the connectors with the connector types of PCIe Slot and U.2 and SFF8643/SFF-8644 are also different, so that the connector types are adjusted according to the actual physical link information.
In one possible implementation, GPIO (general porpose intput output) functionality can be provided for different riser cards. GPIO is the abbreviation of general purpose input/output port, namely, the output and input of the GPIO can be controlled by software; for example, when the Riser card is applied, the GPIO can drive a status indicator light for indicating the working condition of the slot; for example, when the NVMe card is applied, the GPIO can be configured as a hot plug related signal, so that the out-of-band hot plug management of the NVMe hard disk is realized.
In summary, the memory chip is arranged on the adapter card, and the configuration information in the memory chip changes along with the change of the adapter card, so that the same main board or PCIe Switch chip can be automatically adapted to different adapter cards, and the scheme is simple in design, small in development amount and stable, and does not need to rely on a third-party logic controller; based on the configuration information in the memory chip, not only PCIe port allocation can be flexibly adjusted according to the adapter card, but also the switching can be performed aiming at the application scene of the rear end, and the connector type is adjusted according to the adapter card, so that more protocols are supported, the configuration is richer and more flexible; the system can be configured according to the actual physical link conditions, so that the system can adapt to applications of different chassis heights or cables with different lengths, the signal transmission of each port is optimal, and the stability and the performance of the system are ensured to be optimal.
FIG. 3 is a method flow diagram illustrating a PCIe Switch auto-configuration method in accordance with an exemplary embodiment. The method is applied to the PCIe Switch automatic configuration system shown in FIG. 1, and as shown in FIG. 3, the method can comprise the following steps:
s301, acquiring configuration information in a memory chip corresponding to a main board; the memory chips are arranged on the corresponding transfer cards, and the configuration information in the memory chips corresponds to the transfer cards one by one.
S302, configuring the PCIe Switch chip on the main board according to the configuration information and the corresponding switching card slot so as to realize PCIe port configuration.
In summary, the memory chip is arranged on the adapter card, and the configuration information in the memory chip changes along with the change of the adapter card, so that the same main board or PCIe Switch chip can be automatically adapted to different adapter cards, and the scheme is simple in design, small in development amount and stable, and does not need to rely on a third-party logic controller; based on the configuration information in the memory chip, not only PCIe port allocation can be flexibly adjusted according to the adapter card, but also the switching can be performed aiming at the application scene of the rear end, and the connector type is adjusted according to the adapter card, so that more protocols are supported, the configuration is richer and more flexible; the system can be configured according to the actual physical link conditions, so that the system can adapt to applications of different chassis heights or cables with different lengths, the signal transmission of each port is optimal, and the stability and the performance of the system are ensured to be optimal.
FIG. 4 is a block diagram illustrating the structure of a PCIe Switch auto-configuration device in accordance with an exemplary embodiment. The device comprises:
a configuration information obtaining module 401, configured to obtain configuration information in a memory chip corresponding to a motherboard; the memory chips are arranged on the corresponding transfer cards, and the configuration information in the memory chips corresponds to the transfer cards one by one;
and the PCIe port configuration module 402 is configured to configure PCIe Switch chips on the motherboard according to the configuration information and corresponding Switch slots, so as to implement PCIe port configuration.
In summary, the memory chip is arranged on the adapter card, and the configuration information in the memory chip changes along with the change of the adapter card, so that the same main board or PCIe Switch chip can be automatically adapted to different adapter cards, and the scheme is simple in design, small in development amount and stable, and does not need to rely on a third-party logic controller; based on the configuration information in the memory chip, not only PCIe port allocation can be flexibly adjusted according to the adapter card, but also the switching can be performed aiming at the application scene of the rear end, and the connector type is adjusted according to the adapter card, so that more protocols are supported, the configuration is richer and more flexible; the system can be configured according to the actual physical link conditions, so that the system can adapt to applications of different chassis heights or cables with different lengths, the signal transmission of each port is optimal, and the stability and the performance of the system are ensured to be optimal.
Referring to fig. 5, a block diagram of a computer device according to an exemplary embodiment of the present application is provided, where the computer device includes a memory and a processor, and the memory is configured to store a computer program, and when the computer program is executed by the processor, implement a PCIe Switch automatic configuration system as described above.
The processor may be a central processing unit (Central Processing Unit, CPU). The processor may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field-Programmable gate arrays (FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination thereof.
The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the methods in embodiments of the present application. The processor executes various functional applications of the processor and data processing, i.e., implements the methods of the method embodiments described above, by running non-transitory software programs, instructions, and modules stored in memory.
The memory may include a memory program area and a memory data area, wherein the memory program area may store an operating system, at least one application program required for a function; the storage data area may store data created by the processor, etc. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some implementations, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
In an exemplary embodiment, a computer readable storage medium is also provided for storing at least one computer program that is loaded and executed by a processor to implement all or part of the steps of the above method. For example, the computer readable storage medium may be Read-Only Memory (ROM), random-access Memory (RandomAccess Memory, RAM), compact disc Read-Only Memory (CD-ROM), magnetic tape, floppy disk, optical data storage device, and the like.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (8)
1. A PCIe Switch automatic configuration system, the system comprising: a motherboard and a transfer card corresponding to the motherboard;
the transfer card is provided with a storage chip;
the memory chip is connected with the main board through the switching clamping groove; the memory chip stores configuration information corresponding to the transfer card; the configuration information comprises port bit width information, port connector type and physical link drive setting information;
the main board is provided with a PCIe Switch chip; the PCIe Switch chip is used for performing PCIe port configuration according to the configuration information on the memory chip and the corresponding adapter card slot;
the main board is correspondingly provided with a plurality of corresponding transfer cards, and each transfer card is provided with a memory chip corresponding to the transfer card one by one.
2. The system of claim 1, wherein a signal relay chip is disposed on a transmission link between the PCIe Switch chip and the memory chip, the signal relay chip being configured to improve signal transmission quality between the PCIe Switch chip and the memory chip.
3. The system of claim 2, wherein the signal relay chip is a driver chip.
4. The system of claim 1, wherein the port bit width information comprises at least one of a PCIe X16 lane, a PCIe X8 lane, a PCIe X4 lane, and a PCIe X2 lane.
5. The system of claim 4, wherein the port connector type is determined based on a corresponding riser card; the port connector types include SHPC connector type, U.2 connector type, SFF-8644 connector type, and SFF-8643 connector type.
6. The system of claim 5, wherein the port connector type corresponding to the Riser card is the SHPC connector type;
the type of the port connector corresponding to the adapter card being an NVMe card is the U.2 connector type;
the port connector type corresponding to the external IO card is the SFF-8644 connector type or the SFF-8643 connector type;
and when the transfer card type is a hybrid card, the port connector type corresponding to the transfer card type is the hybrid application of the SHPC connector type and the U.2 connector type.
7. The system of claim 1, wherein the physical link drive setup information is determined based on chassis height and the port connector type.
8. A PCIe Switch automatic configuration method, wherein the method is applied to a PCIe Switch automatic configuration system, the method includes:
acquiring configuration information in a memory chip corresponding to a main board; the memory chips are arranged on the corresponding transfer cards, and the configuration information in the memory chips corresponds to the transfer cards one by one; the configuration information comprises port bit width information, port connector type and physical link drive setting information;
configuring PCIe Switch chips on the main board according to the configuration information and the corresponding switching card slot positions so as to realize PCIe port configuration;
the main board is correspondingly provided with a plurality of corresponding transfer cards, and each transfer card is provided with a memory chip corresponding to the transfer card one by one.
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