CN115996205B - TSN Ethernet switching module and electric power Internet of things message processing method - Google Patents

Abstract

The specification discloses a TSN Ethernet switching module and a method for processing electric power Internet of things messages, wherein the TSN Ethernet switching module comprises a processor and a TSN switching chip. The TSN exchange chip is provided with an SPI interface and an RGMII network port; the processor is connected with the TSN exchange chip through an SPI interface to perform initialization configuration on the TSN exchange chip, and is connected with the TSN exchange chip through an RGMII network interface to perform network management on the TSN exchange chip; when receiving a network message, the TSN exchange chip acquires a protocol type field of the network message, and if the network message is judged to accord with a time-sensitive network protocol standard based on the protocol type field, the network message is distributed to a target thread corresponding to the target protocol standard; the target protocol standard is a time sensitive network protocol standard according to which a network message determined in a TSN protocol stack according to a protocol type field accords. According to the embodiment of the specification, the requirement of industrial scenes can be met by using a single switching chip, and the reliability of the TSN Ethernet switching module is improved.

Description

TSN Ethernet switching module and electric power Internet of things message processing method

Technical Field

The present disclosure relates to the field of ethernet technologies, and in particular, to a TSN ethernet switching module and a method for processing a packet of an electric power internet of things.

Background

Along with the continuous and deep construction of the national power grid to the electric power Internet of things, the deep integration of the information communication technology and the physical system becomes a necessary trend. The electric power internet of things requires construction of an information physical system (CPS) based on a communication information technology to realize comprehensive optimization operation of scheduling, protection, control and transaction. At present, the demands of services in different fields such as power transmission, power transformation, power distribution, electricity consumption, comprehensive energy sources and the like on deterministic networks such as bandwidth, time delay, jitter, time service and the like are increasingly prominent. However, in the fields of the electric power internet of things and the like, multi-chip cascading is generally required to meet the requirements of the Ethernet switch commonly used in the industrial field, and the reliability of the Ethernet switch chip needs to be improved.

Disclosure of Invention

The present specification aims to solve at least one of the technical problems in the related art to some extent. Therefore, an object of the present disclosure is to provide a TSN ethernet switching module, which includes a TSN switching chip, and further provides message processing related to a reserved protocol such as a time sensitive network protocol on the basis of a conventional ethernet switching chip, so as to improve compatibility and interoperability of ethernet, and realize that a single switching chip can meet requirements of industrial scenes, and improve reliability of the TSN ethernet switching module.

A second object of the present specification is to provide a TSN network management system.

A third object of the present disclosure is to provide a TSN switching system based on the internet of things of electric power.

The fourth object of the present disclosure is to provide a method for processing a message of an electric power internet of things.

A fifth object of the present specification is to propose a computer readable storage medium.

To achieve the above objective, an embodiment of a first aspect of the present disclosure provides a TSN ethernet switching module, where the TSN ethernet switching module includes: processor, TSN switching chip. The TSN exchange chip is provided with an SPI interface and an RGMII network port; the TSN switching chip is configured to support a time-sensitive network protocol standard; the processor is connected with the TSN exchange chip through an SPI interface to perform initialization configuration on the TSN exchange chip, and is connected with the TSN exchange chip through an RGMII network interface to perform network management on the TSN exchange chip; when receiving a network message, the TSN exchange chip acquires a protocol type field of the network message, and if the network message is judged to accord with a time-sensitive network protocol standard based on the protocol type field, the network message is distributed to a target thread corresponding to the target protocol standard; the target protocol standard is a time sensitive network protocol standard which is met by a network message determined in a TSN protocol stack according to a protocol type field; the target thread is a processing thread allocated for the target protocol standard, and is used for processing the network message according to the target protocol standard.

According to the TSN Ethernet switching module of the embodiment of the specification, on the basis of supporting the functions of the traditional switching chip, the TSN switching chip is configured to be capable of supporting a time-sensitive network protocol standard. When the TSN exchange chip receives the network message, the network message conforming to the basic protocol can be processed, and the network message conforming to the Time Sensitive Network (TSN) protocol standard can be processed. The TSN switching module has accurate flow scheduling capability, and can ensure the common network high-quality data transmission of various services. The TSN Ethernet switching module of the embodiment of the specification improves the compatibility and the interoperability of the Ethernet, meets the requirements of industrial scenes by utilizing a single switching chip, and improves the reliability of the TSN Ethernet switching module.

In some embodiments of the present disclosure, when a TSN switch chip sends a target network packet according to a time-sensitive network protocol standard, an sending time point of the target network packet sent by the TSN switch chip is added to the target network packet, so that a MAC interface sending the target network packet can identify the target network packet.

In some embodiments of the present description, the time sensitive network protocol standard comprises a precision time synchronization protocol standard; when receiving a first type network message conforming to the accurate time synchronization protocol standard, the TSN exchange chip marks the time stamp information of the network message and caches the time stamp information into the first-in first-out memory; determining master-slave clock difference according to master clock and time stamp information of a data transmission link, and calibrating a clock source of the TSN Ethernet switching module by using the master-slave clock difference so as to perform time synchronous transmission on the first type network messages; wherein the master clock is determined based on the processor executing an optimal master clock algorithm.

In some embodiments of the present description, the time-sensitive network protocol standard includes a time-sensitive traffic scheduling protocol standard and a frame preemption mechanism protocol standard; when receiving a second type network message conforming to the time sensitive flow scheduling protocol standard, the TSN exchange chip performs transmission selection processing on the second type network message according to the time sensitive flow scheduling protocol standard by utilizing a thread corresponding to the time sensitive flow scheduling protocol standard; when receiving the third type network message conforming to the frame preemption mechanism protocol standard, the TSN exchange chip performs frame preemption processing on the third type network message according to the frame preemption mechanism protocol standard by using a thread corresponding to the frame preemption mechanism protocol standard.

In some embodiments of the present description, the TSN switch chip is configured with several Serdes interfaces; the Serdes interface is configured as a Qsgmii interface supporting a 5Gbps transmission rate or as a 10GBase-R interface supporting a 10.3125Gbps transmission rate.

In some embodiments of the present description, the switching module further comprises: a plurality of PHY chips; the PHY chip is connected with the TSN switching chip through the Qsgmii interface so that the Qsgmii interface supports 8B/10B conversion.

In some embodiments of the present description, the PHY chip is configured with a network interface; the PHY chip is connected with external equipment through a network interface; the TSN exchange chip carries out auto-negotiation with the external equipment through the PHY chip so as to exchange signals with the agreed running speed and duplex mode.

In some embodiments of the present description, the switch module further includes an FPGA processing chip; the FPGA processing chip is connected with the TSN exchange chip through a 10GBase-R interface and is used for converting photoelectric signals.

In some embodiments of the present description, the switching module further comprises: EEPROM memory, clock chip and TMP temperature monitor; the processor accesses and manages the EEPROM memory, the clock chip, and the TMP temperature monitor based on the serial communication bus.

To achieve the above object, an embodiment of a second aspect of the present disclosure provides a TSN network management system, including an application layer, a control layer, and a link layer; wherein the switch module of any of the above embodiments is applied to the link layer

To achieve the above objective, an embodiment of a third aspect of the present disclosure provides a TSN switching system based on the electric power internet of things, including the switching module of any one of the embodiments of the first aspect.

In order to achieve the above objective, a fourth embodiment of the present disclosure provides a method for processing a packet of an electric power internet of things, which is applied to a TSN switch chip in a TSN ethernet switch module. The TSN exchange chip is provided with an SPI interface and an RGMII network port; the TSN switching chip is configured to support a time-sensitive network protocol standard; the TSN exchange chip is connected with the processor of the TSN Ethernet exchange module through the SPI interface and the RGMII network interface. The electric power internet of things message processing method comprises the following steps: when a network message is received, a protocol type field of the network message is acquired; if the network message accords with the time sensitive network protocol standard based on the protocol type field, determining a target protocol standard which accords with the network message in a TSN protocol stack according to the protocol type field; distributing the network message to a target thread corresponding to a target protocol standard; the target thread is a processing thread distributed aiming at a target protocol standard; and processing the network message according to the target protocol standard.

According to the method for processing the electric power internet of things message, not only can the network message conforming to the basic protocol be processed, but also the network message conforming to the Time Sensitive Network (TSN) protocol standard can be processed. The method has accurate flow scheduling capability, and can ensure the common network high-quality data transmission of multiple services. The electric power internet of things message processing method improves the compatibility and interoperability of the Ethernet, meets the requirements of industrial scenes by utilizing a single switching chip, and improves the reliability of the TSN Ethernet switching module.

In some embodiments of the present disclosure, the method for processing a packet of the electric power internet of things further includes: when a target network message conforming to the time sensitive network protocol standard is transmitted, the sending time point of the target network message transmitted by the TSN exchange chip is added into the target network message, so that the MAC interface for transmitting the target network message can identify the target network message.

In some embodiments of the present description, the time sensitive network protocol standard comprises a precision time synchronization protocol standard. Processing the network message according to the target protocol standard, including: when a first type network message conforming to the accurate time synchronization protocol standard is received, marking time stamp information of the network message; caching the time stamp information into a first-in first-out memory; and determining master-slave clock differences according to master clock and time stamp information of the data transmission link, and calibrating clock sources of the TSN Ethernet switching module by using the master-slave clock differences so as to carry out time synchronous transmission on the first type network messages. Wherein the master clock is determined based on the processor executing an optimal master clock algorithm.

To achieve the above object, an embodiment of a fifth aspect of the present disclosure provides a computer-readable storage medium having stored thereon an electric power internet of things message processing program, which when executed by a processor, implements an electric power internet of things message processing method according to any one of the embodiments of the fourth aspect.

According to the computer readable storage medium of the embodiment of the present specification, when the power internet of things message processing program is executed by the processor, not only the network message conforming to the basic protocol but also the network message conforming to the Time Sensitive Network (TSN) protocol standard can be processed. The method has accurate flow scheduling capability, and can ensure the common network high-quality data transmission of multiple services. The electric power internet of things message processing method improves the compatibility and interoperability of the Ethernet, meets the requirements of industrial scenes by utilizing a single switching chip, and improves the reliability of the TSN Ethernet switching module.

Additional aspects and advantages of the present description will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present description.

Drawings

Fig. 1 is a block diagram of a TSN ethernet switching module according to an embodiment of the present disclosure.

Fig. 2 is a flow diagram of a time stamping mechanism process according to one embodiment of the present description.

Fig. 3 is a flow chart of a time synchronization method according to one embodiment of the present description.

FIG. 4 is a functional block diagram of inter-sensitive traffic scheduling according to one embodiment of the present description.

Fig. 5 is a functional block diagram of a TAS mechanism according to one embodiment of the present description.

Fig. 6 is a functional block diagram of a frame preemptive MAC in accordance with an embodiment of the present description.

Fig. 7 is a block diagram of a TSN ethernet switching module according to one embodiment of the present disclosure.

Fig. 8 is a functional block diagram of a TSN switching chip according to one embodiment of the present disclosure.

Fig. 9 is a functional block diagram of a TSN network management system according to one embodiment of the present description.

Fig. 10 is a functional block diagram of a TSN switching system according to one embodiment of the present description.

Fig. 11 is a flowchart of a method for processing a message of the internet of things of electric power according to an embodiment of the present disclosure.

Fig. 12 is a flowchart of a method for processing a message of the internet of things of electric power according to a specific embodiment of the present disclosure.

Detailed Description

Embodiments of the present specification are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended for the purpose of illustrating the present description and are not to be construed as limiting the present description.

The electric power internet of things is a specific application embodiment of the internet of things in the smart grid, and is a necessary result of the development of information and network communication technology to a certain stage. The infrastructure of the power system is effectively integrated, the informatization level of the power system is greatly improved, and the utilization efficiency of the infrastructure of the power system is thoroughly improved.

Along with the continuous and deep construction of the national power grid to the electric power Internet of things, the deep integration of the information communication technology and the physical system becomes a necessary trend. The electric power internet of things requires construction of an information physical system (CPS) based on a communication information technology to realize comprehensive optimization operation of scheduling, protection, control and transaction. At present, the demands of services in different fields such as power transmission, power transformation, power distribution, electricity consumption, comprehensive energy sources and the like on deterministic networks such as bandwidth, time delay, jitter, time service and the like are increasingly prominent. In the scene of the rapid increase of information quantity of a new generation intelligent substation, a virtual power plant and the like, service application provides deterministic requirements on performances such as time delay, jitter and the like. The TSN Ethernet switching module of the specification is designed and realized on the basis of the electric power Internet of things, and has the scene of adaptation application in various fields such as power transmission, transformation, distribution, power consumption and the like, so that the requirements of data transmission delay, jitter and reliability are met.

The ethernet switch commonly used in the fields such as the electric power internet of things, rail transit automation, industrial automation and the like generally needs to be configured with 24 ports. However, the number of ports of the industrial TSN switch chip of the international mainstream manufacturer is relatively small, and multi-chip cascading is needed to meet the requirements of the switch in the industrial field.

Based on the technical problems, the specification provides a TSN Ethernet switching module. The TSN switching chip adopted by the TSN Ethernet switching module is a multi-port industrial switching chip supporting a time-sensitive network protocol standard. The service interface can support 24xGE and 4x10GE, namely, a maximum of 24 electric ports and 4 optical ports. The GE port supports 10/100/1000M rate, can negotiate port rate and duplex mode port with the opposite terminal equipment through auto-negotiation, can realize the above-mentioned demand in principle on a single chip, help to improve the reliability of Ethernet exchanger, and can reduce the cost.

The TSN ethernet switching module according to the embodiments of the present disclosure is described in detail below with reference to fig. 1. As shown in fig. 1, the TSN ethernet switching module includes: processor, TSN switching chip. The TSN exchange chip is provided with an SPI interface and an RGMII network interface. The TSN switching chip is configured to support time-sensitive network protocol standards. The processor is connected with the TSN exchange chip through the SPI interface to carry out initialization configuration on the TSN exchange chip, and is connected with the TSN exchange chip through the RGMII network interface to carry out network management on the TSN exchange chip.

When the TSN exchange chip receives the network message, a protocol type field of the network message is obtained, and if the network message is judged to accord with the time-sensitive network protocol standard based on the protocol type field, the network message is distributed to a target thread corresponding to the target protocol standard. The target protocol standard is a time sensitive network protocol standard according to which a network message determined in a TSN protocol stack according to a protocol type field accords. The target thread is a processing thread allocated for the target protocol standard, and is used for processing the network message according to the target protocol standard.

The time sensitive network TSN is a set of protocol standards developed by the IEEE 802.1 working group for interoperability and real-time tasks. The method aims to solve the problem that the compatibility and the interoperability cannot be improved when the real-time Ethernet protocol is only applied to services and application accesses of a plurality of suppliers in a certain specific scene. In addition, the time-sensitive network protocol mainly provides a general processing mechanism for the second layer (MAC layer) of the Ethernet, so that the interoperability among different Ethernet protocol networks is possible, and the network convergence in the true sense is realized. The Time Sensitive Network (TSN) is based on the traditional Ethernet, and provides low-delay and low-jitter deterministic data transmission capability through mechanisms such as clock synchronization, data scheduling and Ethernet configuration, so as to improve network operation safety, intelligence and operation and maintenance convenience and provide reliable technical guarantee for safe and stable operation of the network.

The TSN switch chip of the embodiments of the present disclosure is further configured to support time-sensitive network protocol standards on the basis of supporting the functions of a conventional ethernet switch chip. High performance and low latency management and control functions within the ethernet subnetwork and data plane protocol processing functions can be provided. Responsible for handling various communication protocols including the underlying protocols of IEEE, IETF, IEC and the like and protocols in terms of Time Sensitive Networks (TSNs). Two-layer/three-layer line speed forwarding of data packets in an Ethernet is provided.

A TSN protocol stack is built in the TSN switching chip, and the TSN protocol stack is implemented according to a time-sensitive network protocol standard family, including common protocols such as: the standard of 802.1As protocol, the standard of 802.1Qbv protocol, the standard of 802.1Qbu protocol, the standard of 802.1Qci protocol, the standard of 802.1cb protocol, the standard of 802.1Qcc protocol, the standard of 802.1Qcr protocol, the standard of 802.1Qat protocol and the standard of 802.1Qcp protocol. The TSN protocol stacks are based on componentized construction, can be flexibly tailored, and are loosely coupled to each other.

When the TSN exchange chip receives the network message, the protocol type field of the network message can be acquired first. And judging the protocol standard corresponding to the network message according to the protocol type field. And then distributing the network message to threads corresponding to the protocol standard for processing. The threads process the network messages according to the corresponding protocol standards. In the embodiment of the present specification, when it is determined that the network packet meets the time-sensitive network protocol standard according to the protocol type field, the time-sensitive network protocol standard that meets the network packet is determined in the TSN protocol stack as the target protocol standard of the network packet, such as the 802.1Qbv protocol standard. And then, distributing the network message to a target thread corresponding to the target protocol standard, wherein the target thread can process the network message according to the target protocol standard.

In the TSN switch module of the embodiment of the present disclosure, a quad core Cortex-A7A 40i processor may be employed. The processor is configured with a 1.2GHz main frequency, DDR3 with memory capacity of 2GB, and EMMC with memory capacity of 8 GB. The Linux operating system is carried, so that network data can be processed and the operating system can be operated in real time, the system is managed and the performance is monitored according to the operating instruction of a user, and meanwhile, the operating condition of the TSN exchange module is fed back to the user in real time.

In the embodiment of the present specification, the TSN switching chip is configured with an SPI interface and an RGMII interface. The processor can be connected with the TSN exchange chip through the SPI interface to perform initialization configuration on the TSN exchange chip so that the TSN exchange chip can normally operate; and the network management is carried out on the TSN exchange chip by connecting the RGMII network port with the TSN exchange chip.

According to the TSN Ethernet switching module of the embodiment of the specification, on the basis of supporting the functions of the traditional switching chip, the TSN switching chip is configured to be capable of supporting a time-sensitive network protocol standard. When the TSN exchange chip receives the network message, the network message conforming to the basic protocol can be processed, and the network message conforming to the Time Sensitive Network (TSN) protocol standard can be processed. The TSN switching module has accurate flow scheduling capability, and can ensure the common network high-quality data transmission of various services. The TSN Ethernet switching module of the embodiment of the specification improves the compatibility and the interoperability of the Ethernet, meets the requirements of industrial scenes by utilizing a single switching chip, and improves the reliability of the TSN Ethernet switching module.

In some embodiments of the present disclosure, when a TSN switch chip sends a target network packet according to a time-sensitive network protocol standard, an sending time point of the target network packet sent by the TSN switch chip is added to the target network packet, so that a MAC interface sending the target network packet can identify the target network packet.

Because the TSN exchange chip should follow the accurate time synchronization protocol standard in the time sensitive network protocol standard family when receiving or transmitting the target network message conforming to the time sensitive network protocol standard, the network clock synchronization in the whole communication network is ensured. I.e. to ensure that the time or frequency difference between the individual nodes in the overall communication network remains within a reasonable error level. Thus, for the precise time synchronization protocol standard, the target network message may be a one-step message. When the TSN switch chip sends a one-step message, such as a one-step sync message, the time point sent from the TSN switch chip needs to be added to the message. The MAC interface of the outlet for sending the one-step message can identify the one-step message, and the current time 48-bit nanoseconds and 32-bit nanoseconds are obtained from the time management module of the TSN exchange chip at the correct positions. For the one-step pdelay_resp message, the correction_field field needs to be updated on the MAC interface of the egress, and the local residence time is updated. I.e. by identifying the message on the MAC interface of the egress, the MAC interface calculates the residence time and updates to the correct location.

In some embodiments of the present description, the time sensitive network protocol standard comprises a precision time synchronization protocol standard. When the TSN exchange chip receives the first type network message conforming to the accurate time synchronization protocol standard, the TSN exchange chip marks the time stamp information of the network message and caches the time stamp information into the first-in first-out memory. And determining master-slave clock differences according to master clock and time stamp information of the data transmission link, and calibrating clock sources of the TSN Ethernet switching module by using the master-slave clock differences so as to carry out time synchronous transmission on the first type network messages. Wherein the master clock is determined based on the processor executing an optimal master clock algorithm.

The family of time sensitive network protocol standards includes the 802.1As precision time synchronization protocol standards. The heart of the precision time synchronization protocol standard is the time stamping mechanism. PTP (Precision Time Protocol ) messages, when coming in and going out of an 802.1AS enabled port, sample the local Real Time Clock (RTC) according to protocol triggers. Comparing its RTC value with the corresponding CM information from the port; the RTC clock value is matched to the time of the PTP domain by using a path delay measurement and compensation technology. When the PTP synchronization mechanism covers the whole AVB local area network, clock adjustment and frequency matching algorithms can be accurately realized through periodic PTP message exchange among network node devices. Eventually, all PTP nodes will synchronize to the same "Wall Clock" time, i.e., master Clock time. In a maximum 7-hop network environment, PTP can guarantee clock synchronization errors within 1 μs.

In the embodiment of the present disclosure, a time synchronization system is configured in the TSN ethernet switching module. The time synchronization system at least comprises two time stamp modules, namely a sending time stamp module and a receiving time stamp module. The time stamp module is divided into a message analysis unit, a time stamp marking unit and a time stamp caching unit. When the TSN exchange chip receives or transmits the first type network message, the first type network message between the MAC layer and the physical layer is directly transmitted to the time stamp module for processing.

The function of the time stamp module is to mark time stamp information of the network message when the TSN exchange chip receives and transmits the network message. And judging whether the received network message is an 802.1AS event message, namely a first type network message. If so, the marked time stamp information is cached in a first-in first-out memory. If not, the marked time stamp information is discarded. Illustratively, a timestamp event may be generated when a GPTP event message is sent or received, the timestamp event occurring when a timestamp point of the event message passes a boundary between a node in the local area network and the local area network.

Referring to the flowchart shown in fig. 2, when the timestamp module receives the network packet, the timestamp module pulls up the receiving flag bit by one clock cycle, and automatically reads the timestamp information in GMII format sent by the clock module, where the timestamp includes a time point after the ethernet frame initiator and before the destination MAC address. I.e. after receiving 7 consecutive 0x55,1 0x d5, the time stamping module stamps the time stamps. And then the message analysis module detects the received network message, and firstly detects the protocol type field. If the protocol type field is detected to be 0x88F7, the network message is a GPTP message, the MessageType field is continuously detected, the highest bit indicates whether the message is an 802.1AS event message, 0 indicates the 802.1AS event message, and 1 indicates a general basic message. If the detected most significant bit is 1, the marked time stamp information is directly discarded, and if the detected most significant bit is 0, the time stamp information is stored in the first-in first-out memory FIFO without overflow of the first-in first-out memory FIFO. If the detected protocol type field is 0x0800, the message is an IP message, and the detection is continued, otherwise, the message stops the detection, and the timestamp information is discarded. After detecting that it is an IP message, detecting the protocol part of the IP message header. If 17, the message accords with the UDP protocol, the detection is continued, otherwise, the message stops the detection, and the timestamp information is discarded. After detecting that the packet accords with the UDP protocol, continuing to detect whether the packet is a GPTP packet. If yes, continuing to detect the MessageType field, and determining whether the message is an 802.1AS event message. If the message belongs to the 802.1AS event message, the time stamp information is stored in the FIFO under the condition that the FIFO is not overflowed.

In the embodiments of the present description, when the time synchronization system needs to calculate the master-slave clock difference using the time stamp information, the time stamp information may be read directly from the FIFO in case the FIFO is not empty. The master clock of the data transmission link is already obtained by executing an optimal master clock algorithm on the processor of the TSN ethernet switching module. And determining master-slave clock differences according to master clock and time stamp information of the data transmission link, and calibrating clock sources of the TSN Ethernet switching module by using the master-slave clock differences so as to carry out time synchronous transmission on the first type network messages. Ensuring that the time or frequency difference between the nodes in the overall data transmission link remains within a reasonable level of error.

Specifically, referring to fig. 3, the process of implementing time synchronization by the time synchronization system in the embodiment of the present specification includes the following steps:

s310, initializing system parameters. Before the time synchronization system operates, parameter initialization work is firstly carried out on each node in the data transmission link, and preparation is carried out for the subsequent time synchronization process.

S320, it is confirmed whether the ieee802.1as protocol standard is supported. And judging whether a node which does not support the IEEE802.1AS protocol standard exists in the data transmission link through message transmission and reception by utilizing a peer-to-peer delay mechanism, and if so, terminating the program.

S330, selecting the optimal master clock. After each node in the data transmission link is confirmed to support the IEEE802.1AS protocol, each node operates an optimal master clock selection algorithm (Best Master Clock Algorithm, BMCA) until an optimal master clock is selected, and a time synchronization spanning tree is constructed by taking the optimal master clock as a root to generate a time synchronization path.

S340, path delay measurement. After the time synchronization path is generated, each node in the data transmission link calculates the path delay between the nodes by exchanging the message with the time stamp information, and records the measurement result for the subsequent time synchronization measurement.

S350, time synchronization measurement. After the path delay measurement, the time synchronization system takes the master clock as a root, transmits time synchronization messages with delay measurement results step by step along a time synchronization path, and after each node on the path receives the time synchronization messages, analyzes the messages to extract time stamp information, and calculates the time deviation between the self clock and the master clock.

S360, calibrating the local clock to realize time synchronization. And each node of the data transmission link calibrates the time of the local clock source according to the time deviation, so as to realize time synchronization with the master clock.

In some embodiments of the present description, the time-sensitive network protocol standard includes a time-sensitive traffic scheduling protocol standard and a frame preemption mechanism protocol standard. When receiving the second type network message conforming to the time sensitive flow dispatching protocol standard, the TSN exchange chip uses the thread corresponding to the time sensitive flow dispatching protocol standard to transmit and select the second type network message according to the time sensitive flow dispatching protocol standard. When receiving the third type network message conforming to the frame preemption mechanism protocol standard, the TSN exchange chip performs frame preemption processing on the third type network message according to the frame preemption mechanism protocol standard by using a thread corresponding to the frame preemption mechanism protocol standard.

In the embodiment of the present disclosure, the TSN switch chip of the TSN ethernet switch module further creates a thread corresponding to the time-sensitive traffic scheduling protocol standard, and when receiving a second type network packet conforming to the time-sensitive traffic scheduling protocol standard, distributes the second type network packet to the thread, so that the thread performs transmission selection processing on the second type network packet according to the time-sensitive traffic scheduling protocol standard.

Specifically, the time-sensitive scheduling protocol standard is to add a gating switch on the basis of a traditional queue. The dequeue period of the flow in each queue is controlled by adding a transmission gate (Transmission Gate) after the transmission selection algorithm (Transmission Selection Algorithm). The time of the transmission gate is arranged in a gating list (Gate Control List). As shown in fig. 4, in a scheduling period, corresponding entries in the gating list are read at each time point, transmission gate states of 8 priority queues are obtained, and data transmission is controlled by a door opening and closing mechanism, so that a scheduling result is determined.

In the traditional scheduling mode, a transmission selection unit only needs to directly select a message to forward from 8 queues based on a complete priority or weight mode according to a scheduling strategy, but a gate is added on each queue based on a time-sensitive traffic scheduling mode, and scheduling can only be participated if the gate is opened, or scheduling cannot be participated, so that certain queues are shielded from a scheduling list physically, and the problem of priority of the queues is avoided.

Time-aware shaper (TAS) based scheduling mechanism is designed for lower time granularity and more stringent industrial applications. TAS is defined by the ieee802.1qbv time sensitive traffic scheduling protocol, which is a mechanism that dynamically provides on/off control for egress queues based on a preset periodic Gate Control List (GCL). TAS runs on a globally synchronized clock across a time-sensitive network. 802.1Qbv defines a Time window and is a Time-triggered network (Time-triggered). This window is predefined in this mechanism, and the TAS can transmit time-sensitive data packets over the network with minimal delay and jitter with the help of a time window, but it needs to centrally configure and manage all shapers in the network elements. The gate control list is scanned periodically and the transmission ports are opened for the different queues in a predefined order.

Referring to fig. 5, the egress hardware of the tsn switch chip is provided with 8 queues, and the dequeue period of the flow in each queue is controlled by adding a transmission gate after the transmission selection algorithm. The time of the transmission gate is arranged in the gating list. And in a scheduling period, reading corresponding entries in the gating list at each time point to obtain the transmission gate states of 8 priority queues, thereby determining a scheduling result.

In order to ensure that the network is idle before the transmission of the data messages, a protection bandwidth needs to be set in the TAS mechanism before the whole transmission starts. The guard bandwidth uses the maximum ethernet frame transmission length to ensure that even in the worst case standard ethernet frames are transmitted, the GCL is not occupied with ports until the next cycle is restarted.

In the embodiment of the present description, the TSN switch chip of the TSN ethernet switch module further creates a thread corresponding to the frame preemption mechanism protocol standard. When the TSN exchange chip receives the third-class network message conforming to the frame preemption mechanism protocol standard, the third-class network message is distributed to the thread, so that the thread performs frame preemption processing on the third-class network message according to the frame preemption mechanism protocol standard.

In some cases, the TAS mechanism can have 2 major problems: (1) A certain sampling time is consumed under the condition of protecting the bandwidth; (2) The risk of low priority inversion is based on which a preemptive MAC mechanism is designed.

Referring specifically to fig. 6, under this frame preemption mechanism, the MAC layer egress of the transmission control is divided into two service interfaces, preemptible MAC (pMAC) and high-speed MAC (eMAC). The high-speed eMAC with high priority can preempt PMAC with low priority, and after entering a data stack, the PMAC is transmitted after being aggregated and packaged after waiting for eMAC data transmission to be completed.

Time sensitive traffic will suffer from lower jitter when node devices of the full network enable preemption. When frame preemption is enabled with TAS, the Guard Band between the unprotected time window of preemptible traffic and the fast traffic protected time window can be significantly reduced, thereby making TAS implementation more efficient. By frame preemption, guard bands can be reduced to the shortest low priority frame fragments.

In some embodiments of the present description, the TSN switch chip is configured with several Serdes interfaces. The Serdes interface is configured as a Qsgmii interface supporting a 5Gbps transmission rate or as a 10GBase-R interface supporting a 10.3125Gbps transmission rate.

Specifically, referring to fig. 7, the TSN switch chip of the embodiment of the present disclosure designs several Serdes interfaces in hardware, which may be typically 10 Serdes interfaces. Wherein, 6 Serdes interfaces can be configured as Qsgmii interfaces supporting 5Gbps transmission rate, and 4 Serdes interfaces can be configured as 10GBase-R interfaces supporting 10.3125Gbps transmission rate. Two external interfaces can be matched according to the requirements so as to realize various photoelectric interface combined products.

In some embodiments of the present description, the switching module further comprises: a plurality of PHY chips. The PHY chip is connected with the TSN switching chip through the Qsgmii interface so that the Qsgmii interface supports 8B/10B conversion.

With continued reference to fig. 7, the TSN ethernet switching module further includes a plurality of PHY chips connected to the TSN switching chips through a Qsgmii interface. The TSN switching chip may access the control PHY chip through MDIO/MDC. The rate of the SerDes interface is increased because of the 8B/10B conversion. Whereas 8B/10B conversion is the operation of the PHY chip. Therefore, after the PHY chip is connected with the Qsgmii interface configured by the Serdes interface, the Qsgmii interface can support the 5Gbps transmission rate. The main function of 8B/10B conversion is scrambling code, so that overlong conditions of continuous 0 and continuous 1 in the signal do not occur, and extraction of clock information is affected.

In some embodiments of the present description, the PHY chip is configured with a network interface. The PHY chip is connected to an external device through a network interface. The TSN exchange chip carries out auto-negotiation with the external equipment through the PHY chip so as to exchange signals with the agreed running speed and duplex mode.

The PHY chip can adopt a YT8618 chip and can support IEEE 802.3 1000Base-T/100BaseTX/10Base-Te. Eight port PHY chips integrate 10/100/1000M Ethernet transceivers supporting two QSGMII (5 Gbps high speed serial interface) interfaces in 10/100/1000M mode. And supports IEEE 802.3az high-efficiency energy-saving Ethernet, synchronous Ethernet clock output function and the like. The main function of the PHY chip is to process the message data transmitted by the received TSN exchange chip, then to convert the parallel data into serial stream data, then to encode the data according to the encoding rule of the physical layer, and then to convert the data into analog signals to send out.

As shown in fig. 7, the eight port PHY chip is configured with an RJ45 network interface. The external device may be connected to the PHY chip through an RJ45 network interface. The PHY chip may also be connected to a higher level network through an RJ45 network interface. The TSN exchange chip can conduct auto-negotiation with external equipment through the PHY chip to agree on port operation rate and duplex mode interaction signals. The 1G port single-hop minimum delay is 5us, the 10G port single-hop minimum delay is 1us, jitter is less than 500ns, time synchronization accuracy is less than 20ns, and the bidirectional 128Gbps 64Byte packet long line speed forwarding capability is provided.

In some embodiments of the present description, the switch module further includes an FPGA processing chip. The FPGA processing chip is connected with the TSN exchange chip through a 10GBase-R interface and is used for converting photoelectric signals.

The FPGA processing chip can be used for optical signal conversion processing. The multi-megalight signal can be converted into gigabytes or hundred megabytes, so that the requirements of different application scenes are met. As shown in fig. 7, the FPGA processing chip is configured with a plurality of SFP interfaces for connecting to external devices or an upper network.

In some embodiments of the present description, the switching module further comprises: EEPROM memory, clock chip and TMP temperature monitor. The processor accesses and manages the EEPROM memory, the clock chip, and the TMP temperature monitor based on the serial communication bus.

The switching module further comprises an EEPROM memory, a clock chip and a TMP temperature monitor. The EEPROM memory is an electrified erasable programmable read-only memory. The clock chip RTC is an integrated circuit. Referring to fig. 7, the processor can access and manage the EEPROM memory, the clock chip, and the TMP temperature monitor based on the serial communication bus i_c.

In some embodiments, the processor is further configured with EMMC memory. EMMC (Embedded Multi Media Card) is an embedded memory standard. EMMC integrates a controller in the package that provides a standard interface and manages the flash memory. EMMC is used for program storage in the embodiments of the present description.

In other embodiments, the processor is further configured with a NAND flash memory for configuring the boot program to boot. In addition, the processor is also provided with a USB interface for USB debugging; configuring UART interface for serial port debugging; the RGMII interface is configured to provide network port debugging. The processor is configured with interfaces for serial port debugging and network port debugging, so that a user can conveniently manage and configure the TSN Ethernet switching module.

In summary, referring to fig. 8, the TSN switching chip of the embodiment of the present disclosure includes the following service interfaces: the Serdes interface can support 5Gbps and 10.3125Gbps and is used for configuring 6 QSFMII interfaces and four 10GBase-R interfaces respectively. The PCS interface can be used for completing the physical coding of the QSMII interface and the 10GBase-R interface. The PTP interface is used for completing the processing of PTP protocol messages and supporting one-step and two-step modes, and the main functions comprise: message editing, timestamp editing, updating CF fields, updating CheckSum, etc. A MAC interface for performing ethernet framing functions, comprising: adding Preamble, calculating/checking CRC, IPG control, receiving and transmitting Pause frame, MIB statistics, etc. The TSN exchange chip simultaneously realizes eMac and pMac functions specified by IEEE 802.3br protocol, and mCRC calculation and the like so as to support a frame preemption function.

With continued reference to fig. 8, the TSN switch chip is further configured with Ingress packet processing (Ingress packet) for implementing the various message processing specified by the base protocol and the TSN protocol. Memory management (Traffic Manager), the main functions include memory control, admission control, message replication, queue management, scheduler, traffic shaping, flow control, etc., and also implement time-aware scheduling (TAS) and frame preemption functions specified by the TSN protocol. And the time synchronization Engine (PTP Engine) is used for realizing the time synchronization function specified by the IEEE1588v2 and 802.1AS-Rev protocols and simultaneously realizing the gating state machine function specified by the IEEE 802.1Qbv protocols. And the Egress packet processing (Egress PIPeline) is used for completing the protocol processing of the Egress message and the message editing function.

In addition to the interfaces described above, the TSN switch chip is also configured with other interfaces (Misc Intf) as shown in fig. 8. Comprising the following steps: the CPUGGAC interface is used for exchanging data packets with the external CPU by the TSN exchange chip, the message is provided with a message header regulated internally, and the output of the interface is an RGMII interface. And the MDIO interface is used for configuration and management of the PHY chip. SPI interface, configuration channel of chip. And the inter interface is used for generating an Interrupt signal of the TSN exchange chip. The ComTOD interface realizes the time synchronization among interconnected devices by the China Mobile high precision time synchronization 1PPS+TOD time interface Specification, and input/output signals of the interface are as follows: 1PPS and TOD. The SyncE interface realizes the output of the two paths of interface recovered clocks and is used for constructing the synchronous Ethernet.

In correspondence to the above embodiment, as shown in fig. 9, the present embodiment further provides a TSN network management system, where the TSN network management system includes an application layer 910, a control layer 920, and a link layer 930. The TSN ethernet switching module of any of the above embodiments is applied to the link layer 930.

Specifically, the TSN network management system is located at a control layer and an application layer of the three-layer network architecture. The northbound provides a fine-grained REST API interface, providing the application layer with the ability to configure and sense the network state. The south direction adopts the standard NETCONF protocol to realize unified configuration management of heterogeneous exchange manufacturers. The TSN network management system has the global topological bandwidth and service flow configuration requirements of the system. The TSN network management system can conduct global planning and scheduling according to global topology bandwidth and flow configuration, and complete calculation and configuration of scheduling strategies. The TSN network management system realizes unified management, configuration and monitoring of forwarding equipment supporting a time-sensitive network protocol and end equipment, and simultaneously realizes automatic acquisition of service requirements of the end equipment, and dynamic configuration and management of the system. The TSN network management system application layer provides a visual configuration management interface and provides manual configuration management and state monitoring functions for users. In addition, the application layer of the TSN network management system supports interaction with various application protocols and service interaction with the application layer. The TSN network management system supports configuration management of a network, comprises basic two-layer network configuration management and TSN characteristic configuration management, and comprises a plurality of TSN planning scheduling algorithms such as 802.1Qav, 802.1Qbv, 802.1Qci, IEEE 802.1Qbu, 802.1Qch, 802.1CB and the like.

Corresponding to the above embodiment, the embodiment of the present specification further provides a TSN switching system based on the electric power internet of things. The TSN switching system includes the TSN ethernet switching module of any of the above embodiments.

Referring to fig. 10, the TSN switching system includes:

the real-time operating system Linux, i.e. a host real-time operating system in an embedded system, is used for scheduling and managing hardware resources of the embedded system and providing a programming and managing interface for upper-layer applications.

BSP (Board Support Package), a board-level support package, provides the boot programs (Bootload), kernel (Kernel), root file system (Rootfs), and tool chains and board-level driver packages required to build an embedded operating system.

The system comprises an operating system and a board level abstract layer, wherein the layer abstracts a programming interface and a hardware access interface of the operating system, and aims to enable the network operating system to be independent of a host operating system and different hardware boards, so that the network operating system has good portability, reusability and expandability.

The ethernet chip SDK (Software Development Kit) is a software development kit for network chips such as a bridge chip and a network side chip.

And the hardware abstraction layer is used for independently separating the OSI base protocol stack and the TSN network protocol stack from specific chips and hardware, so that software above the service and control protocol layers is decoupled from the specific hardware and the operating system, and the software system is convenient to adapt to different chips and hardware platforms.

The base protocol stack: the base protocol stacks are realized according to IEEE, IETF, IEC and other standards, and are constructed based on componentization and are loosely coupled with each other.

TSN protocol stack: the TSN network protocol stack is implemented according to the TSN standard family, including commonly used protocols such as: 802.1AS, 802.1qbv, 802.1qbu, 802.1qci, 802.1cb, 802.1qcc. The implementation of the TSN protocol stack is based on componentized construction, can be flexibly tailored, and is loosely coupled to each other.

Based on the standard object access layer, according to IEEE, IETF, IEC and other standards, the management object of the TSN protocol stack provides a unified programming interface for the application and management layer in the form of a lightweight database, so that the application and management layer is decoupled from the service and control protocol layer.

And the application management layer is used for writing a user interface, a northbound interface and an application program required by the network management system based on the object access layer.

The power physical network application layer is an interface between a user and network resources aiming at an operating system for realizing management and control of the network resources under a network environment by the power system application layer. The power physical network operating system is established on an independent operating system, and provides a bridge for network users to use network system resources.

Corresponding to the above embodiment, the embodiment of the present disclosure further provides a method for processing a message of the electric power internet of things. The electric power internet of things message processing method is applied to the TSN switching chip in the TSN Ethernet switching module. The TSN exchange chip is provided with an SPI interface and an RGMII network interface. The TSN switching chip is configured to support time-sensitive network protocol standards. The TSN exchange chip is connected with the processor of the TSN Ethernet exchange module through the SPI interface and the RGMII network interface. As shown in fig. 11, the method for processing the electric power internet of things message includes:

S1110, when receiving the network message, acquiring a protocol type field of the network message.

S1120, if the network message accords with the time sensitive network protocol standard based on the protocol type field, determining a target protocol standard which accords with the network message in the TSN protocol stack according to the protocol type field.

S1130, distributing the network message to a target thread corresponding to the target protocol standard. Wherein the target thread is a processing thread assigned for the target protocol standard.

S1140, processing the network message according to the target protocol standard.

According to the electric power Internet of things message processing method, on the basis of supporting functions of a traditional switching chip, the TSN switching chip can also support time-sensitive network protocol standards. And constructing a TSN protocol stack in the TSN exchange chip. Various message protocol standards conforming to the time sensitive network protocol standard are stored in the TSN protocol stack. Illustratively, as shown in fig. 12, when the TSN switch chip receives a network packet, it determines whether the network packet conforms to a time-sensitive network protocol standard based on the protocol type field. And distributing the network message conforming to the time-sensitive network protocol standard to a target thread corresponding to the target protocol standard, and processing the network message according to the target protocol standard. In the embodiment of the present disclosure, a SYNC message processing thread, a pdelay_rep message processing thread, a follow_up message processing thread, a delay_rep message processing thread, a pdelay_rep_follow up message processing thread, an anonance message processing thread, a signaling message processing thread, a Management message processing thread, an LLDP message processing thread, an SRP message processing thread, an SNVP message processing thread, and the like are pre-configured. With continued reference to fig. 12, in the case that the network port of the TSN switch chip receives a TSN protocol packet conforming to the time-sensitive network protocol standard, it may first determine whether the packet conforms to the IEEE1588v2 protocol. If yes, judging the specific type of the TSN protocol message. Illustratively, if the received SYNC message is a SYNC message, the SYNC message is sent to a SYNC message processing thread to process the SYNC message through SYNC message processing logic.

According to the method for processing the electric power internet of things message, not only can the network message conforming to the basic protocol be processed, but also the network message conforming to the Time Sensitive Network (TSN) protocol standard can be processed. The method has accurate flow scheduling capability, and can ensure the common network high-quality data transmission of multiple services. The electric power internet of things message processing method improves the compatibility and interoperability of the Ethernet, meets the requirements of industrial scenes by utilizing a single switching chip, and improves the reliability of the TSN Ethernet switching module.

In some embodiments of the present disclosure, the method for processing a packet of the electric power internet of things further includes: when a target network message conforming to the time sensitive network protocol standard is transmitted, the sending time point of the target network message transmitted by the TSN exchange chip is added into the target network message, so that the MAC interface for transmitting the target network message can be identified to the target network message.

In some embodiments of the present description, the time sensitive network protocol standard comprises a precision time synchronization protocol standard. Processing the network message according to the target protocol standard, including: and marking the time stamp information of the network message when the first type of network message conforming to the accurate time synchronization protocol standard is received. The time stamp information is buffered to a first in first out memory. And determining master-slave clock differences according to master clock and time stamp information of the data transmission link, and calibrating clock sources of the TSN Ethernet switching module by using the master-slave clock differences so as to carry out time synchronous transmission on the first type network messages. Wherein the master clock is determined based on the processor executing an optimal master clock algorithm.

It should be noted that, for details not disclosed in the method for processing the electric power internet of things message in this embodiment, please refer to details disclosed in the embodiment of the TSN ethernet switching module in the embodiment of this specification, which are not described herein again.

Corresponding to the above embodiments, the present specification further proposes a computer-readable storage medium. The electric power internet of things message processing program is stored on the electric power internet of things message processing program, and when the electric power internet of things message processing program is executed by the processor, the electric power internet of things message processing method according to any one of the embodiments is realized.

According to the computer readable storage medium of the embodiment of the present disclosure, when the power internet of things message processing program is executed by the processor, not only the network message conforming to the base protocol but also the network message conforming to the Time Sensitive Network (TSN) protocol standard can be processed. The method has accurate flow scheduling capability, and can ensure the common network high-quality data transmission of multiple services. The electric power internet of things message processing method improves the compatibility and interoperability of the Ethernet, meets the requirements of industrial scenes by utilizing a single switching chip, and improves the reliability of the TSN Ethernet switching module.

It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as a ordered listing of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

It should be understood that portions of this specification may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present specification. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Furthermore, the terms "first," "second," and the like, as used in the embodiments of the present specification, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implicitly indicating the number of technical features indicated in the embodiments. Thus, the definition of a term "first," "second," or the like in an embodiment of this specification can expressly or implicitly indicate that at least one such feature is included in the embodiment. In the description of the present specification, the word "plurality" means at least two or more, for example, two, three, four, etc., unless explicitly defined otherwise in the embodiments.

Although embodiments of the present disclosure have been shown and described above, it should be understood that the above embodiments are illustrative and not to be construed as limiting the present disclosure, and that variations, modifications, alternatives, and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the present disclosure.

Claims (15)

1. The utility model provides a TSN Ethernet switching module, its characterized in that, the Ethernet switching module includes: a processor, a TSN switching chip; the TSN exchange chip is provided with an SPI interface and an RGMII network port; the TSN switching chip is configured to support a time-sensitive network protocol standard;

The processor is connected with the TSN exchange chip through the SPI interface to perform initialization configuration on the TSN exchange chip, and is connected with the TSN exchange chip through the RGMII network interface to perform network management on the TSN exchange chip;

when the TSN exchange chip receives a network message, acquiring a protocol type field of the network message, and if the network message is judged to accord with the time-sensitive network protocol standard based on the protocol type field, distributing the network message to a target thread corresponding to a target protocol standard; wherein the target protocol standard is a time sensitive network protocol standard according to which the network message is determined to be in accordance with the protocol type field in a TSN protocol stack; the target thread is a processing thread distributed for the target protocol standard, and the target thread is used for processing the network message according to the target protocol standard.

2. The switch module of claim 1, wherein when the TSN switch chip sends a target network packet according to the time-sensitive network protocol standard, an sending time point of the target network packet sent by the TSN switch chip is added to the target network packet, so that a MAC interface sending the target network packet can identify the target network packet.

3. The switching module of claim 1, wherein the time sensitive network protocol standard comprises a precision time synchronization protocol standard;

when the TSN exchange chip receives a first type of network message conforming to the accurate time synchronization protocol standard, marking time stamp information of the network message, and caching the time stamp information into a first-in first-out memory; determining master-slave clock differences according to a master clock of a data transmission link and the timestamp information, and calibrating a clock source of the Ethernet switching module by using the master-slave clock differences so as to perform time synchronous transmission on the first-class network messages; wherein the master clock is determined based on the processor executing an optimal master clock algorithm.

4. The switching module according to claim 1, wherein the time-sensitive network protocol standard comprises a time-sensitive traffic scheduling protocol standard and a frame preemption mechanism protocol standard;

when receiving a second type network message conforming to the time sensitive flow scheduling protocol standard, the TSN exchange chip performs transmission selection processing on the second type network message according to the time sensitive flow scheduling protocol standard by utilizing a thread corresponding to the time sensitive flow scheduling protocol standard;

When receiving a third type network message conforming to the frame preemption mechanism protocol standard, the TSN exchange chip uses a thread corresponding to the frame preemption mechanism protocol standard to perform frame preemption processing on the third type network message according to the frame preemption mechanism protocol standard.

5. The switch module as in claim 1 wherein the TSN switch chip is configured with a plurality of Serdes interfaces; the Serdes interface is configured as a Qsgmii interface supporting a 5Gbps transmission rate or as a 10GBase-R interface supporting a 10.3125Gbps transmission rate.

6. The switch module as in claim 5, further comprising: a plurality of PHY chips; the PHY chip is connected with the TSN exchange chip through the Qsgmii interface so that the Qsgmii interface supports 8B/10B conversion.

7. The switch module as in claim 6, wherein the PHY chip is configured with a network interface; the PHY chip is connected with external equipment through the network interface;

the TSN exchange chip performs auto-negotiation with external equipment through the PHY chip to exchange signals with agreed operation rate and duplex mode.

8. The switch module as in claim 5, further comprising an FPGA processing chip; the FPGA processing chip is connected with the TSN exchange chip through the 10GBase-R interface and is used for converting photoelectric signals.

9. The switching module of claim 1, further comprising: EEPROM memory, clock chip and TMP temperature monitor;

the processor accesses and manages the EEPROM memory, the clock chip, and the TMP temperature monitor based on a serial communication bus.

10. The TSN network management system is characterized by comprising an application layer, a control layer and a link layer; the switching module of any one of claims 1 to 9 being applied on the link layer.

11. A TSN switching system based on the internet of things of electric power, characterized by comprising the switching module of any one of claims 1 to 9.

12. The electric power internet of things message processing method is characterized by being applied to a TSN (traffic channel) switching chip in an Ethernet switching module, wherein the TSN switching chip is provided with an SPI (serial peripheral interface) and an RGMII (radio frequency identification interface); the TSN switching chip is configured to support a time-sensitive network protocol standard; the TSN exchange chip is connected with the processor of the Ethernet exchange module through the SPI interface and the RGMII network interface; the method comprises the following steps:

When a network message is received, acquiring a protocol type field of the network message;

if the network message accords with the time-sensitive network protocol standard based on the protocol type field, determining a target protocol standard which accords with the network message in a TSN protocol stack according to the protocol type field;

distributing the network message to a target thread corresponding to the target protocol standard; wherein the target thread is a processing thread allocated for the target protocol standard;

and processing the network message according to the target protocol standard.

13. The method according to claim 12, wherein the method further comprises:

when a target network message conforming to the time sensitive network protocol standard is sent, the sending time point of the target network message sent by the TSN switching chip is added to the target network message, so that the MAC interface for sending the target network message can identify the target network message.

14. The method of claim 13, wherein the time sensitive network protocol standard comprises a precision time synchronization protocol standard; the processing the network message according to the target protocol standard comprises the following steps:

When a first type network message conforming to the accurate time synchronization protocol standard is received, marking time stamp information of the network message;

caching the timestamp information into a first-in first-out memory;

determining master-slave clock differences according to a master clock of a data transmission link and the timestamp information, and calibrating a clock source of the Ethernet switching module by using the master-slave clock differences so as to perform time synchronous transmission on the first-class network messages; wherein the master clock is determined based on the processor executing an optimal master clock algorithm.

15. A computer readable storage medium, wherein an electric power internet of things message processing program is stored thereon, which when executed by a processor, implements the electric power internet of things message processing method according to any of claims 12-14.

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