CN115985266A - Gate drive circuit, display panel and display device - Google Patents
Gate drive circuit, display panel and display device Download PDFInfo
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- CN115985266A CN115985266A CN202310116073.6A CN202310116073A CN115985266A CN 115985266 A CN115985266 A CN 115985266A CN 202310116073 A CN202310116073 A CN 202310116073A CN 115985266 A CN115985266 A CN 115985266A
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Abstract
The embodiment of the application provides a gate drive circuit, a display panel and a display device, wherein, the gate drive circuit includes: including cascaded multirow shift register unit, the first input of the shift register unit of the (N + 1) th row is connected to the output of the shift register unit of the nth row, the second input of the shift register unit of the (N + 1) th row is connected to the output of the shift register unit of the (N + 2) th row, the shift register unit includes: the first input circuit is connected with the first high-level signal end, the first control signal end and the first input end; the second input circuit is connected with a second high-level signal end, a second control signal end, a first node and a second input end; the first control circuit is connected with the first clock signal end, the first node and the output end of the shift register; and the second control circuit is connected with the third high-level signal end, the second clock signal end and the second node. The technical scheme of the embodiment of the application can avoid the occurrence of a plurality of outputs of the shift register unit.
Description
Technical Field
The application relates to the technical field of display, in particular to a gate driving circuit, a display panel and a display device.
Background
Currently, the Gate driving circuit is usually formed on an Array substrate of the liquid crystal display by an Array process, i.e., a Gate driver on Array (GOA) process. The gate driving circuit usually includes a plurality of cascaded GOA units, and currently, the Output abnormality of the GOA unit is usually a plurality of outputs (Multi-outputs) of the GOA unit, which affects the stability of the display device.
Disclosure of Invention
Embodiments of the present application provide a gate driving circuit, a display panel and a display device to solve or alleviate one or more technical problems in the prior art.
As an aspect of the embodiments of the present application, there is provided a gate driving circuit including cascaded multiple rows of shift register units, wherein a first input terminal of an N +1 th row of shift register units is connected to an output terminal of an nth row of shift register units, a second input terminal of the N +1 th row of shift register units is connected to an output terminal of an N +2 th row of shift register units, and the shift register unit includes: a first input circuit connected to the first high-level signal terminal, the first control signal terminal, the first node, and the first input terminal of the shift register unit, the first input circuit configured to: under the control of a signal of a first high-level signal end and a signal of a first input end, a signal of a first control signal end is output to a first node; a second input circuit connected to a second high-level signal terminal, a second control signal terminal, the first node, and a second input terminal of the shift register unit, the second input circuit configured to: under the control of the signal of the second high-level signal end and the signal of the second input end, the signal of the second control signal end is output to the first node; a first control circuit connected to the first clock signal terminal, the first node, and the output terminal of the shift register unit, the first control circuit configured to: outputting an output signal from an output terminal under the level control of the first node; a second control circuit connected to the third high level signal terminal, the second clock signal terminal, and the second node, the second control circuit configured to: and outputting the second clock signal to the second node under the control of the second clock signal terminal.
In one embodiment, the first input circuit includes: the grid electrode of the first transistor is used for connecting a first high-level signal end, and the first pole of the first transistor is used for connecting a first input end; and the grid electrode of the second transistor is connected to the second pole of the first transistor, the first pole of the second transistor is used for connecting the first control signal end, and the second pole of the second transistor is connected to the first node.
In one embodiment, the first control circuit includes: the grid electrode of the third transistor is connected to the first node, and the first pole of the third transistor is used for connecting the first clock signal end; and one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the second pole of the third transistor.
In one embodiment, the second control circuit includes: the grid electrode and the first electrode of the fourth transistor are used for being connected with the second clock signal end; and the grid electrode of the fifth transistor is connected to the second pole of the fourth transistor, the first pole of the fifth transistor is used for connecting the third high-level signal end, and the second pole of the fifth transistor is connected to the second node.
In one embodiment, the second input circuit includes: a gate of the sixth transistor is used for connecting the second high-level signal end, and a first pole of the sixth transistor is used for connecting the second input end; and the grid electrode of the seventh transistor is connected to the second pole of the sixth transistor, the first pole of the seventh transistor is used for connecting the second control signal end, and the second pole of the seventh transistor is connected to the first node.
In one embodiment, the shift register unit further comprises: and the grid electrode of the eighth transistor is connected to the second node, the first pole of the eighth transistor is used for connecting a low-level signal end, and the second pole of the eighth transistor is connected to the first node.
In one embodiment, the shift register unit further comprises: a gate of the ninth transistor is connected to the second node, a first pole of the ninth transistor is used for connecting the low-level signal end, and a second pole of the ninth transistor is used for connecting the output end; a tenth transistor, a gate of which is used for connecting the output terminal, a first pole of which is used for connecting the low-level signal terminal, and a second pole of which is connected to the second node; a gate of the eleventh transistor is connected to the first node, a first pole of the eleventh transistor is connected to the second node, and a second pole of the eleventh transistor is used for connecting a low-level signal terminal; and the grid electrode and the first electrode of the twelfth transistor are used for being connected with the reset signal end, and the second electrode of the twelfth transistor is connected with the second node.
In one embodiment, the shift register unit further comprises: and one end of the second capacitor is connected to the second node, and the other end of the second capacitor is used for connecting a low-level signal end.
As another aspect of the embodiments of the present application, there is provided a display panel including the gate driving circuit according to any one of the above first aspect of the present application.
As a further aspect of embodiments of the present application, embodiments of the present application provide a display device comprising a gate driving circuit according to any one of the above-mentioned first aspects of the present application, or comprising a gate driving circuit according to any one of the above-mentioned second aspects of the present application.
By adopting the technical scheme, the embodiment of the application can improve the stability of the gate drive circuit, and avoid the occurrence of a plurality of outputs of the shift register unit, thereby improving the stability of the display device.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
FIG. 1 is a circuit diagram of a shift register unit according to the related art;
FIG. 2 is a diagram illustrating a cascade connection of a plurality of shift register units according to the related art;
FIG. 3 is a timing diagram of a shift register unit according to the related art;
FIG. 4 is a timing diagram illustrating an abnormal output of a plurality of shift register units according to the related art;
FIG. 5 is a circuit diagram of a shift register unit of a gate driving circuit according to an embodiment of the present disclosure;
FIG. 6 is a diagram illustrating a cascade relationship of a plurality of shift register units in a gate driving circuit according to an embodiment of the present disclosure;
FIG. 7 is a timing diagram of a forward scan of a gate driving circuit according to an embodiment of the present application;
FIG. 8 is a reverse scan timing diagram of a gate driving circuit according to an embodiment of the present application;
FIG. 9 is a timing diagram of a gate driving circuit according to an embodiment of the present application;
FIG. 10 is a timing comparison diagram of a shift register unit according to an embodiment of the present application and a shift register unit of the related art;
FIG. 11 is a timing diagram comparing a first node of a shift register unit according to an embodiment of the present application with a first node of a shift register unit in the related art;
FIG. 12 is a timing diagram comparing a second node of a shift register unit according to an embodiment of the present application with a second node of a shift register unit in the related art.
Description of reference numerals:
10: a gate drive circuit;
100: a shift register unit; 110: a first input circuit; 111: a first transistor; 112: a second transistor; 120: a second input circuit; 121: a sixth transistor; 122: a seventh transistor; 130: a first control circuit; 131: a third transistor; 132: a first capacitor; 140: a second control circuit; 141: a fourth transistor; 142: a fifth transistor; 151: an eighth transistor; 152: a ninth transistor; 153: a tenth transistor; 154: an eleventh transistor; 155: a twelfth transistor; 156: a second capacitance.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
Fig. 1 is a circuit diagram of a shift register unit in the related art. As shown in fig. 1, in the related art, the shift register unit includes 10 transistors and 2 capacitors. The 10 transistors are respectively a first transistor T1 to a tenth transistor T10. In case that the control node PU _ CN is at a high level and the second clock signal terminal CKB is at a high level, the sixth transistor T6 and the seventh transistor T7 are turned on, thereby making the sixth transistor T6 and the seventh transistor T7 form a direct current path. At this time, it is necessary to set the conduction parameters of the sixth transistor T6 and the seventh transistor T7, for example, set the divided voltages with different aspect ratios, so that the resistance of the sixth transistor T6 is greater than the resistance of the seventh transistor T7, and the level of the second node PD can be pulled down.
Fig. 2 is a diagram illustrating a cascade relationship of a plurality of shift register units in the related art. As shown in fig. 2, the shift register unit of the odd stage controls the shift register unit of the odd stage, and the shift register unit of the even stage controls the shift register unit of the even stage. Specifically, the output of the N row shift register unit is the input of the N +2 th row shift register unit, and the output of the N +2 th row shift register unit is fed back to the gate of the second transistor T2 of the N row shift register unit. When the OUTPUT of the N +2 th row shift register unit is at a high level, the second transistor T2 of the nth row shift register unit is turned on to reset the first node PU and the second node PD, and the OUTPUT terminal OUTPUT of the nth row shift register unit OUTPUTs a low level.
FIG. 3 is a timing diagram of a shift register unit according to the related art; FIG. 4 is a timing diagram illustrating an abnormal output of a plurality of shift register units according to the related art. As shown in fig. 3, in the related art, there is a voltage drop in the voltage of the first node PU of the shift register unit (see part a), and there is a voltage drop in the voltage of the second node PD (see part B). Furthermore, in conjunction with fig. 4, in the case where the output of the N +2 th row shift register unit is abnormal, the first node PU and the second node PD of the nth row shift register unit cannot be reset, resulting in an abnormality in the output (e.g., OUT1-OUT 5) of the multi-row shift register unit.
A gate driver circuit 10 according to an embodiment of the first aspect of the present application is described below with reference to fig. 5-12.
Fig. 5 is a circuit diagram of the shift register unit 100 of the gate driving circuit 10 according to an embodiment of the present application; fig. 6 is a diagram illustrating a cascade relationship of a plurality of shift register units 100 in the gate driving circuit 10 according to an embodiment of the present application. As shown in fig. 5 and 6, the gate driving circuit 10 includes a cascade of a plurality of rows of shift register units 100, wherein a first input terminal of the N +1 th row of shift register units 100 is connected to an output terminal of the N +1 th row of shift register units 100, and a second input terminal of the N +1 th row of shift register units 100 is connected to an output terminal of the N +2 th row of shift register units 100.
For example, in the examples of fig. 5 and 6, the first input terminal OUT of the first row of shift register cells GOA1 N-1 Can be used for connecting the frame start signal terminal STV and the first line shiftThe output terminal OUT1 of the bit register GOA1 can be connected to the first input terminal OUT of the second row of shift registers GOA2 N-1 . The output terminal OUT2 of the second row of shift registers GOA2 can be connected to the second input terminal OUT of the first row of shift registers GOA1 N+1 And a first input terminal OUT of a third row shift register GOA3 N-1 . The output terminal OUT3 of the third row shift register GOA3 can be connected to the second input terminal OUT of the second row shift register GOA2 N+1 And a first input OUT of a fourth row shift register GOA4 N-1 . The cascade connection of the multi-row shift register unit 100 in the embodiment of the present application effectively replaces the scheme in the related art in which the odd-level shift register unit controls the odd-level shift register unit and the even-level shift register unit controls the even-level shift register unit.
The shift register unit 100 includes a first input circuit 110, a second input circuit 120, a first control circuit 130, and a second control circuit 140. The first input circuit 110 is connected to the first high-level signal terminal VGH1, the first control signal terminal CN, the first node PU and the first input terminal OUT of the shift register unit 100 N-1 . The second input circuit 120 is connected to the second high-level signal terminal VGH2, the second control signal terminal CNB, the first node PU and the second input terminal OUT of the shift register unit 100 N+1 . The first control circuit 130 is connected to the first clock signal terminal CK, the first node PU and the output terminal OUT of the shift register N . The second control circuit 140 is connected to the third high-level signal terminal VGH3, the second clock signal terminal CKB, and the second node PD.
The first input circuit 110 is configured to: at the first high level signal terminal VGH1 and a first input terminal OUT N-1 Under the control of the signal of (3), outputting the signal of the first control signal terminal CN to the first node PU; the second input circuit 120 is configured to: a signal at a second high level signal terminal VGH2 and a second input terminal OUT N+1 Under the control of the signal of (3), outputting the signal of the second control signal terminal CNB to the first node PU; the first control circuit 130 is configured to: under the level control of the first node PU, the output signal is output to the output end OUT N (ii) a The second control circuit 140 isIs configured to: the second clock signal is output to the second node PD under the control of the second clock signal terminal CKB.
Illustratively, the first input terminal OUT of the first row shift register GOA1 N-1 May be used to connect the start of frame signal terminal STV. FIG. 7 is a timing diagram of a forward scan of the gate driving circuit 10 according to an embodiment of the present application; fig. 8 is a reverse scan timing diagram of the gate driving circuit 10 according to the embodiment of the present application. Referring to fig. 7 and 8, the shift register supports forward scanning and reverse scanning. For example, when the first control signal terminal CN is at a high level and the second control signal terminal CNB is at a low level, the forward scanning is performed; when the first control signal terminal CN is at a low level and the second control signal terminal CNB is at a high level, the reverse scan is performed.
According to the gate driving circuit 10 of the embodiment of the application, by using the cascaded multi-row shift register unit 100, when the second clock signal terminal CKB is at a high level, the second clock signal can charge the second node PD without voltage drop, so that threshold loss is avoided, the effects of improving driving capability and waveform shaping of the second node PD level signal are achieved, the first node PU and the second node PD are reset by the second clock signal of the current stage, the stability of the gate driving circuit 10 is improved, multiple outputs of the shift register unit 100 are avoided, and the stability of the display device is improved.
In one embodiment, in conjunction with fig. 5, the first input circuit 110 includes a first transistor 111 and a second transistor 112. The gate of the first transistor 111 is used for connecting the first high-level signal terminal VGH1, and the first pole of the first transistor 111 is used for connecting the first input terminal OUT N-1 . The gate of the second transistor 112 is connected to the second pole of the first transistor 111, the first pole of the second transistor 112 is used for connecting the first control signal terminal CN, and the second pole of the second transistor 112 is connected to the first node PU.
Wherein one of the first pole and the second pole is a source, and the other of the first pole and the second pole is a drain. The first transistor 111 and the second transistor 112 may be N-type transistors or P-type transistors, which is not limited in this embodiment.
Illustratively, in conjunction with fig. 5 and 6, the gate driving circuit 10 may include a frame start signal terminal STV, a first clock signal line CKL, a second clock signal line CKBL, a third clock signal line CKR, and a fourth clock signal line CKBR. For example, the same signal CKBL is connected to different ports in different rows, the first row on the odd-numbered side is connected to the CK port, the second row on the odd-numbered side is connected to the CKB port, and so on.
For the odd-numbered rows of shift register cells 100, the first control circuit 130 can be connected to the first clock signal terminal CK of the first clock signal line CKL, and the second control circuit 140 is connected to the second clock signal terminal CKB of the second clock signal line CKBL. For the even-numbered rows of the shift register units 100, the first control circuit 130 may be connected to the first clock signal terminal CK of the third clock signal line CKR, and the second control circuit 140 is connected to the second clock signal terminal CKB of the fourth clock signal line CKBR.
Wherein, the first input end OUT of the first row shift register GOA1 N-1 May be used to connect the start of frame signal terminal STV. The first control signal terminal CN is at a high level 8V, and the second control signal terminal CNB is at a low level-8V. Fig. 9 is a timing diagram of the gate driving circuit 10 according to the embodiment of the present application. Referring to fig. 9, in the first stage T1, the frame start signal terminal STV is at a high level, the first transistor 111 is bootstrapped due to the capacitance effect of the transistor, and the first transistor 111 outputs 16V. The second transistor 112 can be fully turned on, the first node PU is fully charged to 8V level, the second node PD is kept low, and the output terminal OUT is at this time N And outputting a low level.
In one embodiment, as shown in fig. 5 and 6, the first control circuit 130 includes a third transistor 131 and a first capacitor 132. A gate of the third transistor 131 is connected to the first node PU, and a first pole of the third transistor 131 is used for connecting the first clock signal terminal CK. One end (e.g., the left end in fig. 5) of the first capacitor 132 is connected to the first node PU, and the other end (e.g., the right end in fig. 5) of the first capacitor 132 is connected to the second pole of the third transistor 131.
Illustratively, in conjunction with FIG. 9, in the first controlWhen the signal terminal CN is at a high level 8V and the second control signal terminal CNB is at a low level-8V, in the first stage T1, the frame start signal terminal STV is at a high level, the first transistor 111 is bootstrapped, and the first transistor 111 outputs 16V. The second transistor 112 may be fully turned on and the first node PU is charged to a full 8V level. The second node PD is maintained at a low level, the third transistor 131 is turned on, and the output terminal OUT N And outputting a low level. In the second stage T2, the first clock signal terminal CK of the first clock signal line CKL is at a high level, the first capacitor 132 generates a bootstrap effect, the voltage of the first node PU is at 24V, the second node PD maintains at a low level, the third transistor 131 is turned on, and the output terminal OUT is turned on N And outputting a high level. In the third stage T3, the first clock signal terminal CK of the third clock signal line CKR is at a high level, the first node PU and the second node PD are at a low level, and the output terminal OUT N And outputting a low level.
In one embodiment, as shown in fig. 5, the second control circuit 140 includes a fourth transistor 141 and a fifth transistor 142. The gate and the first electrode of the fourth transistor 141 are used for connecting the second clock signal terminal CKB. A gate of the fifth transistor 142 is connected to the second pole of the fourth transistor 141, a first pole of the fifth transistor 142 is used for connecting the third high-level signal terminal VGH3, and a second pole of the fifth transistor 142 is connected to the second node PD.
Illustratively, in the fourth stage T4, the second clock signal terminal CKB of the second clock signal line CKBL is at a high level, and at this time, the fourth transistor 141 and the fifth transistor 142 cooperate to enable the fifth transistor 142 to be bootstrapped, and the second clock signal of the second clock signal terminal CKB charges the second node PD through the fifth transistor 142 without voltage drop.
In this embodiment, on the basis of the cascade relationship of the shift register units 100, by providing the fourth transistor 141 and the fifth transistor 142, the second clock signal of the second clock signal terminal CKB can charge the second node PD through the fifth transistor 142 without voltage drop, so as to avoid threshold loss and effectively improve the stability of the gate driving circuit 10.
In one embodiment, as shown in FIG. 5, a second input circuit120 include a sixth transistor 121 and a seventh transistor 122. A gate of the sixth transistor 121 is connected to the second high-level signal terminal VGH2, and a first pole of the sixth transistor 121 is connected to the second input terminal OUT N+1 . A gate of the seventh transistor 122 is connected to the second pole of the sixth transistor 121, a first pole of the seventh transistor 122 is used for connecting the second control signal terminal CNB, and a second pole of the seventh transistor 122 is connected to the first node PU.
Illustratively, in conjunction with fig. 6, in the case where the first control signal terminal CN is at a high level of 8V and the second control signal terminal CNB is at a low level of-8V, the first transistor 111 and the sixth transistor 121 are normally on, and output terminal OUT of the next row of shift register units 100 N The output signal is fed back to the second input terminal OUT of the present line shift register unit 100 N+1 。
In one embodiment, referring to fig. 5, the shift register unit 100 may further include an eighth transistor 151, a ninth transistor 152, a tenth transistor 153, an eleventh transistor 154, a twelfth transistor 155, and a second capacitor 156.
Specifically, a gate of the eighth transistor 151 is connected to the second node PD, a first pole of the eighth transistor 151 is connected to the low-level signal terminal VGL, and a second pole of the eighth transistor 151 is connected to the first node PU. A gate of the ninth transistor 152 is connected to the second node PD, a first pole of the ninth transistor 152 is connected to the low-level signal terminal VGL, and a second pole of the ninth transistor 152 is connected to the output terminal OUT N . The gate of the tenth transistor 153 is connected to the output terminal OUT N A first pole of the tenth transistor 153 is connected to the low level signal terminal VGL, and a second pole of the tenth transistor 153 is connected to the second node PD. A gate of the eleventh transistor 154 is connected to the first node PU, a first pole of the eleventh transistor 154 is connected to the second node PD, and a second pole of the eleventh transistor 154 is connected to the low-level signal terminal VGL. A gate and a first pole of the twelfth transistor 155 are connected to the RESET signal terminal RESET, and a second pole of the twelfth transistor 155 is connected to the second node PD. One terminal (e.g., the upper terminal in fig. 5) of the second capacitor 156 is connected to the second node PD, and the other terminal (e.g.,the lower end in fig. 5) is used to connect the low level signal terminal VGL.
In this embodiment, the fourth transistor 141, the fifth transistor 142 and the eleventh transistor 154 can be prevented from being turned on simultaneously, so that a dc path (i.e., a short circuit) from the second clock signal terminal CKB to the low level signal terminal VGL can be avoided, and a problem that potentials of the first node PU and the second node PD compete with each other due to the dc path can be avoided, so that power consumption of the gate driving circuit 10 can be reduced, and stability of the gate driving circuit 10 can be improved.
FIG. 10 is a timing diagram comparing the shift register unit 100 according to the embodiment of the present application and a related art shift register unit; FIG. 11 is a timing diagram comparing the first node PU of the shift register unit 100 according to the embodiment of the present application with the first node PU of the shift register unit in the related art; fig. 12 is a timing comparison diagram of the second node PD of the shift register unit 100 according to the embodiment of the present application and the second node of the shift register unit in the related art.
According to the gate driving circuit 10 of the embodiment of the present application, as shown in fig. 9 to 12, as can be seen from fig. 11, by using the circuit structure and the cascade relation of the shift register unit 100 of the embodiment of the present application, the reset voltage of the second node PD has no voltage drop, the voltage and the response speed of the second node PD are increased, and the circuit output is more stable when the row is closed; as can be seen from fig. 12, by using the circuit structure and the cascade relation of the shift register unit 100 according to the embodiment of the present application, the bootstrap voltage of the first node PU can be higher, the waveform shaping of the first node PU is realized, the voltage and the response speed of the first node PU are improved, and the circuit output is more stable when the row is opened.
A display panel according to a second aspect of the present application comprises a gate driver circuit 10 according to any of the above-described first aspect of the present application.
A display device according to an example of the third aspect of the present application comprises the gate driver circuit 10 according to any of the above-described first aspect of the present application, or comprises the display panel according to any of the above-described second aspect of the present application.
Illustratively, the display panel may include an array of a plurality of sub-pixel units. The display device may further include a data driving circuit. The data driving circuit is used for providing data signals to the pixel array. The gate drive circuit 10 is used to provide drive signals to the pixel array, which may drive, for example, scan transistors and sense transistors in the sub-pixel cells. The data driving circuit is electrically connected to the sub-pixel unit through the data line, and the gate driving circuit 10 is electrically connected to the sub-pixel unit through the gate line.
Exemplarily, the display device may be a liquid crystal display device or an organic light emitting diode display device. For example, the display device may be any product or component with a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
Other configurations of the gate driving circuit 10, the display panel and the display device of the above embodiments can be adopted in various technical solutions known to those skilled in the art now and in the future, and will not be described in detail here.
In the description of the present specification, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral parts; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the recitation of a first feature "on" or "under" a second feature may include the recitation of the first and second features being in direct contact, and may also include the recitation of the first and second features not being in direct contact, but being in contact with another feature between them. Also, the first feature "on," "above" and "over" the second feature may include the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The above disclosure provides many different embodiments or examples for implementing different structures of the application. The components and arrangements of specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the present application, and these should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A gate driving circuit comprising a plurality of cascaded rows of shift register cells, wherein a first input of an N +1 th row of shift register cells is connected to an output of an nth row of shift register cells, a second input of the N +1 th row of shift register cells is connected to an output of an N +2 th row of shift register cells, the shift register cells comprising:
a first input circuit connected to a first high level signal terminal, a first control signal terminal, a first node, and a first input terminal of the shift register unit, the first input circuit configured to: under the control of the signal of the first high-level signal end and the signal of the first input end, outputting the signal of the first control signal end to the first node;
a second input circuit connected to a second high-level signal terminal, a second control signal terminal, the first node, and a second input terminal of the shift register unit, the second input circuit configured to: under the control of the signal of the second high-level signal end and the signal of the second input end, outputting the signal of the second control signal end to the first node;
a first control circuit connected to a first clock signal terminal, the first node, and an output terminal of the shift register unit, the first control circuit configured to: outputting an output signal from the output terminal under the level control of the first node;
a second control circuit connected to a third high level signal terminal, a second clock signal terminal, and a second node, the second control circuit configured to: and outputting the second clock signal to the second node under the control of a second clock signal at the second clock signal end.
2. A gate drive circuit as claimed in claim 1, wherein the first input circuit comprises:
a first transistor, a gate of which is used for connecting the first high-level signal terminal, and a first pole of which is used for connecting the first input terminal;
and a gate of the second transistor is connected to a second pole of the first transistor, a first pole of the second transistor is used for connecting the first control signal terminal, and a second pole of the second transistor is connected to the first node.
3. A gate drive circuit as claimed in claim 1, wherein the first control circuit comprises:
a third transistor, a gate of which is connected to the first node, and a first pole of which is used for connecting the first clock signal terminal;
one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the second pole of the third transistor.
4. A gate drive circuit as claimed in claim 1, wherein the second control circuit comprises:
a fourth transistor, a gate and a first pole of which are used for connecting the second clock signal terminal;
a gate of the fifth transistor is connected to the second pole of the fourth transistor, a first pole of the fifth transistor is used for connecting the third high-level signal terminal, and a second pole of the fifth transistor is connected to the second node.
5. A gate drive circuit as claimed in claim 1, wherein the second input circuit comprises:
a sixth transistor, a gate of which is used for connecting the second high-level signal terminal, and a first pole of which is used for connecting the second input terminal;
a seventh transistor, a gate of which is connected to the second pole of the sixth transistor, a first pole of which is used to connect the second control signal terminal, and a second pole of which is connected to the first node.
6. The gate driving circuit according to claim 1, wherein the shift register unit further comprises:
a gate of the eighth transistor is connected to the second node, a first pole of the eighth transistor is used for connecting a low-level signal terminal, and a second pole of the eighth transistor is connected to the first node.
7. The gate driver circuit of claim 6, wherein the shift register cell further comprises:
a ninth transistor, a gate of which is connected to the second node, a first pole of which is used for connecting the low-level signal terminal, and a second pole of which is used for connecting the output terminal;
a tenth transistor, a gate of which is connected to the output terminal, a first pole of which is connected to the low-level signal terminal, and a second pole of which is connected to the second node;
an eleventh transistor, a gate of which is connected to the first node, a first pole of which is connected to the second node, and a second pole of which is connected to the low-level signal terminal;
and a twelfth transistor, wherein a gate and a first pole of the twelfth transistor are used for connecting a reset signal terminal, and a second pole of the twelfth transistor is connected to the second node.
8. The gate driving circuit according to claim 1, wherein the shift register unit further comprises:
and one end of the second capacitor is connected to the second node, and the other end of the second capacitor is used for connecting a low-level signal end.
9. A display panel comprising the gate driver circuit according to any one of claims 1 to 8.
10. A display device comprising the gate driver circuit according to any one of claims 1 to 8; or comprising a display panel according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310116073.6A CN115985266A (en) | 2023-02-08 | 2023-02-08 | Gate drive circuit, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310116073.6A CN115985266A (en) | 2023-02-08 | 2023-02-08 | Gate drive circuit, display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115985266A true CN115985266A (en) | 2023-04-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310116073.6A Pending CN115985266A (en) | 2023-02-08 | 2023-02-08 | Gate drive circuit, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115985266A (en) |
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2023
- 2023-02-08 CN CN202310116073.6A patent/CN115985266A/en active Pending
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