CN115981880B - Method, device, system, storage medium and chip for avoiding deadlock of host access slave - Google Patents
Method, device, system, storage medium and chip for avoiding deadlock of host access slave Download PDFInfo
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Abstract
The invention discloses a method, a device, a system and a chip for avoiding deadlock of a host accessing a slave, wherein the method comprises the following steps: in the communication process of the host module and the slave module, a take-over module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and transparent transmission processing is carried out; after receiving the take-over command, the take-over module is switched into a take-over mode, takes over the operation of the connected slave module, and performs subsequent communication with the host module; after receiving the exit takeover command, the takeover module completes the current command operation with the host module, exits the current takeover mode and enters a monitoring transparent transmission mode. By implementing the invention, the stability, the robustness and the software friendliness of the system can be improved.
Description
Technical Field
The present invention relates to the technical field of data communication in a chip, and in particular, to a method, an apparatus, a system, a storage medium, and a chip for avoiding deadlock of a host accessing a slave.
Background
In large-scale digital chip designs, a host module (Master) is typically provided for access, which may be implemented, for example, with a CPU; meanwhile, there may be multiple memory space types, such as a system configuration space, an on-chip cache space, an off-chip cache space, and the like, where these memory spaces are managed by corresponding memory logic circuits as Slave modules (Slave) for access. There may be situations where one host module accesses multiple slave modules, typically through a standard bus protocol (e.g., AMBA AXI bus) and a bus interconnect module (interconnect) that is responsible for command arbitration and access routing for the different functional modules.
FIG. 1 is a schematic diagram of an application architecture with a master module and a slave module according to the prior art; under this bus structure, the master module is connected with at least one slave module through a bus interconnect module. Generally, after the host module sends an access command, the bus interconnection module routes the access to the corresponding slave module according to the address mapping; the slave module executes after receiving the command and returns a response (such as a write execution result, read data and the like), and the bus interconnection module is responsible for arbitrating the responses of the plurality of slave modules, and selects one of the responses to be sent to the host module according to the arbitration result. In addition, the clock reset module (Clock and Reset Generator, CRG) is generally responsible for generating the clock and reset signals of all modules, and the clock and reset signals of different modules can be independently controlled by the CPU through issuing software commands for low power consumption and anomaly management.
However, after the host module sends a command to a certain slave module, the command is calculated to be executed only after the host module receives a corresponding response; if the slave module is not able to return a response, the master module is always in a waiting state, and deadlock is caused. This deadlock situation may occur, frequently, in the following scenario:
scene 1: under the low power consumption scene, the clock of the slave module is closed and reset to be effective through the CRG module, and the slave is in a shutdown mode and cannot execute the command.
Scene 2: an exception occurs inside the slave module, so that the command cannot be executed correctly and a response is returned.
In the prior art, the above-mentioned deadlock problem is generally solved by the following method:
for scenario 1, in a low power scenario, the master module is restricted from accessing the slave module that is turned off.
For scenario 2, resetting all of the host module, bus interconnect module, and slave module is equivalent to restarting the entire system.
However, the existing solutions have some disadvantages when used in actual projects:
for the solution of scenario 1, when applied to the platform debugging stage, if the software test is not complete, or in the system normal operation stage, because the software is executed abnormally, the shut-down slave module may be accessed by mistake, so that a deadlock is caused, and in this case, it usually takes a lot of time to debug to solve the deadlock problem.
For the solution of scenario 2, if an abnormality occurs in a single slave module, all the master module, the bus interconnection module and the slave module are reset, so that other functions still in normal operation are affected, a great cost is caused, and meanwhile, the system robustness is poor.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method, a device, a system, a storage medium and a chip for avoiding deadlock of a host access slave, which can avoid deadlock of a host module under the condition that normal operation of other modules is not affected, and improve the stability of the system.
In order to solve the above technical problems, as one aspect of the present invention, a method for avoiding deadlock of a master accessing a slave is provided, which at least includes the following steps:
in the communication process of the host module and the slave module, a take-over module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and transparent transmission processing is carried out;
after receiving the take-over command, the take-over module is switched into a take-over mode, takes over the operation of the connected slave module, and performs subsequent communication with the host module;
after receiving the exit takeover command, the takeover module completes the current command operation with the host module, exits the current takeover mode and enters a monitoring transparent transmission mode.
The step of monitoring information between the host module and the slave module in real time and performing transparent transmission processing further comprises the steps of:
the take-over module transmits command information forwarded by the bus interconnection module from the host module to the slave module; transmitting the response message from the host module to the host module through the bus interconnection module;
the take-over module monitors and counts the command and the response message, and records the command type and the access data length when the command is received as a read command of the host module; recording the sending number of the writing data when the writing command is received as the writing command of the host module; and when the received read data is the read command returned by the slave module, recording the received read data.
After receiving the take-over command from the clock reset module, the take-over module switches to a take-over mode, and the step of taking over the operation of the slave module connected with the take-over module further comprises:
all operations of the host module on the slave module are shielded, the takeover module replaces the slave module and the host module to complete all issued but not yet ended command messages, and a new command message issued by the host module is responded.
Correspondingly, the invention also provides a device for avoiding deadlock of the access of the host to the slave, which is arranged between the host module and the slave module and at least comprises:
the monitoring transparent transmission processing unit is used for being in a monitoring transparent transmission mode in the communication process of the host module and the slave module, monitoring command/response information between the host module and the slave module in real time and performing transparent transmission processing;
the take-over processing unit is used for switching to enter a take-over mode after receiving a take-over command, carrying out take-over processing on the operation of the connected slave module and carrying out subsequent communication with the host module;
and the takeover exit unit is used for completing the current command operation with the host module after receiving the takeover exit command, exiting the current takeover mode and entering the monitoring transparent transmission mode.
Wherein, the transparent transmission processing unit of monitoring further includes:
the transparent transmission processing unit is used for transparent transmitting the command message from the host module forwarded by the bus interconnection module to the slave module; transmitting the response message from the host module to the host module through the bus interconnection module;
the monitoring processing unit is used for monitoring and counting the command and the response message, and recording the command type and the access data length when the command is received as a read command of the host module; recording the sending number of the writing data when the writing command is received as the writing command of the host module; and when the received read data is the read command returned by the slave module, recording the received read data.
Wherein the takeover processing unit further comprises:
and the shielding processing unit is used for shielding all operations of the host module on the slave module, and the takeover module replaces the slave module and the host module to complete all the sent command messages which are not ended yet, and responds to the new command messages sent by the host module subsequently.
Correspondingly, the invention also provides a method for avoiding deadlock of the access of the host to the slave, which at least comprises the following steps:
in the communication process of the host module and the slave module, a take-over module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and transparent transmission processing is carried out;
when a slave module is detected to enter a low-power-consumption working mode or work abnormality occurs, the clock reset module is controlled to send an instruction for turning off the slave module, and the clock reset module sends a take-over command to a take-over module connected with the slave module;
after receiving the takeover command, the takeover module is switched to enter a takeover mode, the operation of the slave module connected with the takeover module is taken over, the slave module and the host module are subjected to subsequent communication, and a takeover response is returned to the clock reset module;
and the clock reset module controls the slave module to be turned off after receiving the takeover response.
The step of monitoring information between the host module and the slave module in real time and performing transparent transmission processing further comprises the steps of:
the take-over module transmits command information forwarded by the bus interconnection module from the host module to the slave module; transmitting the response message from the host module to the host module through the bus interconnection module;
the take-over module monitors and counts the command and the response message, and records the command type and the access data length when the command is received as a read command of the host module; recording the sending number of the writing data when the writing command is received as the writing command of the host module; and when the received read data is the read command returned by the slave module, recording the received read data.
After receiving the take-over command from the clock reset module, the take-over module switches to a take-over mode, and the step of taking over the operation of the slave module connected with the take-over module further comprises the following steps:
all operations of the host module on the slave module are shielded, the takeover module replaces the slave module and the host module to complete all issued but not yet ended command messages, and a new command message issued by the host module is responded.
Wherein the method further comprises:
when the slave module which is turned off needs to be turned on, controlling to send a starting instruction to the clock reset module;
when the clock reset module receives a starting instruction, a take-over exit command is sent to the take-over module; and controlling to open the slave module;
after receiving the take-over exit command, the take-over module completes the current command operation with the host module, exits the current take-over mode, enters a monitoring transparent transmission mode, and sends a take-over exit response to the clock reset module.
The invention also provides a system for avoiding deadlock of the host accessing the slave, which comprises a host module and at least one slave module connected through a bus interconnection module, wherein a take-over module and a clock reset module connected with each take-over module and the slave module are arranged between each slave module and the interconnection module; wherein:
the clock reset module is used for sending a take-over command to the take-over module connected with the slave module after receiving an instruction for turning off the slave module, and controlling the slave module to be turned off after receiving a take-over response of the take-over module; when receiving an instruction for starting the slave module, controlling to restart the slave module, and sending an exit takeover command to a takeover module connected to the slave module;
the take-over module is a device for avoiding deadlock of the host accessing the slave as described above.
The invention also provides a computer readable storage medium storing executable instructions that when executed implement a method as described above.
The invention also provides a chip, and the system for avoiding deadlock of the host accessing the slave is deployed in the chip.
The embodiment of the invention has the following beneficial effects:
the invention provides a method, a device, a system, a storage medium and a chip for avoiding deadlock of a host accessing a slave. Connecting a bus operation take-over module between each slave module and the bus interconnection module, and interacting with the take-over module through the clock reset module to control the working mode of the take-over module; the receiving module can monitor the execution and response conditions of commands between the host module and the slave module in real time, and after a certain slave module fails or is temporarily closed, the receiving module can be controlled to enter a receiving mode in time through the clock reset module, and the receiving module can automatically replace the slave module to complete receiving and response of all commands. Thus, the situation that the host module is deadlocked can be avoided; the stability of the system is improved;
after a certain slave module is turned off (or abnormal), the invention can avoid the situation that the master module is deadlocked without limiting the access of software or resetting all modules in the system, and can greatly improve the robustness and software friendliness of the system.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are required in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that it is within the scope of the invention to one skilled in the art to obtain other drawings from these drawings without inventive faculty.
FIG. 1 is a schematic diagram of an application architecture with a master module and a slave module according to the prior art;
FIG. 2 is a schematic diagram of a main flow of an embodiment of a method for avoiding deadlock of a master accessing a slave according to the present invention;
FIG. 3 is a schematic diagram of an application architecture according to the method of the present invention;
FIG. 4 is a more detailed flow chart of the process of taking over by the take-over module in the method of the present invention;
FIG. 5 is a more detailed flow chart of the method according to the present invention, wherein the takeover module exits the takeover process;
FIG. 6 is a schematic diagram illustrating an embodiment of an apparatus for avoiding deadlock of a master accessing a slave according to the present invention;
fig. 7 is a schematic structural diagram of the listening transparent processing unit in fig. 6.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent.
FIG. 2 is a schematic diagram illustrating the main flow of an embodiment of a method for avoiding deadlock of a master accessing a slave according to the present invention; as shown in fig. 3 to 5, in this embodiment, the method is applied to an application architecture as shown in fig. 3, where the application architecture includes a host module and at least one slave module connected by a bus interconnection module, a takeover module is disposed between each slave module and the interconnection module, and a clock reset module connected to each takeover module and the slave module, where the clock reset module receives a software command of the CPU module.
More specifically, the method for avoiding deadlock of the master access to the slave comprises at least the following steps:
step S10, in the process of communication between a host module and a slave module, a take-over module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and transparent transmission processing is carried out;
in a specific example, the step S10 further includes: the take-over module transmits command information forwarded by the bus interconnection module from the host module to the slave module; transmitting the response message from the host module to the host module through the bus interconnection module;
the take-over module monitors and counts the command and the response message, and records the command type and the access data length when the command is received as a read command of the host module; recording the sending number of the writing data when the writing command is received as the writing command of the host module; and when the received read data is the read command returned by the slave module, recording the received read data.
Step S11, after receiving the take-over command, the take-over module is switched into a take-over mode, takes over the operation of the connected slave module, and performs subsequent communication with the host module; it can be understood that, in a specific example, when a certain slave module needs to enter a low-power consumption working mode or the system detects that the slave module is abnormal in working, the clock reset module sends a take-over command to a take-over module connected with the slave module;
in a specific example, the step S11 further includes:
the take-over module shields all operations of the host module on the slave module, and the take-over module replaces the slave module to complete all sent command messages which are not ended yet with the host module, and responds to new command messages sent by the host module subsequently.
In a specific application, for the operation that the host module has sent to the slave module before, but the slave module is abnormal and has not completed responding, the operation is responsible for completion by the take-over module, so that deadlock situations in the prior art are avoided. Specifically, for the write command sent by the host module, according to the monitored command execution condition, if the write data is already sent partially or not sent yet, the takeover module is responsible for sending the write data corresponding to all the incomplete write commands; if the slave module returns a write response, the takeover module is responsible for accepting the response; if the slave module returns read data, the takeover module is responsible for receiving these write data.
The master module also continues to access the slave module while the slave unit is in the off mode, in which case the takeover module is responsible for receiving all commands and completing all responsive operations.
Step S12, after receiving the exit takeover command, the takeover module completes the current command operation with the host module (namely, all executing commands return responses), exits the current takeover mode and enters a monitoring transparent transmission mode.
Referring to fig. 4 and 5, in a more detailed example, the method for avoiding deadlock of a master accessing a slave includes at least the following steps:
step S20, in the process of communication between the host module and the slave module, a take-over module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and transparent transmission processing is carried out;
specifically, in this step, the takeover module transparently transmits the command message from the host module forwarded by the bus interconnection module to the slave module; transmitting the response message from the host module to the host module through the bus interconnection module;
the take-over module monitors and counts the command and the response message, and records the command type and the access data length when the command is received as a read command of the host module; recording the sending number of the writing data when the writing command is received as the writing command of the host module; and when the received read data is the read command returned by the slave module, recording the received read data.
Step S21, when a slave module is detected to enter a low-power-consumption working mode or work abnormality occurs, the clock reset module is controlled to send an instruction for turning off the slave module, and the clock reset module sends a take-over command to a take-over module connected with the slave module;
step S22, after receiving the takeover command, the takeover module is switched to enter a takeover mode, the operation of the connected slave module is taken over, the slave module and the host module are subjected to subsequent communication, and a takeover response is returned to the clock reset module;
more specifically, in this step, all operations of the slave module by the master module are masked, all issued but not yet completed command messages are completed by the takeover module in place of the slave module and the master module, and a new command message is subsequently issued in response to the master module.
And S23, after receiving the takeover response, the clock reset module controls to turn off the slave module, and the clock reset module turns off the slave module by turning off the clock of the slave module and resetting to be effective, so that the slave module enters a turn-off mode.
Step S30, when the slave module which is turned off needs to be turned on, controlling to send a starting instruction to the clock reset module;
step S31, when the clock reset module receives a starting instruction, a take-over exit command is sent to the take-over module; and controlling to open the slave module; specifically, the clock reset module enables the slave module to enter a normal working mode by opening and resetting the clock of the corresponding slave module;
step S32, after receiving the take-over exit command, the take-over module completes the current command operation with the host module, exits the current take-over mode, enters a monitoring transparent transmission mode, and sends a take-over exit response to the clock reset module.
Referring to fig. 6, a schematic structural diagram of an embodiment of an apparatus for avoiding deadlock of a master access slave according to the present invention is shown. In this embodiment, the device 1 for avoiding deadlock of a master accessing a slave is disposed in a takeover module shown in fig. 3, where the takeover module is disposed between a master module and a slave module, and the device 1 at least includes:
the monitoring transparent transmission processing unit 10 is used for being in a monitoring transparent transmission mode in the communication process of the host module and the slave module, monitoring command/response information between the host module and the slave module in real time and performing transparent transmission processing;
the takeover processing unit 11 is configured to switch to a takeover mode after receiving a takeover command, perform takeover processing on an operation of a slave module connected to the takeover processing unit, and perform subsequent communication with the host module;
more specifically, the takeover processing unit 11 further includes:
and the shielding processing unit is used for shielding all operations of the host module on the slave module, and the take-over module replaces the slave module to complete all the sent command messages which are not ended yet with the slave module, and responds to the new command messages sent by the host module subsequently.
And the takeover exit unit 12 is configured to complete the current command operation with the host module after receiving the takeover exit command, exit the current takeover mode, and enter the transparent monitoring mode.
More specifically, the listening transparent processing unit 10 further includes:
the transparent transmission processing unit 100 is configured to transparent transmit the command message forwarded by the bus interconnection module from the host module to the slave module; transmitting the response message from the host module to the host module through the bus interconnection module;
the monitoring processing unit 101 is configured to monitor and count the command and the response message, and record a command type and an access data length when a read command of the host module is received; recording the sending number of the writing data when the writing command is received as the writing command of the host module; and when the received read data is the read command returned by the slave module, recording the received read data.
For more details, reference is made to and the description of fig. 2 to 5 is incorporated in the foregoing, and no further description is given here.
In another aspect of the present invention, a system for avoiding deadlock of a host accessing a slave is provided, and the overall architecture of the system may be shown in fig. 3, where the system at least includes a host module, and at least one slave module connected by a bus interconnection module, a takeover module is disposed between each slave module and the interconnection module, and a clock reset module connected to each takeover module and each slave module; wherein:
the clock reset module is used for sending a take-over command to the take-over module connected with the slave module after receiving an instruction for turning off the slave module, and controlling the slave module to be turned off after receiving a take-over response of the take-over module; when receiving an instruction for starting the slave module, controlling to restart the slave module, and sending an exit takeover command to a takeover module connected to the slave module;
the take-over module is provided with the device for avoiding deadlock of the host access slave machine, which is described in the foregoing fig. 6 and 7.
For more details, reference is made to the foregoing descriptions of fig. 6 and 7, and no further description is given here.
The present invention also provides a computer readable storage medium storing executable instructions that when executed implement the method as described in the foregoing figures 2-5. For more details, reference is made to the foregoing descriptions of fig. 2 to 5, and no further description is given here.
The invention also provides a chip, wherein the system for avoiding deadlock of the host machine accessing the slave machine is deployed in the chip. For more details, reference is made to the foregoing descriptions of fig. 2 to 7, and no further description is given here.
The embodiment of the invention has the following beneficial effects:
the invention provides a method, a device, a system, a storage medium and a chip for avoiding deadlock of a host accessing a slave. Connecting a bus operation take-over module between each slave module and the bus interconnection module, and interacting with the take-over module through the clock reset module to control the working mode of the take-over module; the receiving module can monitor the execution and response conditions of commands between the host module and the slave module in real time, and after a certain slave module fails or is temporarily closed, the receiving module can be controlled to enter a receiving mode in time through the clock reset module, and the receiving module can automatically replace the slave module to complete receiving and response of all commands. Thus, the situation that the host module is deadlocked can be avoided; the stability of the system is improved;
after a certain slave module is turned off (or abnormal), the invention can avoid the situation that the master module is deadlocked without limiting the access of software or resetting all modules in the system, and can greatly improve the robustness and software friendliness of the system.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above disclosure is only a preferred embodiment of the present invention, and it is needless to say that the scope of the invention is not limited thereto, and therefore, the equivalent changes according to the claims of the present invention still fall within the scope of the present invention.
Claims (13)
1. A method for avoiding deadlock of a host accessing a slave, comprising at least the steps of:
in the communication process of the host module and the slave module, a take-over module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and transparent transmission processing is carried out;
after receiving the take-over command from the clock reset module, the take-over module is switched into a take-over mode, takes over the operation of the slave module connected with the take-over module, and performs subsequent communication with the host module; and returning a take-over response to the clock reset module, so that the clock reset module controls the slave module to be turned off after receiving the take-over response;
after receiving an exit take-over command sent by the clock reset module after the slave module is opened, the take-over module completes the current command operation with the host module, exits from the current take-over mode and enters into a monitoring transparent transmission mode.
2. The method of claim 1, wherein the step of monitoring information between the master module and the slave module in real time and performing a pass-through process further comprises:
the take-over module transmits command information forwarded by the bus interconnection module from the host module to the slave module; and transmitting the response message from the host module to the host module through the bus interconnection module;
the take-over module monitors and counts the command message and the response message, and records the command type and the access data length when a read command of the host module is received; recording the sending number of the writing data when the writing command is received as the writing command of the host module; and when the received read data is the read command returned by the slave module, recording the received read data.
3. The method of claim 2, wherein the step of switching the takeover module into the takeover mode to take over the operation of the slave module to which it is connected after receiving the takeover command further comprises:
and shielding all response operations of the host module to the slave module, replacing the slave module and the host module by a take-over module to complete all issued but not-ended command messages, and responding to new command messages issued by the host module.
4. An apparatus for avoiding deadlock of a host accessing a slave, the apparatus being disposed between a host module and a slave module, the apparatus comprising at least:
the monitoring transparent transmission processing unit is used for being in a monitoring transparent transmission mode in the communication process of the host module and the slave module, monitoring command/response information between the host module and the slave module in real time and performing transparent transmission processing;
the take-over processing unit is used for switching into a take-over mode after receiving a take-over command from the clock reset module, carrying out take-over processing on the operation of the connected slave module and carrying out subsequent communication with the host module; and returning a take-over response to the clock reset module, so that the clock reset module controls the slave module to be turned off after receiving the take-over response;
the take-over and take-off unit is used for completing the current command operation with the host module after receiving the take-over and take-off command sent by the clock reset module after the slave module is opened, and exiting the current take-over mode and entering the monitoring transparent transmission mode.
5. The apparatus of claim 4, wherein the listening transparent processing unit further comprises:
the transparent transmission processing unit is used for transparent transmitting the command message from the host module forwarded by the bus interconnection module to the slave module; transmitting the response message from the host module to the host module through the bus interconnection module;
the monitoring processing unit is used for monitoring and counting the command and the response message, and recording the command type and the access data length when the command is received as a read command of the host module; recording the sending number of the writing data when the writing command is received as the writing command of the host module; and when the received read data is the read command returned by the slave module, recording the received read data.
6. The apparatus of claim 5, wherein the take over processing unit further comprises:
and the shielding processing unit is used for shielding all operations of the host module on the slave module, and the takeover module replaces the slave module and the host module to complete all the sent command messages which are not ended yet, and responds to the new command messages sent by the host module subsequently.
7. A method for avoiding deadlock of a host accessing a slave, comprising at least the steps of:
in the communication process of the host module and the slave module, a take-over module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and transparent transmission processing is carried out;
when a slave module is detected to enter a low-power-consumption working mode or work abnormality occurs, the clock reset module is controlled to send an instruction for turning off the slave module, and the clock reset module sends a take-over command to a take-over module connected with the slave module;
after receiving the takeover command, the takeover module is switched to enter a takeover mode, the operation of the slave module connected with the takeover module is taken over, the slave module and the host module are subjected to subsequent communication, and a takeover response is returned to the clock reset module;
and the clock reset module controls the slave module to be turned off after receiving the takeover response.
8. The method of claim 7, wherein the step of monitoring information between the master module and the slave module in real time and performing a pass-through process further comprises:
the take-over module transmits command information forwarded by the bus interconnection module from the host module to the slave module; transmitting the response message from the host module to the host module through the bus interconnection module;
the take-over module monitors and counts the command and the response message, and records the command type and the access data length when the command is received as a read command of the host module; recording the sending number of the writing data when the writing command is received as the writing command of the host module; and when the received read data is the read command returned by the slave module, recording the received read data.
9. The method of claim 8, wherein the step of switching into the takeover mode to take over the operation of the slave module to which it is connected after the takeover module receives the takeover command from the clock reset module further comprises:
all operations of the host module on the slave module are shielded, the takeover module replaces the slave module and the host module to complete all issued but not yet ended command messages, and a new command message issued by the host module is responded.
10. The method of claim 9, wherein the method further comprises:
when the slave module which is turned off needs to be turned on, controlling to send a starting instruction to the clock reset module;
when the clock reset module receives a starting instruction, a take-over exit command is sent to the take-over module; and controlling to open the slave module;
after receiving the take-over exit command, the take-over module completes the current command operation with the host module, exits the current take-over mode, enters a monitoring transparent transmission mode, and sends a take-over exit response to the clock reset module.
11. The system for avoiding deadlock of the host accessing the slave is characterized by comprising a host module and at least one slave module connected through a bus interconnection module, wherein a take-over module and a clock reset module connected with each take-over module and the slave module are arranged between each slave module and the interconnection module; wherein:
the clock reset module is used for sending a take-over command to the take-over module connected with the slave module after receiving an instruction for turning off the slave module, and controlling the slave module to be turned off after receiving a take-over response of the take-over module; when receiving an instruction for starting the slave module, controlling to restart the slave module, and sending an exit takeover command to a takeover module connected to the slave module;
the take-over module is provided with a device for avoiding deadlock of a host accessing a slave according to any one of claims 4 to 6.
12. A computer readable storage medium storing executable instructions which, when executed, implement the method of any one of claims 1 to 3.
13. A chip having disposed therein the system for avoiding deadlock of a master access slave according to claim 11.
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