CN115981551A

CN115981551A - High-speed self-balancing storage control method and storage medium

Info

Publication number: CN115981551A
Application number: CN202211575760.6A
Authority: CN
Inventors: 刘雪枫; 李亮; 田绪超; 孙清心
Original assignee: Jiangsu Advanced Construction Machinery Innovation Center Ltd
Current assignee: Jiangsu Advanced Construction Machinery Innovation Center Ltd
Priority date: 2022-12-09
Filing date: 2022-12-09
Publication date: 2023-04-18

Abstract

The invention discloses a high-speed self-balancing storage control method and a storage medium. The invention adopts a cyclic writing mode for the physical storage space, and has the characteristic of writing balance naturally, thereby avoiding bad blocks caused by repeated erasing and writing of a single storage space. The invention establishes Hash mapping of the logical address and the physical address, and the read-write time complexity is O (1). The invention establishes the logical page cache at the operation end, further abstracts the logical writing, and the writing operation can adopt any length, thereby meeting the characteristic of short-write long-memory. The reading of the invention can adopt two modes, one mode is that the logic address is used as a base address to read data with any length; the other is to read specific byte data by using the data content as a key word and adopting an algorithm searching mode.

Description

High-speed self-balancing storage control method and storage medium

Technical Field

The invention relates to a high-speed self-balancing storage control method and a storage medium, and belongs to the technical field of information.

Background

With the development of flash memory technology, the storage space of flash memory media is larger and the cost is lower. Nandflash is a typical flash memory, and is characterized in that a block (block) -page (page) -byte (byte) is used as a partition structure, and a page (page) is generally used as a read-write unit, and a block (block) is used as an erase unit. The characteristic of the block storage structure has asymmetric read-write and erase operations when in use, which increases the difficulty of storage system management and sets physical limit conditions for using the medium.

For standardized management, a storage medium is generally formatted by a file system, and read-write management is performed by using an abstract interface of the file system. In a small embedded device, the main control MCU has a simple structure and a single logic function, and lacks the operating environment of a large file system, so that the block storage device is difficult to manage in the embedded device.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a high-speed self-balancing storage control method and a storage medium.

In order to achieve the above object, the present invention provides a high-speed self-balancing storage control method, which comprises:

step 1, initializing a physical interface of a block storage device;

step 2, reading hardware information by using a physical interface of the storage equipment;

step 3, calculating the physical storage structure of the hardware according to the hardware information, and initializing the value of a physical control keyword;

step 4, initializing cycle keywords to a preset initial value;

step 5, calculating the operable logic unit quantity logic _ unit _ num;

step 6, assigning the operable logic unit quantity logic _ unit _ num to a key word of logic _ unit _ num;

step 7, reading the last stored next _ write _ address from the logic address storage area, if reading the next _ write _ address fails, setting the next _ write _ address as a default initial address, and entering step 8, if reading the next _ write _ address succeeds, directly entering step 8;

step 8, applying for a cache page storage space in the memory, wherein the size of the cache page storage space is logic _ unit _ capacity; if the application of the cache page storage space fails, the step is repeatedly executed.

Preferably, the physical control key includes a block _ nums of memory blocks of the physical device, a page number of a single memory block of the physical device, page _ nums, a page byte number of a minimum page of the physical device, page _ bytes, a logical unit block logic _ unit _ capacity that can be operated at the minimum, whether to automatically cycle write a cycle, a logical unit number logic _ unit _ num, and a next writable logical unit address next _ write _ address.

Preferably, step 5, the operable logical unit number logic _ unit _ num is calculated:

logic_unit_num =

(block_nums+1)*( page_nums+1)*((page_bytes+1)/(logic_unit_capacity+1))-1。

preferentially, step 9, if the application of the cache page storage space is successful, writing the data into the cache page, and entering step 10;

step 10, judging whether the cache page is fully written with data, if so, entering step 11, otherwise, entering step 9;

step 11, obtaining the variable value of the logic address next _ write _ address, making logic _ unit _ capacity = next _ write _ address, and according to logic _ unit _ num =

And (block _ nums + 1) ((page _ bytes + 1)/(logic _ unit _ capacity + 1)) -1, and calculating to obtain block _ nums, page _ nums and page _ bytes.

Preferentially, step 12, if the physical memory address is a block boundary or a page boundary, executing an erasing operation and entering step 13, otherwise, directly entering step 13;

and step 13, accumulating the variable value in the next _ write _ address, and updating the variable value in the next _ write _ address.

Preferentially, step 14, judging whether the variable value in the next _ write _ address is successfully written into the logic address storage area, if so, entering step 15, otherwise, entering step 12;

step 15, store the variable value of the next _ write _ address into the logical address storage area, and proceed to step 10.

Preferably, in step 91, before entering step 9, the following steps are performed:

judging whether the cache address of the region to be stored is empty, if so, entering a step 9, otherwise, obtaining a variable value in the next _ write _ address, and according to a mapping formula logic _ unit _ num =

(block _ nums + 1) ((page _ bytes + 1)/(logic _ unit _ capacity + 1)) -1, let logic _ unit _ capacity = next _ write _ address, calculate block _ nums, page _ nums and page _ bytes.

At step 92, a specified amount of data is read into the logical address storage area.

Preferably, the data includes picture data and text data in byte form.

An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any of the above methods when executing the program.

A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method of any of the above.

The invention achieves the following beneficial effects:

in a first aspect, the present invention is mainly used for solving the problem of inconsistent reading and writing based on a block storage device, and an abstract physical control layer is used for managing and adapting a physical storage space, and the physical control layer mainly comprises a group of control keywords for managing and adapting the physical storage space.

In the second aspect, the invention adopts a mode of circularly writing in the physical storage space in sequence, and naturally has the characteristic of writing balance, thereby avoiding bad blocks caused by repeatedly erasing and writing a single storage space.

In the third aspect, the invention establishes hash mapping of logical addresses and physical addresses, so that the read-write time complexity is O (1).

In the fourth aspect, the logical page cache is established at the operation end, the logical writing is further abstracted, the writing operation can adopt any length, so that the characteristic of short-write long-memory is met, and the logical page cache mechanism is established in the erasing process, so that the data writing with any length can be met.

In a fifth aspect, the reading of the present invention can adopt two ways, one is to read data with any length by using a logical address as a base address; the other is to read specific byte data by using the data content as a key word and adopting an algorithm searching mode.

Drawings

Fig. 1 is a block diagram of a BMS system data local storage;

FIG. 2 is a block diagram of the Nandflash block storage hardware;

FIG. 3 is a block diagram of the present invention;

FIG. 4 is a diagram of an abstract control class and physical storage structure;

FIG. 5 is a logic flow diagram of the present invention;

FIG. 6 is a diagram of cache page write logic according to the present invention.

Detailed Description

The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

The invention is realized by the following technical scheme:

in a first aspect, the present invention abstracts a physical control layer for managing and adapting physical storage space, the physical control layer consisting essentially of a set of control keys.

In a second aspect, the invention adopts a cyclic writing mode for the physical storage space, and has the characteristic of writing balance naturally, thereby avoiding bad blocks caused by repeated erasing and writing of a single storage space.

In the third aspect, the invention establishes Hash mapping between the logical address and the physical address, and the read-write time complexity is O (1).

In the fourth aspect, the invention establishes the logical page cache at the operation end, further abstracts the logical writing, and can adopt any length for the writing operation, thereby meeting the characteristic of 'short-write long-memory'.

In the fifth aspect, the reading of the invention can adopt two modes, one mode is that the logic address is used as a base address to read data with any length; the other is to read specific byte data by using the data content as a key word and adopting an algorithm searching mode.

(1) Device hardware architecture and logical port

Nandflash is a typical block memory device, and is characterized in that a block (block) -page (page) -byte (byte) is used as a partition structure, and generally, a page (page) is used as a read-write unit, and a block (block) is used as an erase unit.

Fig. 1 is a view of a local storage structure of BMS system data, in which a physical interface and each logic control module of the Nandflash block storage device are provided on the left side, the Nandflash block storage device and a main control chip use a high-speed SPI bus as a physical channel for communication, and data interaction is performed through a serial controller of the Nandflash block storage device.

Fig. 2 is a structural diagram of a Nandflash block memory device, wherein the Nandflash block memory device is mainly composed of 1024 memory block stacks, each block includes 64 memory page pages, and each memory page can store 2048 bytes.

(2) Integral frame structure

FIG. 3 is an overall framework diagram of the present invention, employing software and hardware abstraction and a layered architecture. The specific physical block storage structure is positioned at the bottommost layer, the driving interface layer is responsible for driving specific physical hardware and driving an interface to an upper-layer abstract device, and the abstract interface layer is an API interface for calling abstraction for an upper layer by the storage block control system. The data writing caching and reading algorithm is supported by adopting an interface definition mode, the dynamic property is good, the expandability is strong, and the data comprises the image data and the character data in a byte form.

(3) Data structure

Fig. 4 shows the data structure of the abstract control class on the left and the physical storage structure diagram corresponding to some key control words on the right. Wherein, block _ nums represents the number of storage blocks of an actual physical storage medium, page _ nums represents the number of storage pages of each storage block, page _ bytes represents each storage page, logic _ unit _ capacity represents the minimum operable logical unit block, that is, the logical page size, cycle represents whether to automatically cycle write, logic _ unit _ num represents the operable logical unit number, next _ write _ address represents the next writable logical unit address, txcnt represents the number of bytes that can be written in a logical page, and txbuff represents the logical page cache space address.

Assume that a physical structure of a block storage device is 1024 blocks, each block contains 64 physical pages, and each physical page contains 2048 bytes to store. Then block _ nums =1023, page _nums =63, page _bytes =2047. Assuming that the minimum number of bytes written in a single time of the storage device is 512, logic _ unit _ capacity =511, and the calculation formula between logic \/u num and the physical parameter is logic _ unit _ num =

(block _ nums + 1) ((page _ bytes + 1)/(logic _ unit _ capacity + 1)) -1, which is an address mapping formula.

(4) Logic structure

Fig. 5 is a control logic flow chart, which is mainly divided into three parts: an initialization portion, an erasure portion and a read data portion.

(A) Initialization section

Step 1, initializing a physical interface of a block storage device.

And 2, calling a feature information reading interface function to read the hardware information.

And 3, calculating a physical storage structure of the hardware according to the hardware information, and initializing the value of a physical control key word, wherein the physical control key word comprises block _ nums, page _ bytes, logic _ unit _ capacity, cycle, logic unit number, logic _ unit _ num and next _ write _ address.

Block _ nums represents the number of storage blocks of the physical device, page _ nums represents the number of pages of a single storage block of the physical device, page _ bytes represents the number of bytes of a single page of a minimum page of the physical device, and logic _ unit _ capacity represents the number of minimum logical storage units preset by a user.

And 4, initializing a cycle keyword into a preset initial value according to a global predefined setting parameter, wherein the keyword controls whether old data is covered in the cyclic writing process.

Step 5, calculating the operable logic unit quantity logic _ unit _ num according to a formula;

the calculation formula is logic _ unit _ num =

(block _ nums + 1) ((page _ bytes + 1)/(logic _ unit _ capacity + 1)) -1. The formula is mainly based on the maximum byte number which can be stored by the hardware device, and the operable logic unit number is obtained by dividing the maximum byte number by the preset logic storage unit number. The formula carries out linear mapping on a physical storage address and a logical operation address to form a Hash mapping structure with the searching complexity of O (1).

Step 6, assigning the calculated operable logical unit quantity to a logic _ unit _ num keyword;

and 7, reading the next _ write _ address of the last to-be-written logical address from the logical address storage area, wherein the specific storage area is called a logical address storage area. The main function of this area is to remember the value of the next _ write _ address variable of the last operation, each time a modification is performed on this variable, a variable write is triggered.

If reading the logical address next _ write _ address fails, setting the logical address next _ write _ address as a default starting address, and entering step 8, if reading the logical address next _ write _ address succeeds, directly entering step 8.

Step 8, as shown in fig. 6, the system firstly applies for a cache page storage space in the memory, where the cache page storage space is logic _ unit _ capacity. If the application of the cache page storage space is successful, the step 9 is entered, otherwise, the step is executed repeatedly. The cache page is initially free and gradually fills as data is written. In each writing process, the erasure checking mechanism is triggered, and the erasure part logic is as follows.

(B) Erase and erase parts

Step 9, the system calls a data writing interface, data is firstly written into a cache page in a byte stream mode, the organization structure of the data is not limited, the size and the format of data writing in each time can be defined by a user, and the step 10 is entered.

step 11, obtaining a variable value in the logical address next _ write _ address, and calculating corresponding block _ nums, page _ nums, and page _ bytes by letting logic _ unit _ capacity = next _ write _ address according to a mapping formula of block _ unit _ num = (block _ nums + 1) × (page _ nums + 1) ((page _ bytes + 1)) -1.

Step 12, since the physical storage block generally executes the erase operation by block and page boundaries, before executing the write, it needs to check block _ nums, page _ nums, and page _ bytes parameters, which constitute the physical storage address, if the physical storage address is a block boundary or a page boundary, the erase operation is executed and step 13 is entered, otherwise, the step 13 is directly entered;

step 13, accumulating the variable value in the next _ write _ address and updating the variable value in the next _ write _ address;

step 14, judging whether the variable value in the next _ write _ address is successfully written into the logic address storage area, if so, entering step 15, otherwise, entering step 12;

step 15, store the variable value of next _ write _ address into the logical address storage area, and go to step 10.

As shown in fig. 6, when the write data interface is called, the logic of this part writes data into the cache page first. And if the cache page data is not fully written, directly returning and waiting for subsequent data writing.

If the cache page is full, physical parameters of the actual storage area, namely, block _ num, page _ num and page _ bytes parameters, are calculated according to a variable value in the current next _ write _ address and a formula of logic _ unit _ num = (block _ num + 1) ((page _ num + 1)) -1. Such as the block area, page offset address, etc.

Before the actual writing is executed, whether the boundary is a block boundary or not is checked, and a block erasing command is executed according to the parameter information. After the erase is performed, the variable value of the next _ write _ address is modified, and the variable value of the next _ write _ address is stored in the logical address storage area, and then the actual data write is performed.

(C) Read data section

Step 91, before determining whether to call the data writing interface, the following steps are performed:

judging whether the cache address of the region to be stored is empty, if yes, entering step 9, if not, obtaining the variable value in the next _ write _ address of the logic address,

according to the mapping formula logic _ unit _ num =

(block _ nums + 1) ((page _ bytes + 1)/(logic _ unit _ capacity + 1)) -1 and the variable value in the logical address next _ write _ address, let logic _ unit _ capacity = next _ write _ address, calculate block _ nums, page _ nums and page _ bytes.

Step 92, call the actual data reading interface to read the specified amount of data into the logical address storage area.

When the logic calls the data reading interface, the logic firstly checks whether the address of the area to be stored is empty. If the cache address is not empty, physical parameters of the actual storage area, such as a block area, a page offset address and the like, are calculated according to the transmitted logical address and a formula. And then calling an actual data reading interface to read the specified amount of data to the area to be stored. Since the actual physical addresses are stored in sequence, the corresponding logical addresses are also stored linearly. Therefore, if the stored data is also encoded in sequence based on the sequential storage, the search of the data based on the search algorithm can be supported.

The invention is mainly used for solving the problem of inconsistent reading and writing based on the block storage device, and the main method is to adopt a group of control keywords for managing and adapting physical storage space and establishing Hash mapping of physical addresses and logical storage addresses, so that the time complexity of reading and writing is O (1). The actual writing in the physical layer is in sequence, and the method has the characteristic of writing balance naturally, so that bad blocks caused by repeated erasing and writing of a single storage unit can be avoided. In the writing process, the bad block storage can be identified and skipped through logic control, and the compatibility is good. A logical page cache mechanism is established in the erasing process, and the writing of data with any length can be met. When reading data, the sequential reading of logical addresses is satisfied, and an sequential lookup algorithm can be supported. The invention has strong applicability and high stability and reliability.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, it is possible to make various improvements and modifications without departing from the technical principle of the present invention, and those improvements and modifications should be considered as the protection scope of the present invention.

Claims

1. A high-speed self-balancing storage control method is characterized by comprising the following steps:

step 1, initializing a physical interface of a block storage device;

step 4, initializing cycle keywords to a preset initial value;

step 5, calculating the operable logic unit quantity logic _ unit _ num;

2. The high-speed self-balancing storage control method according to claim 1,

the physical control key comprises the number of storage blocks of the physical device, the number of pages of a single storage block of the physical device, page _ nums, the number of bytes of a single page of a minimum page of the physical device, page _ bytes, the minimum operable logical unit block, logic _ unit _ capacity, whether to automatically and circularly write the cycle, the number of logical units, logic _ unit _ num, and the next writable logical unit address, next _ write _ address.

3. The method of claim 2, wherein the high-speed self-balancing storage control system comprises a storage controller,

step 5, calculating the operable logic unit quantity logic _ unit _ num:

logic_unit_num =

(block_nums+1)*( page_nums+1)*((page_bytes+1)/(logic_unit_capacity+1))-1。

4. the high-speed self-balancing storage control method according to claim 3,

step 9, if the application of the cache page storage space is successful, writing the data into the cache page, and entering step 10;

5. The high-speed self-balancing storage control method according to claim 4, further comprising:

step 12, if the physical memory address is a block boundary or a page boundary, executing an erasing operation and entering step 13, otherwise, directly entering step 13;

the high-speed self-balancing storage control method according to claim 5, further comprising:

6. The high-speed self-balancing storage control method according to claim 4,

step 91, before entering step 9, the following steps are performed:

7. At step 92, a specified amount of data is read into the logical address storage area.

8. The high-speed self-balancing storage control method according to claim 4,

the data includes picture data and text data in byte form.

9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method of any one of claims 1 to 8 when executing the program.

10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 8.