CN115967415A - Feedforward echo eliminating device and echo eliminating method - Google Patents

Feedforward echo eliminating device and echo eliminating method Download PDF

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Publication number
CN115967415A
CN115967415A CN202111186944.9A CN202111186944A CN115967415A CN 115967415 A CN115967415 A CN 115967415A CN 202111186944 A CN202111186944 A CN 202111186944A CN 115967415 A CN115967415 A CN 115967415A
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China
Prior art keywords
current
circuit
echo cancellation
node
echo
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CN202111186944.9A
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Chinese (zh)
Inventor
陈建文
廖宜庆
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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Priority to CN202111186944.9A priority Critical patent/CN115967415A/en
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

The feedforward echo cancellation device comprises a first impedance circuit, a second impedance circuit and an echo cancellation current generation circuit. The first impedance circuit is used for responding to the transmission current to output a first current to the node. The second impedance circuit is used for responding to the transmission current to output a second current to the node. The echo cancellation current generation circuit is used for drawing an echo cancellation current from the node. The node is connected to an input terminal of the programmable gain amplifier circuit through a gain control circuit, and the gain control circuit is used for setting an amplification gain of the programmable gain amplifier circuit.

Description

Feedforward echo eliminating device and echo eliminating method
Technical Field
The present disclosure relates to an echo cancellation device, and more particularly, to a feedforward echo cancellation device applied to an ethernet device and an echo cancellation method thereof.
Background
In a full duplex (full duplex) communication system, a communication device may transmit and receive signals simultaneously. Thus, the signal received by the receiver in the communication device may include an echo (echo) generated based on the data signal output from the local transmitter and a data signal transmitted from another communication device. In order to correctly obtain the data signal transmitted from another communication device, an echo cancellation device may be used to reduce the effect of echo. In some related arts, the compensation signal generated by the echo cancellation device and the echo have mismatch in a high frequency band, so that the compensation signal cannot effectively reduce the influence of the echo. On the other hand, in these related arts, the echo cancellation device cancels the echo by summing the compensation signal and the signal output from the programmable gain amplifier in the communication device. However, when the communication device adjusts the amplification gain of the programmable gain amplifier according to the system operation state, the echo cancellation device is not adjusted correspondingly, so that the compensation signal may not effectively reduce the effect of the echo.
Disclosure of Invention
In some embodiments, a feed-forward echo cancellation device includes a first impedance circuit, a second impedance circuit, and an echo cancellation current generation circuit. The first impedance circuit is used for responding to the transmission current to output a first current to a node. The second impedance circuit is used for responding to the transmission current to output a second current to the node. The echo cancellation current generation circuit is used for drawing an echo cancellation current from the node. The node is connected to the input end of the programmable gain amplifier circuit through a gain control circuit, and the gain control circuit is used for setting the amplification gain of the programmable gain amplifier circuit.
In some embodiments, an echo cancellation method includes the operations of: outputting a first current to a node in response to a transmission current, wherein the node is connected to an input of a programmable gain amplifier circuit via a gain control circuit, and the gain control circuit is configured to set an amplification gain of the programmable gain amplifier circuit; drawing an echo cancellation current from the node; and outputting a second current to the node in response to the transmit current, wherein a sum of the first current and the second current approximates the echo cancellation current.
The features, implementations, and functions of the present disclosure will be described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram illustrating a near-end communication device in accordance with some embodiments of the present disclosure;
FIG. 2 is a schematic diagram illustrating a frequency response of the plurality of currents and the echo cancellation current of FIG. 1, according to some embodiments of the present disclosure;
FIG. 3 is a circuit schematic diagram illustrating the feedforward echo cancellation device and amplifier of FIG. 1 in accordance with some embodiments of the present disclosure; and
FIG. 4 is a flow chart illustrating an echo cancellation method according to some embodiments of the present disclosure.
Detailed Description
All words used herein have their ordinary meaning. The definitions of the above words in commonly used dictionaries, including any use examples of the words discussed herein, in this disclosure are by way of example only and should not be construed as limiting the scope and meaning of the disclosure. Likewise, the disclosure is not intended to be limited to the various embodiments shown in the description.
As used herein, the terms "coupled" or "connected," may mean that two or more elements are in direct, indirect, or mutual physical or electrical contact, and may also mean that two or more elements are in mutual operation or action. As used herein, the term "circuit" may be a device connected by at least one transistor and/or at least one active and passive component in a manner to process a signal.
As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The terms first, second, third and the like may be used herein to describe and distinguish various elements. Thus, a first component may also be referred to herein as a second component without departing from the spirit of the present disclosure. For ease of understanding, similar components in the various figures will be designated by the same reference numerals.
As used herein, "about," "near," or "the same" generally refers to an error or range in actual values that is within about twenty percent, preferably within about ten percent, and more preferably within about five percent. Unless expressly stated otherwise, all numbers reported herein are to be interpreted as approximations, as indicated by the error or range of values "about", "near" or "the same".
Fig. 1 is a schematic diagram illustrating a near-end communication device 10 according to some embodiments of the present disclosure. In some embodiments, the near-end communication device 10 may be, but is not limited to, an ethernet network device. For example, the near-end communication device 10 may be part of an ethernet interface controller. The near-end communication device 10 may include a transmitter circuit 11, a receiver circuit 12, a transmission current generation circuit 13, a feedforward echo cancellation device 14, an amplifier 15, and a control circuit 16.
The transmitter circuit 11 is used to transmit the data signal SD to the remote communication device 20 via the cable 30. The transmission current generating circuit 13 is used for generating a transmission current I TX . In some embodiments, the transmission current generating circuit 13 can be, but is not limited to, a current-mode digital-to-analog converter circuit for converting information to be transmitted by the near-end communication device 10 into the transmission current I TX . In this way, the transmitter circuit 11 can be based on the transmission current I TX A data signal SD is generated. The receiver circuit 12 may receive data signals from the remote communication device 20 via the cable 30. During the process of receiving the signal, the receiver circuit 12 may receive the data signal SD generated by the transmitter circuit 11, so that the near-end communication device 10 is affected by the echo to generate nonlinear distortion. The echo canceller 14 of the feedforward type can be used to generate a plurality of currents (e.g., a current I described later) 2 And an echo cancellation current I EC ) To reduce the effect of the echo.
Specifically, the feedforward echo canceller 14 includes an impedance circuit 141, an impedance circuit 142, and an echo cancellation current generation circuit 143. The impedance circuit 141 may provide an impedance (e.g., the resistor R1 in fig. 3) having a value such that the input equivalent impedance is the same as (or close to) the impedance on the path of the near-end communication device 10 transmitting the signal to the far-end communication device 20. Impedance circuit 141 responds to transmission current I TX Generating a current I 1 To node N1 (denoted as plus sign). In other words, by providing the impedance circuit 141, the current I can be utilized 1 Simulating the echoes received by the receiver circuit 12. The impedance circuit 142 is responsive to the transmission current I TX Generating a current I 2 To node N1 (denoted as plus). The echo cancellation current generating circuit 143 is used for drawing an echo cancellation current I from the node N1 EC (denoted as minus). In some embodiments, an echo cancellation current generation circuit143 may operate as a current source circuit coupled between node N1 and ground to draw an echo cancellation current I from node N1 EC . In some embodiments, echo cancellation current generation circuit 143 may be a current mode digital-to-analog converter circuit that may be controlled by control circuit 16 to set the echo cancellation current I EC 。
Further, as shown in fig. 1, data received by the receiver circuit 12 (denoted as data signal SI) is transmitted to the amplifier 15 via the node N1. In this manner, the amplifier 15 may amplify the data signal SI for data processing by subsequent circuits (e.g., without limitation, the control circuit 16). Data signal SI, current I 1 Current I 2 And echo cancellation current I EC It is summed at node N1 and passed to amplifier 15. Therefore, if the current I is 1 Current I 2 And echo cancellation current I EC The sum of the three is (or is close to) 0, and the current I 1 Current I 2 And echo cancellation current I EC May cancel each other at node N1 so that the amplifier 15 may receive the data signal SI that is less affected by the echo. In this way, the amplifier 15 can generate a more accurate data signal. In other words, due to the current I 1 Corresponding to an echo, if the current I 1 Current I 2 And echo cancellation current I EC The sum of the three is (or close to) 0, which means that the echo can be eliminated (or reduced), so that the near-end communication device 10 can interpret the received data more accurately. With respect to the current I 1 Current I 2 And an echo cancellation current I EC The correspondence between them will be described later with reference to fig. 2.
Amplifier 15 includes a gain control circuit 150 and a programmable gain amplifier circuit 152. The gain control circuit 150 sets an amplification gain of the programmable gain amplifier circuit 152 according to the control of the control circuit 16. In some embodiments, the gain control circuit 150 may be an ac coupling circuit, but is not limited thereto. In some embodiments, the gain control circuit 150 may be part of a feedback network of the programmable gain amplifier circuit 152. Node N1 is connected to a programmable gain amplifier circuit 152 via a gain control circuit 150. The control circuit 16 can analyze a system convergence indicator according to the output signal of the programmable gain amplifier circuit 152 to determine whether the gain control circuit 150 needs to be adjusted to set the amplification gain of the programmable gain amplifier circuit 152. In some embodiments, the system convergence indicator may include (but is not limited to) the power of the echo, the signal-to-noise ratio, and the like.
In some embodiments, control circuit 16 may include, but is not limited to, analog-to-digital conversion circuitry (not shown in FIG. 1) and digital signal processor circuitry (not shown in FIG. 1). The adc circuit converts the output signal of the programmable gain amplifier circuit 152 into digital data, and the dsp circuit performs a specific algorithm to determine the system convergence indicator according to the digital data.
As shown in fig. 1, the impedance circuit 141, the impedance circuit 142, and the echo cancellation current generation circuit 143 cancel the echo at a node N1 connected to the input terminal of the amplifier 15. In other words, the impedance circuit 141, the impedance circuit 142, and the echo cancellation current generation circuit 143 may share the gain control circuit 150 and the programmable amplifier circuit 152. Under such a condition, when the control circuit 16 adjusts the amplification gain of the amplifier 15 according to the current operation state, the frequency response of each of the impedance circuit 141, the impedance circuit 142, and the echo cancellation current generation circuit 143 may be adjusted together. Thus, the current I 1 Current I 2 And an echo cancellation current I EC May then be adjusted to achieve better echo cancellation.
FIG. 2 illustrates the current I of FIG. 1 according to some embodiments of the present disclosure 1 Current I 2 And an echo cancellation current I EC A frequency response of (a). In some embodiments, the gain may be calculated by dividing the current output by the gain control circuit 150 (hereinafter referred to as current IPGA) by the corresponding current to obtain the frequency response of the corresponding current. For example, current I 1 Can be expressed as IPGA/I 1 Current I of 2 Can be expressed as IPGA/I 2 And current I EC Can be expressed as IPGA/I EC 。
As previously mentioned, the current I 1 May be considered an echo. Echo cancellation current I EC Can be used to measure the current I 1 Cancel each other at node N1 to reduce the effect of the echo. Ideally, the echo cancellation current I EC Should be the same as (or close to) the current I 1 . However, due to the difference in the actual impedance of the transmission path, the current I 1 And echo cancellation current I EC The presence of mismatch in the high frequency band will result in an echo cancellation current I EC Not identical to (or close to) the current I 1 . The impedance circuit 142 may provide a current I 2 To node N1 to compensate for the energy mismatch at the high frequency band. I.e. the current I 1 And current I 2 Approximately close to (or the same as) the echo cancellation current I EC (can be represented as I) 1 +I 2 ≒I EC )。
Fig. 3 is a circuit schematic diagram illustrating the feedforward echo cancellation device 14 and the amplifier 15 of fig. 1 according to some embodiments of the present disclosure. In this embodiment, the impedance circuit 141 includes a resistor R1 that can transmit a current I TX The output is current I 1 . One end of the resistor R1 and the echo cancellation current generation circuit 143 are coupled to the node N1, and the echo cancellation current generation circuit 143 is coupled between the node N1 and the ground. As such, echo cancellation current generation circuit 143 may draw echo cancellation current I from node N1 EC . The impedance circuit 142 includes a resistor RF and a capacitor CF. The resistor RF and the capacitor CF form a high-pass signal path in response to the transmission current I TX Generating a current I 2 . In some embodiments, the capacitor CF may be a capacitor network or a capacitor array network, which may adjust the capacitance value of the capacitor CF according to the control of the control circuit 16. In some embodiments, the resistor RF and the capacitor CF may be used to control the bandwidth of the high-pass signal path. For example, the product of the resistance RF and the capacitance CF can be used to determine the current I in FIG. 2 2 Corner frequency (corner frequency).
In this embodiment, the impedance circuit 141 is directly coupled to the node N1 to pass the current I 1 To node N1. The impedance circuit 142 is directly coupled to the node N1 for passing the current I 2 To node N1. Similarly, the echo cancellation current generation circuit 143 is directly coupled to the node N1 to draw the echo cancellation current I from the node N1 EC To ground. In other words, the current I 1 Current I 2 And an echo cancellation current I EC May be summed at node N1. As shown in FIG. 2, current I 1 And current I 2 Is fed into node N1 and the echo cancellation current I EC Is flowing from node N1. Under this condition, the current I 1 Current I 2 And an echo cancellation current I EC Can be represented as I 1 +I 2 -I EC ≒0。
Furthermore, the node N1 is further connected to the input terminal of the programmable gain amplifier circuit 152 via the gain control circuit 150. The gain control circuit 150 may be, for example but not limited to, an ac coupling circuit (which may be a dc coupling circuit in some embodiments), which includes a capacitor C1 and a capacitor C2. The capacitor C1 is coupled between the node N1 and the input terminal of the programmable gain amplifier circuit 152. The capacitor C2 is coupled between the node N1 and the ground. In some embodiments, each of the capacitors C1 and C2 may be a switched capacitor circuit or a capacitor network. The equivalent capacitance value of the gain control circuit 150 can be determined by the capacitor C1 and the capacitor C2. As previously described, the data signal SI may be transmitted to the programmable gain amplifier circuit 152 via the node N1 and the gain control circuit 150. Therefore, if the capacitance value of the capacitor C1 is larger, the corresponding ac impedance is lower, and the energy transmitted to the programmable gain amplifier circuit 152 via the gain control circuit 150 in the data signal SI can be increased. In this way, the amplification gain of the programmable gain amplifier circuit 152 can be increased. Alternatively, if the capacitance value of the capacitor C1 is smaller, the corresponding ac impedance is higher, so that the energy transmitted to the programmable gain amplifier circuit 152 via the gain control circuit 150 in the data signal SI can be reduced. In this manner, the amplification gain of the programmable gain amplifier circuit 152 can be reduced.
In some embodiments, the amplifier 15 may further include a feedback network, which may be used to adjust the amplification gain and/or frequency response of the programmable gain amplifier circuit 152. For example, the amplifier 15 includes a feedback network 154 coupled between the input and the output of the programmable gain amplifier circuit 152. The feedback network 154 includes a variable resistor RFB and a capacitor CFB. The variable resistor RFB may change its impedance value based on the control of the control circuit 16 to set the amplification gain of the programmable gain amplifier circuit 152 in cooperation with the gain control circuit 150 or to set the frequency response of the programmable gain amplifier circuit 152.
The arrangement of fig. 3 is for example, and the disclosure is not so limited. Various arrangements of feedforward echo cancellation that share the same gain control circuit and programmable gain amplifier circuit are within the scope of this disclosure.
Fig. 4 is a flow chart illustrating an echo cancellation method 400 according to some embodiments of the present disclosure. In some embodiments, the operations of fig. 4 may be performed by (but not limited to) the echo cancellation device 14 of the feedforward type of fig. 1.
In operation S410, in response to a transmission current (e.g., transmission current I) TX ) A first current (e.g. current I) 1 ) The output is provided to a node (e.g., node N1), wherein the node is connected to an input terminal of a programmable gain amplifier circuit (e.g., gain control circuit 152) via a gain control circuit (e.g., gain control circuit 150), and the gain control circuit is configured to set an amplification gain of the programmable gain amplifier circuit.
In operation S420, an echo cancellation current (e.g., current I) is drawn from the node EC )。
In operation S430, a second current (e.g., current I) is applied in response to the transmission current 2 ) And outputting to the node, wherein the sum of the first current and the second current is close to the echo cancellation current.
The above operations can be understood by referring to the description of the foregoing embodiments, and thus, the description is not repeated herein. The operations of the echo cancellation method 400 described above are merely examples and need not be performed in the order shown in this example. The various operations under the echo cancellation method 400 may be added, replaced, omitted, or performed in a different order (e.g., simultaneously or partially simultaneously) as appropriate without departing from the manner and scope of operation of various embodiments of the present disclosure.
In summary, the feed-forward echo cancellation device and the echo cancellation method in some embodiments of the disclosure may be automatically adjusted when the communication device adjusts the circuit configuration according to the current operation state, so as to achieve better echo cancellation.
Although the embodiments of the present disclosure have been described above, these embodiments are not intended to limit the present disclosure, and those skilled in the art can make variations on the technical features of the present disclosure according to the explicit or implicit contents of the present disclosure, and all such variations may fall within the scope of the patent protection sought by the present disclosure.
[ description of symbols ]
10: near-end communication device
11: transmitter circuit
12: receiver circuit
13: transmission current generating circuit
14: feedforward echo eliminator
141: impedance circuit
142: impedance circuit
143: echo cancellation current generation circuit
15: amplifier
150: gain control circuit
152: programmable gain amplifier circuit
154: feedback network
16: control circuit
20: remote communication device
30: cable wire
400: echo cancellation method
C1, C2, CF, CFB: capacitor with a capacitor element
I 1 、I 2 : electric current of
I EC : echo cancellation current
I TX : transmitting electric current
N1: node point
R1, RF: resistance (RC)
RFB: variable resistor
S410, S420, S430: operation of
SD, SI: data signal

Claims (10)

1. A feed-forward echo canceller comprising:
a first impedance circuit to output a first current to a node in response to a transmission current;
a second impedance circuit for outputting a second current to the node in response to the transmission current; and
an echo cancellation current generation circuit for drawing an echo cancellation current from the node,
wherein the node is connected to an input of a programmable gain amplifier circuit via a gain control circuit for setting an amplification gain of the programmable gain amplifier circuit.
2. A feed-forward echo cancellation device according to claim 1, wherein said first current, said second current and said echo cancellation current cancel each other at said node.
3. A feed-forward echo cancellation device according to claim 1, wherein the sum of the first current and the second current is the same as the echo cancellation current.
4. A feed-forward echo cancellation device as claimed in claim 1, wherein said first impedance circuit, said second impedance circuit, and said echo cancellation current generation circuit are directly coupled to said node.
5. A feedforward echo cancellation device in accordance with claim 1, wherein the gain control circuit is an ac coupling circuit or a dc coupling circuit.
6. A feedforward echo cancellation device in accordance with claim 1, wherein the second impedance circuit includes a resistor and a capacitor, and the resistor and the capacitor are used to set a corner frequency of the second current.
7. A feed forward echo cancellation device as claimed in claim 1, wherein said echo cancellation current generating circuit is a current mode digital to analog converter circuit.
8. A feedforward echo cancellation device in accordance with claim 1, wherein the gain control circuit is configured to be adjusted based on a system convergence indicator to set the amplification gain.
9. A feed forward echo cancellation device according to claim 1, wherein said node is further configured to receive a data signal and to transmit said data signal to said programmable gain amplifier circuit.
10. An echo cancellation method, comprising:
outputting a first current to a node in response to a transmit current, wherein the node is connected to an input of a programmable gain amplifier circuit via a gain control circuit, and the gain control circuit is configured to set an amplification gain of the programmable gain amplifier circuit;
drawing an echo cancellation current from the node; and
outputting a second current to the node in response to the transmit current, wherein a sum of the first current and the second current approximates the echo cancellation current.
CN202111186944.9A 2021-10-12 2021-10-12 Feedforward echo eliminating device and echo eliminating method Pending CN115967415A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111186944.9A CN115967415A (en) 2021-10-12 2021-10-12 Feedforward echo eliminating device and echo eliminating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111186944.9A CN115967415A (en) 2021-10-12 2021-10-12 Feedforward echo eliminating device and echo eliminating method

Publications (1)

Publication Number Publication Date
CN115967415A true CN115967415A (en) 2023-04-14

Family

ID=87360365

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111186944.9A Pending CN115967415A (en) 2021-10-12 2021-10-12 Feedforward echo eliminating device and echo eliminating method

Country Status (1)

Country Link
CN (1) CN115967415A (en)

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