CN115966547A

CN115966547A - Inductor and chip

Info

Publication number: CN115966547A
Application number: CN202111091043.1A
Authority: CN
Inventors: 刘水华
Original assignee: Shanghai Boxincheng Microelectronics Technology Co ltd
Current assignee: Shanghai Boxincheng Microelectronics Technology Co ltd
Priority date: 2021-09-17
Filing date: 2021-09-17
Publication date: 2023-04-14
Anticipated expiration: 2041-09-17
Also published as: CN115966547B

Abstract

The embodiment of the application provides an inductor and a chip, and the inductor comprises an insulating substrate, a first inductance layer and a second inductance layer. The first insulating layer of the first inductance layer is arranged between the first conducting layer and the second conducting layer, a first connecting line in the first conducting layer is electrically connected with the peripheral endpoint of the first conducting coil in the first conducting layer, and a second connecting line included in the second conducting layer is electrically connected with the inner peripheral endpoint of the first conducting coil; a second insulating layer of the second inductance layer is arranged between the third conducting layer and the fourth conducting layer, a third connecting wire in the third conducting layer is electrically connected with a peripheral end point of a second conducting coil in the third conducting layer, and a fourth connecting wire included in the fourth conducting layer is electrically connected with an inner peripheral end point of the second conducting coil; the first inductance layer and the second inductance layer are respectively arranged on two opposite sides of the insulating substrate. The inductor adopts the insulating substrate as the substrate, so that the preparation efficiency is high, the process difficulty is low, the yield of finished products is high, and the inductor has better coupling performance.

Description

Inductor and chip

[ technical field ] A method for producing a semiconductor device

The present application relates to the field of microelectronics, and in particular, to an inductor and a chip.

[ background of the invention ]

With the rapid development of the electronic information industry, the update iteration speed of electronic products is high, and the electronic products are developed towards higher and higher speeds, miniaturization and intellectualization, so as to meet the requirements of the market on quick response, low cost, low power consumption, portability, easy carrying and the like of the electronic products. Therefore, the use of low-cost and highly integrated electronic components has become a main means for solving the above problems.

Because high-performance passive devices, especially high-performance inductors, are difficult to integrate and have high cost, how to obtain low-cost high-performance inductors becomes a problem to be solved urgently in the development process of the electronic information industry. The current inductors mainly include discrete inductors, board level inductors, and on-chip inductors. The discrete inductors are mostly manufactured by winding coils in a mechanical winding mode and manufacturing a board level inductor based on a printed circuit board, so that the discrete inductors and the board level inductor are not suitable for the development trend of miniaturization of electronic products.

The on-chip inductor is an optimal electronic element meeting the development of the electronic information industry, but the on-chip inductor is prepared by taking monocrystalline silicon as a substrate, on one hand, the resistivity of the monocrystalline silicon is small, the relative dielectric constant is large, and the on-chip inductor has the problems of large substrate loss, substrate parasitic capacitance and the like, so that the performance of the on-chip inductor is seriously influenced; on the other hand, most on-chip inductors use Benzocyclobutene (BCB), polyimide (PI), silicon dioxide (SiO 2) and other materials as the isolation layer material between the coils, which leads to the problem of low breakdown field strength of the inductor.

[ contents of application ]

In view of the above, embodiments of the present application provide an inductor and a chip.

In a first aspect, an embodiment of the present application provides an inductor, including an insulating substrate, a first inductance layer, and a second inductance layer; the first inductance layer comprises a first conductive layer, a second conductive layer and a first insulating layer; the first conducting layer comprises a first conducting coil and a first connecting wire, and the first connecting wire is electrically connected with the peripheral endpoint of the first conducting coil; the second conducting layer comprises a second connecting wire, and the second connecting wire is electrically connected with the inner periphery endpoint of the first conducting coil; the first insulating layer is arranged between the first conducting layer and the second conducting layer; the second inductance layer comprises a third conducting layer, a fourth conducting layer and a second insulating layer; the third conducting layer comprises a second conducting coil and a third connecting line, and the third connecting line is electrically connected with the peripheral end point of the second conducting coil; the fourth conducting layer comprises a fourth connecting line, and the fourth connecting line is electrically connected with the inner periphery endpoint of the second conducting coil; the second insulating layer is arranged between the third conductive layer and the fourth conductive layer; the first inductance layer and the second inductance layer are respectively arranged on two opposite sides of the insulating substrate.

In one implementation form of the first aspect, the insulating substrate is one of glass, ceramic, glass fiber board, and polyimide film.

In one implementation form of the first aspect, the insulating substrate has a thickness of 0.5mm or less.

In one implementation manner of the first aspect, the material of the first conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper, and the material of the second conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper; the material of the third conducting layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper, and the material of the fourth conducting layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper.

In one implementation manner of the first aspect, the thicknesses of the first conductive layer and the third conductive layer are both greater than or equal to 600nm.

In one implementation manner of the first aspect, the first conductive coil comprises N circles of first conductive wires, the width of each first conductive wire is less than or equal to 100 μm, and N is greater than or equal to 1; the second conductive coil comprises M circles of second conductive wires, the width of each second conductive wire is less than or equal to 100 mu M, and M is larger than or equal to 1.

In one implementation manner of the first aspect, N is larger than or equal to 2, and the minimum distance between the adjacent first conductive lines is smaller than or equal to 100 μm; m is more than or equal to 2, and the minimum distance between the adjacent second conductive lines is less than or equal to 100 μ M.

In one implementation manner of the first aspect, the first conductive coil comprises a first spiral coil and a second spiral coil, and the first spiral coil is connected with the second spiral coil in parallel; the second conductive coil comprises a third spiral coil and a fourth spiral coil, and the third spiral coil and the fourth spiral coil are connected in parallel.

In an implementation manner of the first aspect, the first connection line, the second connection line, the third connection line, and the fourth connection line are all of a full-face structure.

In one implementation manner of the first aspect, the first conductive layer further includes first bonding pads, and the first connection line and the second connection line are electrically connected to different first bonding pads, respectively; the third conductive layer further comprises a second binding pad, and the third connecting line and the fourth connecting line are electrically connected with different second binding pads respectively.

In one implementation manner of the first aspect, the second conductive layer is disposed on one side of the first conductive layer close to the insulating substrate, the insulating substrate includes a first notch, and the second connection line is disposed in the first notch; and/or the fourth conducting layer is arranged on one side, close to the insulating substrate, of the third conducting layer, the insulating substrate comprises a second notch, and the second connecting line is arranged in the second notch.

In a second aspect, embodiments of the present application provide a chip including an inductor as provided in the first aspect.

The substrate of the inductor provided by the embodiment of the application adopts the insulating substrate as the substrate, so that the substrate can be prepared and formed by adopting a cutting process of the insulating substrate, the preparation efficiency is high, the process difficulty is small, and the yield of finished products is high. Compared with the prior art that the insulating substrate is adopted as the substrate, the silicon-based substrate is adopted as the substrate, so that the cost can be obviously saved, the substrate loss and the substrate parasitic capacitance can be greatly reduced, the performance of the inductor is greatly improved, and the isolation voltage of the inductor can be larger than 10000V.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic cross-sectional view of an inductor according to an embodiment of the present application;

fig. 2 is another schematic cross-sectional view of an inductor according to an embodiment of the present application;

fig. 3 is a schematic exploded plan view of an inductor according to an embodiment of the present application;

fig. 4 is a schematic cross-sectional view of an inductor according to another embodiment of the present application;

fig. 5 is a schematic cross-sectional view of an inductor according to another embodiment of the present application;

FIG. 6 is a cross-sectional view of an inductor according to yet another embodiment of the present application;

fig. 7 is a schematic diagram of a first conductive coil and a second conductive coil in an inductor according to an embodiment of the present application;

fig. 8 is a schematic diagram of a first conductive coil in an inductor according to another embodiment of the present application;

fig. 9 is a schematic diagram of a second conductive coil in an inductor according to another embodiment of the present application;

fig. 10 is a schematic cross-sectional view of an inductor according to yet another embodiment of the present application;

fig. 11 is a schematic diagram of a chip according to an embodiment of the present disclosure.

[ detailed description ] embodiments

In order to better understand the technical solution of the present application, the following detailed description is made with reference to the accompanying drawings.

It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely a relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.

In the description herein, it is to be understood that the terms "substantially", "approximately", "about", "substantially", and the like, as used in the claims and the examples herein, are intended to be generally accepted as not being precise, within the scope of reasonable process operation or tolerance.

It should be understood that although the terms first, second, third, etc. may be used to describe the connecting lines, etc. in the embodiments of the present application, these connecting lines, etc. should not be limited to these terms. These terms are only used to distinguish connecting lines and the like from each other. For example, the first connection line may also be referred to as a second connection line, and similarly, the second connection line may also be referred to as a first connection line without departing from the scope of the embodiments of the present application.

The applicant provides a solution to the problems of the prior art through intensive research.

Fig. 1 is a schematic cross-sectional view of an inductor according to an embodiment of the present application, fig. 2 is a schematic cross-sectional view of another inductor according to an embodiment of the present application, and fig. 3 is an exploded schematic plan view of an inductor according to an embodiment of the present application. It should be noted that fig. 1 and fig. 2 are schematic cross-sectional views of a cut line along different positions in an inductor, respectively.

Referring to fig. 1, 2 and 3, an inductor according to an embodiment of the present invention includes an insulating substrate 30, a first inductance layer 10 and a second inductance layer 20, where the first inductance layer 10 and the second inductance layer 20 are respectively disposed on two opposite sides of the insulating substrate 30, for example, as shown in fig. 1 and 2, the first inductance layer 10 is disposed above the insulating substrate 30, and the second inductance layer 20 is disposed below the insulating substrate 30. In addition, the first inductance layer 10 may be disposed below the insulating substrate, and in this case, the second inductance layer 20 is disposed above the insulating substrate 30.

Referring to fig. 1 and 2, the first inductor layer 10 includes a first conductive layer 11, a second conductive layer 12, and a first insulating layer 13, and the first insulating layer 13 is disposed between the first conductive layer 11 and the second conductive layer 12.

Further, referring to fig. 1, fig. 2 and fig. 3, the first conductive layer 11 includes a first conductive coil 111 and a first connection line 112, the first connection line 112 is electrically connected to a peripheral end of the first conductive coil 111, it should be noted that the first conductive coil 111 may be a spiral coil or a wave coil, and preferably, as shown in fig. 3, the first conductive coil 111 is a spiral coil.

The second conductive layer 12 includes a second connection line 121, and the second connection line 121 is electrically connected to the inner peripheral terminal of the first conductive coil 111. That is, one end of the first conductive coil 111 is electrically connected to the first connection line 112, and the other end is electrically connected to the second connection line 121.

With reference to fig. 1 and fig. 2, the second inductor layer 20 includes a third conductive layer 21, a fourth conductive layer 22 and a second insulating layer 23, and the second insulating layer 23 is disposed between the third conductive layer 21 and the fourth conductive layer 22.

Further, with reference to fig. 1, fig. 2 and fig. 3, the third conductive layer 21 includes a second conductive coil 211 and a third connecting line 212, and the third connecting line 212 is electrically connected to the peripheral end of the second conductive coil 211, it should be noted that the second conductive coil 211 may be a spiral coil or a wave coil, and preferably, as shown in fig. 3, the second conductive coil 211 is a spiral coil.

The fourth conductive layer 22 includes a fourth connection line 221, and the fourth connection line 221 is electrically connected to an inner peripheral terminal of the second conductive coil 211. That is, one end of the second conductive coil 211 is electrically connected to the third connection line 212, and the other end is electrically connected to the fourth connection line 221.

In the embodiment of the present application, as shown in fig. 1 and fig. 2, the first conductive layer 11 is located on one side of the second conductive layer 12 close to the insulating substrate 30; the third conductive layer 21 is located on a side of the fourth conductive layer 22 close to the insulating substrate 30. Note that the first conductive layer 11 may be located on the side of the second conductive layer 12 away from the insulating substrate 30, and the third conductive layer 21 may be located on the side of the fourth conductive layer 22 away from the insulating substrate 30. For example, the first conductive layer 11 is located on the side of the second conductive layer 12 close to the insulating substrate 30, and the third conductive layer 21 is located on the side of the fourth conductive layer 22 far from the insulating substrate 30; for another example, the first conductive layer 11 is located on a side of the second conductive layer 12 away from the insulating substrate 30, and the third conductive layer 21 is located on a side of the fourth conductive layer 22 close to the insulating substrate 30; for another example, the first conductive layer 11 is located on a side of the second conductive layer 12 away from the insulating substrate 30, and the third conductive layer 21 is located on a side of the fourth conductive layer 22 away from the insulating substrate 30.

The inductor in the present application may be manufactured by a cutting process of an insulating substrate, for example, the first conductive coil 111, the first connection line 112, the second connection line 121, the second conductive coil 211, the third connection line 212, and the fourth connection line 221 arranged in an array may be respectively manufactured on two opposite sides of a large glass, and then the large glass is cut to form a plurality of inductors.

Because the cost of the insulating substrate with the same area is far lower than that of the silicon-based substrate, compared with the prior art that the silicon-based substrate is adopted as the substrate, the inductor provided by the embodiment of the application adopts the insulating substrate as the substrate, so that the cost can be obviously saved. In addition, the embodiment of the application adopts the insulating substrate cutting process, for example, tens of thousands of inductors can be formed by cutting large glass, so that the preparation process is effectively simplified, and the preparation efficiency is improved. The cost of the inductor provided by the embodiment of the application is about one tenth of that of the silicon-based substrate inductor in the prior art.

In addition, in the embodiment of the application, because the insulating substrate has larger resistivity and smaller dielectric constant compared with a silicon-based substrate, the substrate loss and the substrate parasitic capacitance can be greatly reduced, and the performance of the inductor is greatly improved.

In the prior art, the insulating layers between the adjacent conductive coils of the inductor adopting the silicon-based substrate are generally prepared by adopting a thin film deposition technology, and the thickness of the insulating layers is generally in the order of micrometers, so that the limit of the isolation voltage of the inductor in the prior art is 6000V. And the thickness of the insulating substrate is in millimeter order, and the insulating substrate 30 is arranged between the first conductive coil 111 and the second conductive coil 211, so that the inductor has larger breakdown field intensity. The inventor finds that the isolation voltage of the inductor provided by the embodiment of the application can be greater than 10000V.

In an embodiment of the present application, as shown in fig. 1 and 2, the first conductive layer 11 further includes first bonding pads 113, and the first connection line 112 and the second connection line 121 are electrically connected to different first bonding pads 113, respectively. The third conductive layer 21 further includes second bonding pads 213, and the third connection line 212 and the fourth connection line 221 are electrically connected to the different second bonding pads 213, respectively.

The first bonding pad 113 and the first conductive layer 11 are disposed on the same layer, and the first bonding pad 113, the first conductive coil 111, and the first connection line 112 may be simultaneously prepared. The second bonding pad 213 and the third conductive layer 21 are disposed on the same layer, so that the second bonding pad 213, the second conductive coil 211 and the third connection line 212 may be simultaneously fabricated.

And the first bonding pad 113 is disposed to be different from the second conductive layer 12.

In one implementation, as shown in fig. 1, the second conductive layer 12 is disposed on a side of the first conductive layer 11 away from the insulating substrate 30, and the second connection line 121 may be electrically connected to the inner peripheral end point of the first conductive coil 111 through a via hole located in the first insulating layer 13 and may be electrically connected to the first bonding pad 113 through a via hole in the first insulating layer 13.

Fig. 4 is a schematic cross-sectional view of an inductor according to another embodiment of the present application.

In another implementation, as shown in fig. 4, the second conductive layer 12 is disposed on a side of the first conductive layer 11 close to the insulating substrate 30, the insulating substrate 30 includes a first slit, and the second connection line 121 is disposed in the first slit.

In addition, in order to ensure that the first conductive layer 11 has a flat carrying surface, after the second connection lines 121 are prepared in the first notches, the first notches need to be filled with the first insulating layer 13. The peripheral terminal of the first conductive coil 111 and the first bonding pad 113 may be electrically connected to the second connection line 121 through a via hole included in the first insulating layer 13 filled in the first slit.

And the second bonding pad 213 is disposed to be different from the fourth conductive layer 22.

In one implementation, as shown in fig. 1, the fourth conductive layer 22 is disposed on a side of the third conductive layer 21 away from the insulating substrate 30, and the fourth connection line 221 may be electrically connected to the inner peripheral end point of the second conductive coil 211 through a via hole located in the second insulating layer 23 and may be electrically connected to the second bonding pad 213 through a via hole in the second insulating layer 23.

In another implementation, as shown in fig. 4, the fourth conductive layer 22 is disposed on a side of the third conductive layer 21 close to the insulating substrate 30, the insulating substrate 30 includes a second slit, and the fourth connection line 221 is disposed in the second slit.

In addition, in order to ensure that the third conductive layer 21 has a flat carrying surface, after the fourth connection line 221 is prepared in the second notch, the second notch needs to be filled with the second insulating layer 23. The inner peripheral end of the second conductive coil 211 and the second bonding pad 213 may be electrically connected to the fourth connection line 221 through a via hole included in the second insulating layer 24 filled in the second slit.

In one embodiment of the present application, as shown in fig. 1, the second conductive layer 12 is located on a side of the first conductive layer 11 away from the insulating substrate 30, and the fourth conductive layer 22 is located on a side of the third conductive layer 21 away from the insulating substrate. Only the insulating substrate 30 is included between the first conductive coil 111 and the second conductive coil 211, and other signal lines are not included, so that signals between the first conductive coil 111 and the second conductive coil 211 are prevented from being interfered by the other signal lines.

In one embodiment of the present application, as shown in fig. 4, the insulating substrate 30 includes a first slit and the second connection line 121 is disposed in the first slit, the insulating substrate 30 includes a second slit and the fourth connection line 221 is disposed in the second slit. In this embodiment, the inductor has a small thickness, and miniaturization of the inductor is easily achieved.

Fig. 5 is a schematic cross-sectional view of an inductor according to still another embodiment of the present application.

In the embodiment of the present application, as shown in fig. 5, the second conductive layer 12 in the first conductive layer 10 is located on a side of the first conductive layer 11 away from the insulating substrate 30, and the fourth conductive layer 22 in the second conductive layer 20 is located on a side of the third conductive layer 21 close to the insulating substrate 30.

Further, a side of the insulating substrate 30 facing the second inductance layer 20 includes a second slit, and the fourth connection line 221 is disposed in the second slit.

Fig. 6 is a schematic cross-sectional view of an inductor according to still another embodiment of the present application.

In one embodiment of the present application, as shown in fig. 6, the second conductive layer 12 in the first conductive layer 10 is located on a side of the first conductive layer 11 close to the insulating substrate 30, and the fourth conductive layer 22 in the second conductive layer 20 is located on a side of the third conductive layer 21 away from the insulating substrate 30.

Further, a side of the insulating substrate 30 facing the first inductance layer 10 includes a first slit, and the second connection line 121 is disposed in the first slit.

It should be noted that, as shown in fig. 1 to fig. 4 and fig. 6, the sequence of the functional film layers in the first inductance layer 10 along the direction away from the insulating substrate 30 is the same as the sequence of the functional film layers in the second inductance layer 20 along the direction away from the insulating substrate 30, and then the first inductance layer 10 and the second inductance layer 20 can be simultaneously prepared.

In an embodiment of the present application, the insulating substrate 30 is one of glass, ceramic, fiberglass board, and polyimide film, and specifically may be one of alumina ceramic and epoxy fiberglass board.

The insulating substrate 30 may be one of alkali-free glass, aluminosilicate glass, and soda glass, that is, the insulating substrate 30 may be alkali-free glass, aluminosilicate glass, or soda glass. These glasses have advantages such as better chemical stability, electrical insulation, mechanical strength, further guarantee the performance of the inductor that this application embodiment provided. These glasses are dimensionally stable, yet have the ability to fine pitch vias, stability to temperature and humidity, coefficient of Thermal Expansion (CTE) matching to the device, and availability in large areas at low cost.

In an embodiment of the present application, the thickness of the insulating substrate 30 is less than or equal to 0.1mm, for example, the thickness of the insulating substrate 30 is 0.1mm or 0.2mm, and the thickness gives consideration to a good coupling coefficient and a high voltage withstanding performance of the device, and meanwhile, large-area production can be achieved, and the cost is reduced.

In one embodiment of the present application, the material of the first conductive layer 11 is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper, and the material of the second conductive layer 12 is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper; the material of the third conductive layer 21 is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium, and copper, and the material of the fourth conductive layer 22 is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium, and copper.

In a specific embodiment, the materials of the first conductive layer 11, the second conductive layer 12, the third conductive layer 21, and the fourth conductive layer 22 may be the same. The first conductive layer 11, the second conductive layer 12, the third conductive layer 21, and the fourth conductive layer 22 can be prepared in the same film forming apparatus.

In one implementation, the first conductive layer 11, the second conductive layer 12, the third conductive layer 21, and the fourth conductive layer 22 may all be conductive film layers made of a single material.

In one implementation, the first conductive layer 11, the second conductive layer 12, the third conductive layer 21, and the fourth conductive layer 22 may be conductive films made of multiple materials, for example, a composite film made of molybdenum, aluminum, and molybdenum.

In one implementation, a portion of the first conductive layer 11, the second conductive layer 12, the third conductive layer 21, and the fourth conductive layer 22 may be a conductive film layer made of a single material, and another portion may be a conductive film layer made of multiple materials.

In one embodiment of the present application, the thicknesses of the first conductive layer 11 and the third conductive layer 21 are both greater than or equal to 600nm. Since the first conductive layer 11 and the third conductive layer 21 respectively include the first bonding pad 113 and the second bonding pad 213, the inventors have found that, when the thicknesses of the first bonding pad 113 and the second bonding pad 213 in the thickness direction of the inductor are both greater than or equal to 600nm, the first bonding pad 113 and the second bonding pad 213 have excellent bonding characteristics with an external signal line.

Further, the thicknesses of the second conductive layer 12 and the fourth conductive layer 22 may be both 600nm or more.

In one embodiment of the present application, the thickness of the inductor may be about 0.5mm, and the length and width thereof may be about 2mm × 2mm, so that the inductor using the inventive concept of the present application may also have a fine structure.

Fig. 7 is a schematic diagram of a first conductive coil and a second conductive coil in an inductor according to an embodiment of the present application.

In one embodiment of the present application, as shown in FIG. 3 and FIG. 7, the first conductive coil 111 includes N turns of the first conductive wire, where N ≧ 1; and the width of the first conductive line is w1, w1 ≦ 100 μm, e.g., w1 ≦ 30 μm. Wherein, specifically, 20 μm ≧ w1 ≧ 2 μm, for example, w1=5 μm or w1=15 μm. The line width can achieve higher yield and excellent electrical performance.

The second conductive coil 211 comprises M second conductive wires, and M is greater than or equal to 1; and the width of the second conductive line is w2, w2 ≦ 100 μm, e.g., w2 ≦ 30 μm. Specifically, 20 μm.gtoreq.w 2.gtoreq.2 μm, for example, w2=5 μm or w2=15 μm.

Further, N is greater than or equal to 2, that is, the first conductive coil 111 includes a plurality of turns of the first conductive wire; the minimum distance between adjacent first conductive lines is d1, d1 ≦ 100 μm, e.g., d1 ≦ 30 μm. Specifically, 20 μm.gtoreq.d 1.gtoreq.2 μm, for example, d1=5 μm or d1=15 μm.

M is more than or equal to 2, that is, the second conductive coil 211 comprises a plurality of circles of second conductive wires; the minimum distance between adjacent second conductive lines is d2, d2 ≦ 100 μm, e.g., d2 ≦ 30 μm. . Wherein, specifically, 20 μm ≧ d2 ≧ 2 μm, for example, d2=5 μm or d2=15 μm.

In one embodiment of the present application, as shown in fig. 3 and 7, the first conductive coil 111 is a spiral coil including at least one turn of the first conductive wire, and the second conductive coil 211 is a spiral coil including at least one turn of the second conductive wire.

Fig. 8 is a schematic diagram of a first conductive coil in an inductor according to another embodiment of the present application, and fig. 9 is a schematic diagram of a second conductive coil in an inductor according to another embodiment of the present application.

As shown in fig. 8, the first conductive coil 111 includes a first spiral coil 111a and a second spiral coil 111b, and the first spiral coil 111a is connected in parallel with the second spiral coil 111 b. That is, the first conductive coil 111 is formed by connecting at least two parallel spiral coils in parallel.

Further, the first spiral coil 111a includes a plurality of turns of the first conductive line, and the second spiral coil 111b includes a plurality of turns of the first conductive line. In addition, among the plurality of turns of the first conductive line in the first spiral coil 111a, the width of the first conductive line is also w1, and the minimum distance between adjacent first conductive lines is also d1; of the plurality of turns of the first conductive line in the second spiral coil 111b, the width of the first conductive line is also w1, and the minimum distance between adjacent first conductive lines is also d1.

As shown in fig. 9, the second conductive coil 211 comprises a third spiral coil 211a and a fourth spiral coil 211b, and the third spiral coil 211a is connected in parallel with the fourth spiral coil 211 b. That is, the second conductive coil 211 is formed by at least two parallel spiral coils connected in parallel.

Further, the third spiral coil 211a includes a plurality of turns of the first conductive line, and the fourth spiral coil 211b includes a plurality of turns of the second conductive line. In addition, among the plurality of turns of the second conductive line in the third spiral coil 211a, the width of the second conductive line is also w2, and the minimum distance between adjacent second conductive lines is also d2; of the plurality of turns of the second conductive line in the fourth spiral coil 211b, the width of the second conductive line is also w2, and the minimum distance between adjacent second conductive lines is also d2.

In one implementation, at least two of the spiral coils in the first conductive coil 111 are electrically connected at a peripheral end and an inner peripheral end of the first conductive coil 111, respectively.

In one implementation, at least two spiral coils of the second conductive coil 211 are electrically connected at a peripheral end point and an inner peripheral end point of the second conductive coil 211, respectively.

The spiral coils are connected in parallel to form the conductive coil, so that the inductance value is further improved, and the coupling performance is improved.

In one embodiment of the present application, although the first conductive coil 111 includes a first spiral coil 111a and a second spiral coil 111b connected in parallel, and the second conductive coil 211 includes a third spiral coil 211a and a fourth spiral coil 211b connected in parallel, the first connection line 112 and the second connection line 121 respectively electrically connected to the first conductive coil 111 are both of a full-surface structure, and the third connection line 212 and the fourth connection line 221 respectively electrically connected to the second conductive coil 211 are both of a full-surface structure.

That is, a first connecting line 112 designed to be continuous and full-surface is electrically connected to the first spiral coil 111a and the second spiral coil 111b at the same time, and a second connecting line 121 designed to be continuous and full-surface is electrically connected to the first spiral coil 111a and the second spiral coil 111b at the same time; one continuous whole-surface designed third connection line 212 is simultaneously electrically connected to the third spiral coil 211a and the fourth spiral coil 211b, and one continuous whole-surface designed fourth connection line 221 is simultaneously electrically connected to the third spiral coil 211a and the fourth spiral coil 211 b.

Fig. 10 is a schematic cross-sectional view of an inductor according to still another embodiment of the present application.

In one embodiment of the present application, as shown in fig. 1-2, 4-6, only one complete insulating substrate 30 is included between the first inductor layer 10 and the second inductor layer 20. The first inductance layer 10 and the second inductance layer 20 can be formed on both sides of one insulating substrate 30, respectively.

In another embodiment of the present application, as shown in fig. 10, the insulating substrate 30 is between the first inductance layer 10 and the second inductance layer 20, and the insulating substrate 30 includes a first sub-insulating substrate 301 and a second sub-insulating substrate 302. The first inductance layer 10 is prepared on the first sub insulating substrate 301, and the second inductance layer 20 is prepared on the second sub insulating substrate 302, and then the first sub insulating substrate 301 and the second sub insulating substrate 302 are attached together.

As shown in fig. 11, an embodiment of the present application further provides a chip 01, where the chip 01 includes the inductor provided in any of the above embodiments, and the chip 01 may further include other electronic components, such as a resistor, a capacitor, and the like. The chip 01 provided by the embodiment of the present application can be formed by packaging the inductor provided by the embodiment of the present application with other electronic components.

In the embodiment of the application, the preparation process of the inductor is simple and the cost is low, so that the manufacturing difficulty and the cost of the chip can be reduced; in addition, the coupling performance of the inductor is obviously improved compared with the prior art, so that the performance of the chip can be obviously improved.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. An inductor, comprising:

an insulating substrate;

a first inductor layer, the first inductor layer comprising:

the first conducting layer comprises a first conducting coil and a first connecting wire, and the first connecting wire is electrically connected with the peripheral endpoint of the first conducting coil;

the second conducting layer comprises a second connecting wire, and the second connecting wire is electrically connected with the inner periphery endpoint of the first conducting coil;

a first insulating layer disposed between the first conductive layer and the second conductive layer;

a second inductive layer, the second inductive layer comprising:

the third conducting layer comprises a second conducting coil and a third connecting line, and the third connecting line is electrically connected with the peripheral endpoint of the second conducting coil;

the fourth conducting layer comprises a fourth connecting wire, and the fourth connecting wire is electrically connected with the inner periphery endpoint of the second conducting coil;

a second insulating layer disposed between the third conductive layer and the fourth conductive layer;

the first inductance layer and the second inductance layer are respectively arranged on two opposite sides of the insulating substrate.

2. The inductor according to claim 1, wherein the insulating substrate is one of glass, ceramic, fiberglass board, polyimide film.

3. The inductor according to claim 1, wherein a thickness of the insulating substrate is 0.5mm or less.

4. The inductor according to claim 1, wherein the material of the first conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper, and the material of the second conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper;

the third conducting layer is made of at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper, and the fourth conducting layer is made of at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper.

5. The inductor according to claim 1, wherein the first conductive layer and the third conductive layer each have a thickness of 600nm or more.

6. The inductor according to claim 1, wherein the first conductive coil comprises N turns of the first conductive wire, the width of the first conductive wire is less than or equal to 100 μm, and N ≧ 1;

the second conductive coil comprises M circles of second conductive wires, the width of each second conductive wire is less than or equal to 100 micrometers, and M is larger than or equal to 1.

7. The inductor according to claim 6, wherein N ≧ 2, and a minimum distance between adjacent ones of the first conductive lines is 100 μm or less;

m is larger than or equal to 2, and the minimum distance between the adjacent second conductive lines is smaller than or equal to 100 mu M.

8. The inductor according to claim 1 or 6, wherein the first conductive coil comprises a first spiral coil and a second spiral coil, and the first spiral coil is connected with the second spiral coil in parallel;

the second conductive coil comprises a third spiral coil and a fourth spiral coil, and the third spiral coil is connected with the fourth spiral coil in parallel.

9. The inductor as claimed in claim 8, wherein the first connecting line, the second connecting line, the third connecting line and the fourth connecting line are all of a full-surface structure.

10. The inductor according to claim 1, wherein the first conductive layer further comprises first bonding pads, the first connection lines and the second connection lines being electrically connected to different ones of the first bonding pads, respectively;

the third conductive layer further comprises second binding pads, and the third connecting line and the fourth connecting line are electrically connected with the different second binding pads respectively.

11. The inductor according to claim 1, wherein the second conductive layer is disposed on a side of the first conductive layer adjacent to the insulating substrate, the insulating substrate includes a first slit and the second connection line is disposed within the first slit; and/or the presence of a gas in the atmosphere,

the fourth conducting layer is arranged on one side, close to the insulating substrate, of the third conducting layer, the insulating substrate comprises a second notch, and the fourth connecting line is arranged in the second notch.

12. A chip comprising an inductor according to any one of claims 1 to 11.