CN115963710A

CN115963710A - Overlay error correction method and apparatus, electronic device, and storage medium

Info

Publication number: CN115963710A
Application number: CN202310014488.2A
Authority: CN
Inventors: 樊贝贝
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-01-05
Filing date: 2023-01-05
Publication date: 2023-04-14

Abstract

The disclosure relates to an overlay error correction method and device, electronic equipment and a computer readable storage medium, relates to the technical field of semiconductor production and manufacturing, and can be applied to a scene of correcting an overlay error under the condition that an overlay error identifier is damaged. The method comprises the following steps: obtaining a current batch of wafers, and determining a plurality of alignment marks corresponding to the current batch of wafers and alignment errors and alignment error deviations of the alignment marks; determining a mark quality value for each alignment mark based on the overlay error and the overlay error deviation; screening the plurality of alignment marks based on the mark quality values to determine a target alignment mark; and determining an error correction result corresponding to the current batch of wafers based on the target alignment mark, and carrying out exposure alignment processing on the next batch of wafers based on the error correction result. The method and the device can determine the alignment error based on the target alignment mark which is not damaged, thereby effectively controlling the alignment error generated in the process.

Description

Overlay error correction method and apparatus, electronic device, and storage medium

Technical Field

The present disclosure relates to the field of semiconductor manufacturing and manufacturing technologies, and in particular, to an overlay error correction method, an overlay error correction apparatus, an electronic device, and a computer-readable storage medium.

Background

In a semiconductor manufacturing process, the exposed and developed pattern (i.e., the current layer) must be aligned with the existing pattern (i.e., the previous layer) on the wafer substrate to ensure proper connection between the devices. The relative position between the current layer and the previous layer of the exposure pattern is called Overlay error (Overlay), and if the Overlay error is too large, the device will be short-circuited or open-circuited, which affects the yield of the product.

The control and reduction of overlay error is currently achieved by three parts working together, including: aligning operation and exposure of a photoetching machine; measuring the overlay error of the photoresist pattern; the model calculation determines the correctable term and feeds back to the lithography machine.

In the actual process, different overlay errors may be generated at different positions away from the center of the wafer, and the measurement patterns obtained at different positions may have different differences. The overlay error of the wafer during the measurement process is affected by many factors, and the affected overlay error is fed back to the exposure machine, which may cause interference with the exposure behavior of the exposure machine.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The disclosure is directed to an overlay error correction method, an overlay error correction apparatus, an electronic device, and a computer-readable storage medium, so as to overcome at least a problem that an incomplete or damaged pattern identifier may cause an error in a measured overlay error in a wafer manufacturing process, and the measured overlay error is fed back to an exposure machine to affect a yield of a whole wafer.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the invention.

According to a first aspect of the present disclosure, there is provided an overlay error correction method, including: obtaining a current batch of wafers, and determining a plurality of alignment marks corresponding to the current batch of wafers, and an alignment error deviation corresponding to each alignment mark; determining a mark quality value corresponding to each alignment mark based on the overlay error and the overlay error deviation of each alignment mark; screening a plurality of alignment marks based on the determined mark quality values to determine a target alignment mark; and determining an error correction result corresponding to the current batch of wafers based on the target alignment mark, and carrying out exposure alignment processing on the next batch of wafers based on the error correction result.

In an exemplary embodiment of the disclosure, the obtaining the current lot of wafers includes: acquiring an overlay error identifier corresponding to the current batch of wafers; respectively acquiring a reference identification signal and an actual identification signal corresponding to the overlay error identification; determining the mark integrity of the overlay error mark according to the actual mark signal and the reference mark signal; configuring a plurality of graphical selection boxes to determine a plurality of the alignment marks based on a plurality of the graphical selection boxes if the identity integrity is less than an integrity threshold; configuring one of the graphic selection boxes to determine the alignment mark based on the graphic selection box if the identity integrity is greater than or equal to an integrity threshold.

In an exemplary embodiment of the disclosure, the determining a plurality of alignment marks corresponding to the current lot of wafers includes: determining a graph selection position corresponding to the current batch of wafers; acquiring the position number of the graph selection positions, and configuring a corresponding number of graph selection frames according to the position number; and carrying out graphic marking processing on the wafers in the current batch based on the determined graphic selection position and the determined graphic selection frame to obtain a plurality of alignment marks.

In an exemplary embodiment of the present disclosure, the determining the pattern selection position corresponding to the current lot of wafers includes: obtaining the identification type of the overlay error identification of the current batch of wafers; determining a symmetrical center point corresponding to the current batch of wafers; determining at least one figure selection direction corresponding to the current test product based on the symmetrical center point; and determining the graphic selection position corresponding to each graphic selection direction based on the identification type.

In an exemplary embodiment of the present disclosure, the determining, based on the identification type, a graphic selection position corresponding to each graphic selection direction includes: determining the graphic identification characteristics of the wafers in the current batch based on the identification type; determining an inner border graphic selection position in each graphic selection direction based on the graphic identification features; and determining the outer frame graph selection position of the current batch of wafers based on the graph identification features.

In an exemplary embodiment of the present disclosure, the determining a mark quality value for each of the alignment marks includes: determining overlay errors corresponding to the alignment marks; determining an alignment error deviation and an alignment error deviation standard deviation corresponding to each alignment mark based on the alignment errors; determining the mark quality value according to the overlay error, the overlay error deviation and the overlay error deviation standard deviation; the mark quality value

Wherein MQ represents a mark quality value of the alignment mark, OVL represents an overlay error of the alignment mark, qunit represents an overlay error deviation of the alignment mark, and Qunit delta 2 represents an overlay error standard deviation of the alignment mark.

In an exemplary embodiment of the present disclosure, the determining, based on the overlay errors, an overlay error deviation and an overlay error deviation standard deviation corresponding to each of the alignment marks includes: determining an overlay error derivative corresponding to the overlay error; determining the overlay error bias based on the overlay error and the overlay error derivative; determining the standard deviation of overlay error based on the overlay error deviation; the overlay error deviation Qmerit = OVL' -OVL; wherein Qmerit represents an overlay error deviation of the alignment mark, OVL represents an overlay error of the alignment mark, and OVL' represents an overlay error derivative of the alignment mark.

In an exemplary embodiment of the present disclosure, the number of the alignment marks is plural, and the screening of the plural alignment marks based on the determined mark quality value to determine the target alignment mark includes: determining a marker quality average value corresponding to a plurality of said marker quality values; and regarding the alignment mark with the mark quality value smaller than the mark quality average value as the target alignment mark.

In an exemplary embodiment of the present disclosure, the determining an error correction result corresponding to the current lot of wafers based on the target alignment mark includes: determining a target mark signal for the target alignment mark; analyzing and processing the target mark signal, and determining a target central point corresponding to the target alignment mark; determining a target overlay error value corresponding to the target alignment mark based on the target center point; performing analog calculation on the target alignment error value, and determining an alignment error compensation value corresponding to the current batch of wafers; and taking the alignment error compensation value as the error correction result.

In an exemplary embodiment of the present disclosure, the determining a target overlay error value corresponding to the target alignment mark based on the target center point includes: acquiring a pattern alignment direction corresponding to the current test product; the pattern alignment direction comprises a first alignment direction and a second alignment direction; determining a first overlay error value corresponding to the first alignment direction based on the target center point; determining a second registration error value corresponding to the second alignment direction based on the target center point; and generating the target overlay error value according to the first overlay error value and the second overlay error value.

In an exemplary embodiment of the present disclosure, the performing exposure alignment processing on the next batch of wafers based on the error correction result includes: sending the error correction result to exposure alignment equipment; and controlling the exposure alignment equipment to adjust corresponding pattern alignment parameters based on the error correction result so that the exposure alignment equipment performs exposure alignment processing on the next batch of wafers based on the pattern alignment parameters.

According to a second aspect of the present disclosure, there is provided an overlay error correction system comprising: the exposure alignment equipment is used for acquiring the initial current batch of wafers and carrying out exposure alignment processing on the initial current batch of wafers to obtain the current batch of wafers; the mark error measuring equipment is used for determining a specified number of alignment marks based on the alignment error mark integrity of the current batch of wafers and determining the alignment error deviation value corresponding to the current batch of wafers based on the alignment marks; and the computing equipment is used for determining an alignment error compensation value based on the alignment error deviation value and sending the alignment error compensation value to the exposure alignment equipment.

According to a third aspect of the present disclosure, there is provided an overlay error correction apparatus comprising: the alignment mark determining module is used for acquiring a current batch of wafers, determining a plurality of alignment marks corresponding to the current batch of wafers, and an alignment error deviation corresponding to each alignment mark; a mark metric determination module for determining a mark quality value corresponding to each alignment mark based on an alignment error and an alignment error deviation of each alignment mark; the mark screening module is used for screening the plurality of alignment marks based on the determined mark quality values to determine target alignment marks; and the error correction module is used for determining an error correction result corresponding to the current batch of wafers based on the target alignment mark so as to perform exposure alignment processing on the next batch of wafers based on the error correction result.

In an exemplary embodiment of the disclosure, the overlay error correction apparatus further includes a pattern library configuration module, configured to: acquiring an overlay error identifier corresponding to the current batch of wafers; respectively acquiring a reference identification signal and an actual identification signal corresponding to the overlay error identification; determining the mark integrity of the overlay error mark according to the actual mark signal and the reference mark signal; configuring a plurality of graphical selection boxes to determine a plurality of the alignment marks based on a plurality of the graphical selection boxes if the identity integrity is less than an integrity threshold; configuring one of the graphic selection boxes to determine the alignment mark based on the graphic selection box if the identity integrity is greater than or equal to an integrity threshold.

In an exemplary embodiment of the present disclosure, the number of the alignment marks is plural, and the alignment mark determination module includes a test flag determination unit configured to: determining a graph selection position corresponding to the current batch of wafers; acquiring the position number of the figure selection positions, and configuring a corresponding number of figure selection frames according to the position number; and carrying out graphic marking processing on the wafers in the current batch based on the determined graphic selection position and the determined graphic selection frame to obtain a plurality of alignment marks.

In an exemplary embodiment of the disclosure, the test identity determination unit comprises a graphical position determination unit for: obtaining the identification type of the overlay error identification of the current batch of wafers; determining a symmetrical center point corresponding to the current batch of wafers; determining at least one figure selection direction corresponding to the current test product based on the symmetrical center point; and determining the graphic selection position corresponding to each graphic selection direction based on the identification type.

In an exemplary embodiment of the disclosure, the graphic position determination unit includes a graphic position determination subunit to: determining the graphic identification characteristics of the wafers of the current batch based on the identification type; determining an inner border graphic selection position in each graphic selection direction based on the graphic identification features; and determining the outer frame graph selection position of the current batch of wafers based on the graph identification features.

In an exemplary embodiment of the disclosure, the marker metric value determination module comprises an identification metric value determination unit for: determining overlay errors corresponding to the alignment marks; determining an overlay error deviation and an overlay error deviation standard deviation corresponding to each alignment mark based on the overlay errors; determining the mark quality value according to the overlay error, the overlay error deviation and the overlay error deviation standard deviation; the mark quality value

Wherein MQ represents the alignment markThe mark quality value, OVL represents the overlay error of the alignment mark, qmerit represents the overlay error deviation of the alignment mark, and Qmerit delta 2 represents the overlay error standard deviation of the alignment mark.

In an exemplary embodiment of the disclosure, the identification metric value determining unit comprises an overlay error parameter determining subunit configured to: determining an overlay error derivative corresponding to the overlay error; determining the overlay error bias based on the overlay error and the overlay error derivative; determining the standard deviation of the overlay error based on the overlay error deviation; the overlay error deviation Qmerit = OVL' -OVL; wherein Qmerit represents an overlay error deviation of the alignment mark, OVL represents an overlay error of the alignment mark, and OVL' represents an overlay error derivative of the alignment mark.

In an exemplary embodiment of the present disclosure, the number of the alignment marks is plural, and the mark sorting module includes an identification sorting unit to: determining a marker quality average value corresponding to a plurality of said marker quality values; and regarding the alignment mark with the mark quality value smaller than the mark quality average value as the target alignment mark.

In an exemplary embodiment of the disclosure, the error correction module comprises an error correction unit for: determining a target mark signal for the target alignment mark; analyzing and processing the target mark signal, and determining a target central point corresponding to the target alignment mark; determining a target overlay error value corresponding to the target alignment mark based on the target center point; performing analog calculation on the target overlay error value, and determining an overlay error compensation value corresponding to the current batch of wafers; and taking the overlay error compensation value as the error correction result.

In an exemplary embodiment of the disclosure, the error correction unit includes an error correction subunit for: acquiring a pattern alignment direction corresponding to the current test product; the pattern alignment direction comprises a first alignment direction and a second alignment direction; determining a first overlay error value corresponding to the first alignment direction based on the target center point; determining a second alignment error value corresponding to the second alignment direction based on the target central point; and generating the target overlay error value according to the first overlay error value and the second overlay error value.

In an exemplary embodiment of the present disclosure, the overlay error correction apparatus includes a correction result feedback module configured to: sending the error correction result to exposure alignment equipment; and controlling the exposure alignment equipment to adjust corresponding pattern alignment parameters based on the error correction result so that the exposure alignment equipment performs exposure alignment processing on the next batch of wafers based on the pattern alignment parameters.

According to a fourth aspect of the present disclosure, there is provided an electronic device comprising: a processor; and a memory having computer readable instructions stored thereon which, when executed by the processor, implement the overlay error correction method according to any one of the above.

According to a fifth aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements an overlay error correction method according to any one of the above.

The technical scheme provided by the disclosure can comprise the following beneficial effects:

in the overlay error correction method in the exemplary embodiment of the present disclosure, on one hand, the overlay error is calculated based on the target alignment marks obtained by screening a plurality of mark quality values, and the problem that the overlay error accuracy is affected due to the fact that the alignment marks are damaged can be reduced. On the other hand, the error correction result obtained by calculation based on the target alignment mark is used for exposure alignment treatment of the next batch of wafers, so that the product yield can be effectively improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty. In the drawings:

FIG. 1 schematically illustrates a flow chart of an overlay error correction method according to an exemplary embodiment of the present disclosure;

fig. 2 schematically shows a schematic view of graphical identifiers corresponding to different identifier types according to an exemplary embodiment of the present disclosure;

FIG. 3 schematically illustrates a diagram of determining a graphical selection box based on a current test product according to an exemplary embodiment of the present disclosure;

FIG. 4 schematically illustrates a resulting graph of the various order derivatives of overlay error, according to an exemplary embodiment of the present disclosure;

FIG. 5 schematically illustrates a schematic diagram of determining a target alignment mark from a plurality of alignment marks according to an exemplary embodiment of the present disclosure;

FIG. 6 schematically illustrates a graph of overlay error versus overlay error deviation figure of merit after identity screening, according to an exemplary embodiment of the present disclosure;

FIG. 7 schematically illustrates a diagram for determining an overlay error deviation value based on a target alignment mark according to an exemplary embodiment of the present disclosure;

FIG. 8 schematically illustrates a schematic diagram of an overlay error correction system, according to an exemplary embodiment of the present disclosure;

FIG. 9 schematically illustrates a block diagram of an overlay error correction apparatus according to an exemplary embodiment of the present disclosure;

FIG. 10 schematically illustrates a block diagram of an electronic device according to an exemplary embodiment of the present disclosure;

fig. 11 schematically illustrates a schematic diagram of a computer-readable storage medium according to an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in the form of software, or in one or more software-hardened modules, or in different networks and/or processor devices and/or microcontroller devices.

Overlay errors of a wafer in a measurement process may be affected by many factors, for example, instability in a photolithography process, and signal interference exists in a measurement target pattern (IMAGE) acquired by a measurement machine, so that the affected overlay errors are fed back to an exposure machine, thereby interfering with exposure behavior of the exposure machine.

The edge portion of the wafer may often have incomplete IMAGE or damaged IMAGE, for example, in the actual measurement process, the IMAGE with overlay error is damaged due to the process influence, and the IMAGE interval with overlay error is damaged. Due to the occurrence of damaged IMAGE, the measured set quantity error may be wrong, and then the set quantity error is fed back to the exposure machine, which causes the exposure machine to generate a wrong behavior direction, thereby affecting the yield of the whole wafer.

Based on this, the present disclosure provides an overlay error correction method, an overlay error correction system, an overlay error correction apparatus, an electronic device, and a computer-readable storage medium.

It should be noted that the term referred to in the present disclosure, including the Region of Interest (ROI), may be a Region that needs to be processed and is delineated from the processed image in the form of a box, a circle, an ellipse, an irregular polygon, and the like in the machine vision and the image processing, and is referred to as a Region of Interest.

In the present exemplary embodiment, first, an overlay error correction method is provided, which may be implemented by using a server, or a terminal device, where the terminal described in the present disclosure may include a mobile terminal such as a mobile phone, a tablet computer, a notebook computer, a palm top computer, a Personal Digital Assistant (PDA), and a fixed terminal such as a desktop computer. Fig. 1 schematically illustrates a schematic diagram of a process flow of an overlay error correction method, according to some embodiments of the present disclosure. Referring to fig. 1, the overlay error correction method may include the steps of:

step S110 is to obtain a current batch of wafers, determine a plurality of alignment marks corresponding to the current batch of wafers, and determine overlay errors and overlay error deviations corresponding to the alignment marks.

According to some example embodiments of the present disclosure, the current lot of wafers may be wafer products currently undergoing exposure alignment processing. The alignment marks (marks) may be marks determined based on an alignment pattern on the substrate in the current lot of wafers, and the alignment marks (marks) are used to determine overlay errors of the current lot of wafers. Overlay error (OVL) may be an alignment deviation of relative positions between a current layer pattern and a previous layer pattern in a current lot of wafers. The overlay error deviation (Qmerit) may be a parameter for measuring the quality of the overlay error of the alignment mark.

In the integrated circuit manufacturing process, the relative position between the current layer (photoresist pattern) and the reference layer (pattern in the substrate) on the wafer is a key indicator for monitoring the quality of the photolithography process. In the photolithography process, the products to be processed may arrive at the photolithography machines in batches, so that the photolithography machines perform alignment and exposure processing on the currently arrived products to be processed, and a certain batch of wafers currently arriving at the photolithography machine equipment may be referred to as a current batch of wafers. After the current batch of wafers are obtained, because the overlay error corresponding to the current batch of wafers needs to be determined, a plurality of alignment marks (marks) can be determined from a measurement target pattern (IMAGE) corresponding to the current batch of wafers, and the overlay error is measured based on the determined plurality of alignment marks (marks).

For example, in determining the alignment marks, a plurality of alignment marks (marks) may be selected from a metrology target pattern (IMAGE) of a current lot of wafers using a Region of Interest (ROI) box based on the ROI box.

Step S120, determining a mark quality value corresponding to each alignment mark based on the overlay error and the overlay error deviation of each alignment mark.

According to some exemplary embodiments of the present disclosure, the mark quality value may be a quality of an ROI box for framing an alignment mark, and the mark quality value may be expressed as (mark quality, MQ).

After the plurality of alignment marks are determined, in order to determine the quality of the alignment mark selected by each ROI box, a mark quality value corresponding to each alignment mark can be determined; specifically, the mark quality value of each alignment mark may be determined based on an alignment error corresponding to each alignment mark and an alignment error deviation, where the alignment error deviation may be a parameter for measuring whether the quality of the alignment mark is good or bad.

Step S130, screening a plurality of alignment marks based on the determined mark quality values, and determining a target alignment mark.

According to some exemplary embodiments of the present disclosure, the target alignment mark (robust IMAGE) may be an alignment mark that meets a certain condition screened from alignment marks based on a mark quality value, for example, the target alignment mark may be an alignment mark having a mark quality value smaller than an average value of all mark quality values.

After the mark quality values corresponding to all the alignment marks are determined, a plurality of alignment marks can be screened based on the mark quality values, and the target alignment marks meeting specific conditions are screened. For example, an average value corresponding to all mark quality values may be determined, alignment marks having mark quality values greater than the average value may be filtered out, and the remaining alignment marks may be left as target alignment marks. In addition, the target alignment mark meeting the specific condition can be obtained by screening in other screening modes according to the magnitude relation among the multiple mark quality values.

Step S140, determining an error correction result corresponding to the current batch of wafers based on the target alignment mark, and performing exposure alignment processing on the next batch of wafers based on the error correction result.

According to some exemplary embodiments of the present disclosure, the error correction result may be a compensation value of an overlay error of the current lot of wafers determined based on the target alignment mark. The next batch of wafers may be the product to be processed which is sent to the exposure alignment apparatus for the next exposure alignment process. The exposure alignment process may be a process in which an exposure alignment apparatus (e.g., a photolithography machine) performs an alignment operation and an exposure operation on a product.

After the target alignment mark is determined, the offset of the overlay error of the current batch of wafers can be determined based on the target alignment mark, and an error correction result, namely an overlay error compensation value, is determined according to the offset of the overlay error. After the error correction result is obtained, the error correction result can be fed back to the lithography machine, so that the lithography machine can perform exposure alignment processing on the wafers of the next batch based on the error correction result.

According to the overlay error correction method in the present exemplary embodiment, on one hand, the overlay error is calculated based on the target alignment marks obtained by screening a plurality of mark quality values, and the problem that the accuracy of the overlay error is affected due to the fact that the alignment marks are damaged can be reduced. On the other hand, the error correction result obtained by calculation based on the target alignment mark is used for exposure alignment treatment of the next batch of wafers, so that the product yield can be effectively improved.

Next, the overlay error correction method in the present exemplary embodiment will be further described.

In an exemplary embodiment of the present disclosure, an overlay error identifier corresponding to a current batch of wafers is obtained; respectively acquiring a reference identification signal and an actual identification signal corresponding to the overlay error identification; determining the mark integrity of the overlay error mark according to the actual mark signal and the reference mark signal; configuring a plurality of graphic selection boxes to determine a plurality of alignment marks based on the plurality of graphic selection boxes if the identification integrity is less than the integrity threshold; if the identity integrity is greater than or equal to the integrity threshold, a graphic selection box is configured to determine the alignment mark based on the graphic selection box.

The overlay error identifier may be a graphic identifier used for calculating an overlay error in a current test product. The reference mark signal may be an ideal state signal reflecting the mark integrity of the overlay error mark. The actual identification signal may be an actual status signal reflecting the identification integrity of the overlay error identification. The mark integrity may be a parameter value that identifies whether the overlay error mark is damaged or not and still in an intact state. The integrity threshold may be a pre-configured data value for comparison calculations with the identification integrity. The graphic selection box may be a graphic box for framing the alignment marks.

Before determining the alignment mark corresponding to the current batch of wafers, the mark integrity of the overlay mark corresponding to the current batch of wafers may be determined. The specific treatment steps are as follows: acquiring overlay error identifications corresponding to the wafers in the current batch, and after acquiring the overlay error identifications, respectively acquiring reference identification signals and actual identification signals corresponding to the overlay error identifications; the reference identification signal may be an identification signal of the overlay error identifier in an ideal state, and the actual identification signal may be an identification signal actually corresponding to the overlay error identifier.

After the reference identification signal and the actual identification signal are determined, the two signals can be compared, the similarity between the two signals is determined, and the identification integrity corresponding to the overlay error identification is obtained. And comparing the determined mark integrity with an integrity threshold, if the mark integrity is less than the integrity threshold, determining that the overlay error mark is possibly damaged in the process, configuring a plurality of graphic selection frames (ROI frames), and determining a plurality of alignment marks according to the configured plurality of graphic selection frames.

If the mark integrity is greater than or equal to the integrity threshold, the overlay error mark is considered not damaged in the manufacturing process and has a completeness that meets the threshold, and at this time, the overlay error measurement can be directly performed based on the overlay error mark, so that in this case, only one pattern selection frame can be configured, and the alignment mark can be determined based on the pattern selection frame. By determining the mark integrity of the overlay error mark, the number of the graphic selection frames required to be configured can be determined according to the specific numerical value of the integrity, so that the corresponding alignment marks can be selected according to the graphic selection frames with the corresponding number.

In an exemplary embodiment of the present disclosure, for step S110, determining a plurality of alignment marks corresponding to the current lot of wafers may be performed by: determining a graph selection position corresponding to the current batch of wafers; acquiring the position number of the figure selection positions, and configuring a corresponding number of figure selection frames according to the position number; and carrying out graphic marking processing on the wafers in the current batch based on the determined graphic selection position and the determined graphic selection frame to obtain a plurality of alignment marks.

Wherein the pattern selection location may be a specific location for framing the alignment mark in the current test product. The number of locations may be a specific number of graphic selection locations. The graphic marking process may be a process of framing the alignment marks in the current test product.

When the mark integrity of the overlay error mark is less than the preset integrity, a plurality of graphic selection frames can be configured to frame the alignment mark. Before determining the alignment mark, a pattern selection position may be determined in the current lot of wafers according to requirements, for example, a pattern selection position corresponding to the current lot of wafers is determined according to a product pattern distribution characteristic of the current lot of wafers. After the pattern selection locations are determined, a specific number of pattern selection locations, i.e., the number of locations, is obtained, for example, the number of locations in a current lot of wafers may be 8, 10, 25, etc.

After the number of positions is obtained, the corresponding graphic selection frames may be configured according to the number of positions, that is, one graphic selection frame may be configured at one graphic selection position, for example, the shape of the graphic selection frame may be a rectangle.

After the configuration of the graph selection frame is completed, the graph selection frame may be used to perform graph marking processing at the graph selection position on the current batch of wafers, the graph selection frame frames out a plurality of rectangular regions at the corresponding graph selection position, and a graph signal framed by the rectangular regions in the ROI frame is used as an alignment mark, for example, a gray-scale signal framed in the ROI frame is used as the alignment mark. After determining the plurality of alignment marks, the alignment mark selected by the frame may be used as a data basis for measuring overlay errors of the wafers of the current batch, so as to obtain a corresponding measurement result.

In an exemplary embodiment of the present disclosure, determining a pattern selection position corresponding to a current lot of wafers is performed by: obtaining the identification type of the overlay error identification of the current batch of wafers; determining a symmetrical center point corresponding to the wafers in the current batch; determining at least one figure selection direction corresponding to the current test product based on the symmetrical center point; and determining a graphic selection position corresponding to each graphic selection direction based on the identification type.

The mark type may be a specific type of overlay error mark. The symmetry center point may be a center point corresponding to the current test product. The pattern selection direction may be a specific direction for selecting the alignment mark in the exposure pattern for the current test product.

Before determining the graph selection position in the current batch of wafers, determining the identification type of the overlay error identification of the current batch of wafers; for example, referring to fig. 2, fig. 2 schematically illustrates a schematic diagram of graphical identifiers corresponding to different identifier types according to an exemplary embodiment of the present disclosure. The identification type may include a marker Box nesting (Box in Box) identification, an Advanced Image Metric (AIM) identification, and the like. As shown in fig. 2, box in fig. 2 (a) identifies that the identification type is presented in a rectangular graphic shape, and the Box in Box identifies that the rectangular Box contains an alignment mark rectangular Box with a large periphery and an alignment mark rectangular Box with a small inner circle; AIM in fig. 2 (b), the mark type is presented in a raised bar shape; the AIM marker includes an inner alignment mark immediately adjacent to both the horizontal axis and the vertical axis and an outer alignment mark outside the inner alignment mark.

After the identification type corresponding to the wafer of the current batch is determined, a symmetric center point corresponding to the graphic identification can be further determined based on the identification type, for example, the symmetric center point of the Box in Box identification can be at the center position of the rectangular identification; the center of symmetry of the AIM marker may be centered on the bar graph marker of the plurality of different regions. After the center point of symmetry of the graphic identifier is determined, one or more graphic selection directions corresponding to the current test product may be determined based on the center point of symmetry.

After the pattern selection direction is determined, a pattern selection position corresponding to each pattern selection direction in the current batch of wafers can be determined based on the pattern features corresponding to the identification types, that is, the position of each raised bar-shaped pattern in each pattern selection direction is used as a pattern selection position, so that the alignment mark can be determined according to the pattern selection position in the subsequent process. And determining the identification graphic characteristics according to the identification types, and determining the graphic selection position of the frame selection alignment mark according to the identification graphic characteristics.

In an exemplary embodiment of the present disclosure, determining a graphic selection position corresponding to each graphic selection direction based on the identification type includes: determining the graphic identification characteristics of the wafers in the current batch based on the identification type; determining an inner border diagram selection position in each diagram selection direction based on the diagram identification features; and determining the outer frame graph selection position of the wafers in the current batch based on the graph identification characteristics.

The pattern identifier feature may be a specific feature corresponding to the pattern identifier of the current lot of wafers. The inner border graphic selection location may be a graphic selection location for determining a current layer graphic identification. The outer border graphic selection location may be a graphic selection location for determining a front layer graphic identification.

After the identification type corresponding to the current batch of wafers is determined, the graphic selection position in each graphic selection direction in the current batch of wafers can be determined based on the identification type. Continuing to refer to fig. 2, for Box in Box identification, the graphic identification feature of the overlay error identification is to display in a rectangular shape, with the center point of the rectangular graphic as the reference, the position of the outer frame graphic is taken as the outer frame graphic selection position, and the position of the inner frame graphic is taken as the inner frame graphic selection position. The deviation between the graphic center point of the outer frame graphic and the graphic center point of the inner frame graphic is an overlay error.

For the AIM mark, a coordinate system can be established by taking a symmetric central point as a coordinate origin, a horizontal axis as an X axis and a vertical axis as a Y axis, one three quadrants in the coordinate system are taken as a graph selection direction, and two four quadrants in the coordinate system are taken as another graph selection direction. In the first graph selection direction, the identification graph close to the X axis is used as an inner frame, and the graph selection position is determined according to the graph identification feature of the identification graph close to the X axis; similarly, for the second graphic selection direction, the identification graphic close to the Y axis is used as an inner frame, and the graphic selection position is determined according to the graphic identification feature of the identification graphic close to the Y axis.

For the outer border of the AIM identifier, for the first graphic selection direction and the second graphic selection direction, the graphic adjacent to the inner border graphic can be used as the outer border graphic, and the outer border graphic selection position is determined on the outer border graphic. After a plurality of pattern selection locations are determined, a pattern selection box (ROI box) may be configured for each pattern selection location, and referring to fig. 3, fig. 3 schematically illustrates a schematic diagram of determining a pattern selection box based on a current test product according to an exemplary embodiment of the present disclosure. Fig. 3 may include 3 pattern selection boxes, and multiple ROI boxes are configured for mark selection to select a better quality IMAGE, so as to eliminate the influence of the damaged IMAGE in the middle of the process on the measurement overlay error.

In an exemplary embodiment of the present disclosure, determining an indicia quality value corresponding to each alignment indicia comprises: determining overlay errors corresponding to the alignment marks; determining the overlay error deviation and the standard deviation of the overlay error deviation corresponding to each alignment mark based on the overlay error; determining a mark quality value according to the overlay error, the overlay error deviation and the overlay error deviation standard deviation; mark quality value

Wherein, MQ represents the mark quality value of the alignment mark, OVL represents the overlay error of the alignment mark, qmerit represents the overlay error deviation of the alignment mark, and Qmerit delta 2 represents the overlay error standard deviation of the alignment mark.

Wherein, the standard deviation of the overlay error can be a parameter value used for measuring whether the identification quality is stable or not.

After determining the plurality of alignment marks corresponding to the current batch of wafers, an overlay error corresponding to each alignment mark may be determined, and specifically, the overlay error of each alignment mark may be represented by an OVL. When the overlay error corresponding to the alignment mark is calculated, the frame-selected gray scale signal in the inner frame corresponding to the alignment mark and the corresponding frame-selected gray scale signal of the outer frame can be determined, the overlay deviations corresponding to the two gray scale signals relative to the X axis and the Y axis are respectively determined, and the overlay error corresponding to the alignment mark is determined based on the overlay deviations corresponding to the X axis and the Y axis.

After the overlay error of each alignment mark is determined, determining an overlay error deviation and an overlay error deviation standard deviation corresponding to each alignment mark based on the determined overlay error, wherein the overlay error deviation can reflect the quality of the alignment mark (mark), and the overlay error deviation can be expressed by Qmerit; the standard deviation of overlay error, which may be expressed as Qmerit δ 2, may reflect the stability of the alignment mark (mark).

After the data is determined, a mark quality value (MQ) may be determined according to the overlay error, the overlay error deviation, and the overlay error deviation standard deviation corresponding to each alignment mark, as shown in equation 1.

Where MQ may represent the mark quality value of the alignment mark, OVL may represent the overlay error of the alignment mark, qmerit may be the overlay error deviation of the alignment mark, qmerit δ 2 may be the overlay error standard deviation of the alignment mark, and the overlay error standard deviation may be obtained using a standard deviation calculation formula.

According to the determined mark quality value, the quality of the alignment mark determined by each ROI frame can be determined, and whether the alignment mark is damaged in the process is judged.

In an exemplary embodiment of the present disclosure, determining the overlay error deviation and the standard deviation of the overlay error deviation corresponding to each alignment mark based on the overlay error may be performed by: determining an overlay error derivative corresponding to the overlay error; determining an overlay error deviation based on the overlay error and an overlay error derivative; determining an overlay error deviation standard deviation based on the overlay error deviation; overlay error deviation Qmerit = OVL' -OVL; where Qmerit represents the overlay error deviation of the alignment mark, OVL represents the overlay error of the alignment mark, and OVL' represents the overlay error derivative of the alignment mark.

The derivative of the overlay error may be a derivative of each order corresponding to the overlay error, for example, the derivative of the overlay error may be a derivative of a first order corresponding to the overlay error.

After determining the overlay error corresponding to each alignment mark, an overlay error derivative corresponding to each alignment mark may be determined based on the overlay error, for example, first order derivatives, second order derivatives, and other order derivatives of the overlay error corresponding to the alignment mark may be determined. Referring to fig. 4, fig. 4 schematically illustrates a resultant plot of the derivative of each order of overlay error according to an exemplary embodiment of the present disclosure. As can be seen from fig. 4, after calculating the respective order derivatives for the overlay errors, the difference between the ideal state and the actual state of the overlay error corresponding to the respective order derivatives is obtained.

Based on the difference result of each order derivative of the overlay error, the first derivative of the overlay error can be used as a data basis for calculating the overlay error deviation, and after the overlay error derivative is determined, the overlay error deviation can be determined based on the overlay error and the overlay error derivative. Specifically, the calculation method of the overlay error deviation is shown in formula 2.

Qmerit = OVL' -OVL (equation 2)

Where qmeritt may represent an overlay error deviation of the alignment mark, OVL may represent an overlay error of the alignment mark, and OVL' may represent an overlay error derivative of the alignment mark.

After the overlay error deviation is determined, an overlay error deviation standard deviation may be determined based on the overlay error deviation, and the determined overlay error deviation and the overlay error deviation standard deviation may be used as a data basis for calculating the mark quality value.

In an exemplary embodiment of the present disclosure, for step S130, screening a plurality of alignment marks based on the determined mark quality values to determine a target alignment mark, includes: determining a marker quality average value corresponding to a plurality of marker quality values; and taking the alignment mark with the mark quality value smaller than the mark quality average value as a target alignment mark.

The mark quality average value may be a value obtained by averaging mark quality values corresponding to a plurality of alignment marks.

After the mark quality values corresponding to all the alignment marks are determined, the alignment marks can be screened according to the mark quality values obtained through calculation, and the target alignment marks are obtained. For example, a mean value calculation process may be performed on all calculated marker quality values to obtain a marker quality mean value. For the mark quality value, the smaller the mark quality value, the better the quality of the alignment mark. After the mark quality average value is obtained, the alignment marks with the mark quality value larger than or equal to the mark quality average value, namely, the IMAGE with low quality can be filtered, and the alignment marks with the mark quality value smaller than the mark quality average value are screened out to be used as target alignment marks.

Referring to fig. 5, fig. 5 schematically illustrates a schematic diagram of determining a target alignment mark from a plurality of alignment marks according to an exemplary embodiment of the present disclosure. As can be seen from fig. 5, after the mark screening process, the target alignment marks numbered 1 to 4 are obtained, and fig. 5 shows the graphic marks selected by the ROI boxes corresponding to numbers 3 and 4 and the graphic marks selected by the outline boxes.

In addition, the median of the mark quality values of the multiple alignment marks can be determined and used as the median of the quality values, the alignment mark with the mark quality value smaller than the median of the quality values is used as the target alignment mark, so that overlay error statistics corresponding to the current batch of wafers can be carried out based on the determined target alignment mark, and more accurate measurement data can be obtained.

Referring to fig. 6, fig. 6 schematically illustrates a graph of overlay error versus overlay error deviation figure of merit after identification screening according to an exemplary embodiment of the present disclosure. Fig. 6 illustrates an overlay error (OVX) of the wafer of the current lot IN the X coordinate axis direction as an example, and shows a data variation relationship between the overlay error (OVX) of the wafer of the current lot IN the X coordinate axis direction and an overlay error deviation (QMERIT _ IN _ OVX) of the wafer of the current lot IN the X coordinate axis direction. As can be seen from fig. 6, in the related scheme, the overlay error and the overlay error deviation are calculated based on the overlay error marks of the current batch of wafers, and since there may be cases where the overlay error marks themselves are damaged or the spacing is damaged, the calculated overlay error deviation and the variation trend of the overlay error have a deviation. By adopting the processing mode of the scheme, after the mark quality values of the plurality of alignment marks are calculated, the target alignment mark with the mark quality value meeting the specific condition is selected from the plurality of alignment marks. The mark quality value of the target alignment mark obtained by screening meets a specific condition, so that the quality is high, the data change trend of the overlay error deviation calculated based on the target alignment mark is closer to the change of the overlay error, and the data change is stable.

In an exemplary embodiment of the present disclosure, for step S140, determining an error correction result corresponding to the current lot of wafers based on the target alignment mark includes: determining a target mark signal of a target alignment mark; analyzing and processing the target mark signal, and determining a target central point corresponding to the target alignment mark; determining a target overlay error value corresponding to the target alignment mark based on the target central point; performing analog calculation on the target overlay error value, and determining an overlay error compensation value corresponding to the current batch of wafers; and taking the alignment error compensation value as an error correction result.

The target mark signal may be a signal representation corresponding to the target alignment mark, for example, the target mark signal may be a gray scale signal of the target alignment mark. The target center point may be a center location point determined based on the target alignment marks. The target overlay error value may be an overlay error value determined based on the target alignment mark. The overlay error compensation value may be an overlay error offset value determined to correct the target overlay error value.

After the target alignment mark (robust IMAGE) is determined, a target mark signal corresponding to the target alignment mark, that is, a gray scale signal of the target alignment mark (robust IMAGE) can be obtained, wherein the gray scale signal is obtained by dividing the brightness change between the brightest brightness and the darkest brightness into a plurality of parts. After a gray scale signal of a target alignment mark (robust IMAGE) is obtained, analyzing the obtained target mark signal, and determining a target center point corresponding to the target alignment mark according to a signal analysis result. Referring to fig. 7, fig. 7 schematically illustrates a schematic diagram of determining an overlay error deviation value based on a target alignment mark according to an exemplary embodiment of the present disclosure. As shown in fig. 7, after performing signal analysis processing on the gray scale signal of the target alignment mark, a target center point corresponding to the gray scale signal can be determined.

After the target center point is determined, a target overlay error value corresponding to the target alignment mark may be determined based on the target center point. Specifically, the target overlay error value may be calculated based on the pattern alignment direction corresponding to the current test product. When the target overlay error value of the current batch of wafers is determined, the target overlay error value can be transmitted to a calculation center, the calculation center performs simulation calculation on the target overlay error value, and an overlay error compensation value corresponding to the current batch of wafers is determined; and taking the overlay error compensation value as an error correction result so as to use the error correction result in the exposure alignment processing process of the next batch of wafers.

In an exemplary embodiment of the present disclosure, determining a target overlay error value corresponding to a target alignment mark based on a target center point includes: acquiring a pattern alignment direction corresponding to a current test product; the pattern alignment direction comprises a first alignment direction and a second alignment direction; determining a first registration error value corresponding to the first alignment direction based on the target center point; determining a second registration error value corresponding to the second alignment direction based on the target center point; and generating a target overlay error value according to the first overlay error value and the second overlay error value.

Wherein the pattern alignment direction may be a specific direction for performing pattern alignment. The first alignment direction may be an alignment direction along a first coordinate axis determined based on the target center point. The second alignment direction may be an alignment direction along a second coordinate axis determined based on the target center point. The first overlay error value may be an overlay error value determined based on the first pattern alignment direction. The second overlay error value may be an overlay error value determined based on the second pattern alignment direction.

After the target alignment mark is determined, the pattern alignment direction corresponding to the current test product can be obtained, and for the current batch of wafers, two pattern alignment directions such as a first alignment direction and a second alignment direction can be determined based on the determined target center point; the first alignment direction may be a pattern alignment direction corresponding to an X axis, and the second alignment direction may be a pattern alignment direction corresponding to a Y axis.

For the current batch of wafers, a first overlay error value corresponding to the first alignment direction may be determined based on the target center point. Continuing with fig. 7, after performing signal analysis processing on the gray scale signals corresponding to the inner frame and the outer frame of the target alignment mark, a target center point corresponding to the inner frame and a target center point corresponding to the outer frame may be determined, respectively, and a difference value between the target center point corresponding to the inner frame and the target center point corresponding to the outer frame is an overlay error value of the current batch of wafers in the first alignment direction (X axis), as shown by Δ X in fig. 7, that is, a first overlay error value (overlay error value in the X axis direction). Similarly, a second overlay error value (an overlay error value in the Y-axis direction) corresponding to the second alignment direction may be determined based on the target center point, and is represented by Δ Y.

After determining the first overlay error value Δ x and the second overlay error value Δ y corresponding to the first alignment direction and the second alignment direction, respectively, a target overlay error value may be generated according to the first overlay error value Δ x and the second overlay error value Δ y, so as to determine an overlay error compensation value corresponding to a next batch of wafers based on the obtained target overlay error value. Specifically, the overlay error calculation simulation and the data analysis are carried out on the data corresponding to the gray-scale signal by calculating the gray-scale signal of the selected ROI to obtain an overlay error compensation value which is used as an error correction result so as to carry out compensation processing during wafer exposure based on the error correction result, and therefore the product yield is improved.

In an exemplary embodiment of the present disclosure, for step S140, performing exposure alignment processing on the next batch of wafers based on the error correction result includes: sending the error correction result to exposure alignment equipment; and controlling the exposure alignment equipment to adjust the corresponding pattern alignment parameters based on the error correction result so that the exposure alignment equipment performs exposure alignment processing on the wafers of the next batch based on the pattern alignment parameters.

The exposure alignment device may be an operation device for performing alignment processing and exposure processing on a product to be processed. The pattern alignment parameter may be a specific parameter for guiding an alignment process of the current layer pattern with the previous layer pattern.

After the error correction result is obtained, the error correction result can be fed back to the exposure alignment equipment, and after the exposure alignment equipment receives the error correction result, the system can control the exposure alignment equipment to adjust the corresponding graphic alignment parameters based on the error correction result. After the adjustment operation of the pattern alignment parameters is completed, the exposure alignment equipment can perform exposure alignment processing on the next batch of wafers based on the adjusted pattern alignment parameters, so that the product yield is improved.

It should be noted that the terms "first" and "second" are used in this disclosure only for distinguishing different alignment directions of patterns from different overlay errors, and should not limit the disclosure in any way.

In summary, the overlay error correction method of the present disclosure obtains the current batch of wafers, and determines a plurality of alignment marks corresponding to the current batch of wafers; determining a mark quality value for each alignment mark; the mark quality value is determined based on the overlay error and the overlay error deviation of each alignment mark; screening the plurality of alignment marks based on the determined mark quality values to determine a target alignment mark; and determining an error correction result corresponding to the current batch of wafers based on the target alignment mark, and carrying out exposure alignment processing on the next batch of wafers based on the error correction result. On one hand, the overlay error is calculated based on the target alignment marks obtained by screening the quality values of the plurality of marks, so that the problem that the accuracy rate of the overlay error is influenced due to the fact that the alignment marks are damaged can be solved. On the other hand, the error correction result obtained by calculation based on the target alignment mark is used for exposure alignment treatment of the next batch of wafers, so that the product yield can be effectively improved.

It is noted that although the steps of the methods of the present invention are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken into multiple step executions, etc.

Further, in the present exemplary embodiment, an overlay error correction system is also provided. Referring to fig. 8, the overlay error correction system 800 may include: exposure alignment apparatus 810, marking error measurement apparatus 820, and computing apparatus 830.

Specifically, the exposure alignment apparatus 810 is configured to obtain an initial current batch of wafers, and perform exposure alignment processing on the initial current batch of wafers to obtain a current batch of wafers.

The mark error measuring device 820 is configured to determine a specified number of alignment marks based on the integrity of the overlay error marks of the current batch of wafers, and determine an overlay error deviation value corresponding to the current batch of wafers based on the alignment marks. Acquiring an overlay error identifier corresponding to the current batch of wafers, and determining whether the overlay error identifier is damaged in step S810 to obtain the integrity of the overlay error identifier. In step S820, if the integrity of the overlay error flag is greater than the integrity threshold, that is, the overlay error flag is not damaged, configuring a pattern selection box for selecting an alignment mark; in step S830, if the integrity of the overlay error flag is less than or equal to the integrity threshold, i.e. the overlay error flag is damaged, a plurality of graphic selection boxes are configured for selecting the alignment mark. And then screening to obtain a target alignment mark based on the mark quality values of the plurality of alignment marks, and calculating the overlay error deviation value of the current batch of wafers based on the target alignment mark.

And the computing device 830 is configured to determine an overlay error compensation value based on the overlay error deviation value, and send the overlay error compensation value to the exposure alignment device. By the alignment error correction system, the alignment error is corrected, so that the influence on the accuracy of the alignment error under the condition that the alignment mark is damaged can be eliminated, the accuracy of the alignment error is improved, and the yield of products is improved.

Further, in the present exemplary embodiment, an overlay error correction apparatus is also provided. Referring to fig. 9, the overlay error correction apparatus 900 may include: an alignment mark determination module 910, a mark metric determination module 920, a mark screening module 930, and an error correction module 940.

Specifically, the alignment mark determining module 910 is configured to obtain a current batch of wafers, determine a plurality of alignment marks corresponding to the current batch of wafers, and determine an overlay error and an overlay error deviation corresponding to each alignment mark; a mark metric determining module 920, configured to determine a mark quality value corresponding to each alignment mark based on an alignment error of each alignment mark and an alignment error deviation; a mark screening module 930 configured to screen the plurality of alignment marks based on the determined mark quality values to determine a target alignment mark; the error correction module 940 is configured to determine an error correction result corresponding to the current batch of wafers based on the target alignment mark, and perform exposure alignment processing on the next batch of wafers based on the error correction result.

In an exemplary embodiment of the present disclosure, the overlay error correction apparatus 900 further includes a pattern library configuration module for: acquiring an overlay error identifier corresponding to the current batch of wafers; respectively acquiring a reference identification signal and an actual identification signal corresponding to the overlay error identification; determining the mark integrity of the overlay error mark according to the actual mark signal and the reference mark signal; configuring a plurality of graphic selection boxes to determine a plurality of alignment marks based on the plurality of graphic selection boxes if the identification integrity is less than the integrity threshold; if the identity integrity is greater than or equal to the integrity threshold, a graphical selection box is configured to determine the alignment mark based on the graphical selection box.

In an exemplary embodiment of the present disclosure, the number of the alignment marks is plural, and the alignment mark determining module 910 includes a test flag determining unit for: determining a graph selection position corresponding to the wafers in the current batch; acquiring the position number of the figure selection positions, and configuring a corresponding number of figure selection frames according to the position number; and carrying out graphic marking processing on the wafers in the current batch based on the determined graphic selection position and the determined graphic selection frame to obtain a plurality of alignment marks.

In an exemplary embodiment of the present disclosure, the test flag determining unit includes a pattern position determining unit to: acquiring the identification type of the overlay error identification of the current batch of wafers; determining a symmetrical center point corresponding to the wafers in the current batch; determining at least one figure selection direction corresponding to the current test product based on the symmetrical center point; and determining a graphic selection position corresponding to each graphic selection direction based on the identification type.

In an exemplary embodiment of the disclosure, the graphic position determination unit includes a graphic position determination subunit operable to: determining the graphic identification characteristics of the wafers in the current batch based on the identification type; determining an inner border diagram selection position in each diagram selection direction based on the diagram identification features; and determining the outer frame graph selection position of the wafers in the current batch based on the graph identification characteristics.

In an exemplary embodiment of the present disclosure, the mark metric value determining module 920 includes an identification metric value determining unit for: determining overlay errors corresponding to the alignment marks; determining the overlay error deviation and the standard deviation of the overlay error deviation corresponding to each alignment mark based on the overlay error; determining a mark quality value according to the overlay error, the overlay error deviation and the overlay error deviation standard deviation; mark quality value

In an exemplary embodiment of the disclosure, the identification metric value determining unit comprises an overlay error parameter determining subunit for: determining an overlay error derivative corresponding to the overlay error; determining an overlay error deviation based on the overlay error and an overlay error derivative; determining an overlay error deviation standard deviation based on the overlay error deviation; overlay error deviation Qmerit = OVL' -OVL; where Qmerit represents the overlay error deviation of the alignment mark, OVL represents the overlay error of the alignment mark, and OVL' represents the overlay error derivative of the alignment mark.

In an exemplary embodiment of the present disclosure, the number of the alignment marks is plural, and the mark screening module 930 includes an identification screening unit for: determining a mean value of the marking quality for a plurality of marking quality values; and taking the alignment mark with the mark quality value smaller than the mark quality average value as a target alignment mark.

In an exemplary embodiment of the present disclosure, the error correction module 940 includes an error correction unit to: determining a target mark signal of the target alignment mark; analyzing and processing the target mark signal, and determining a target central point corresponding to the target alignment mark; determining a target overlay error value corresponding to the target alignment mark based on the target central point; performing analog calculation on the target overlay error value, and determining an overlay error compensation value corresponding to the current batch of wafers; and taking the alignment error compensation value as an error correction result.

In an exemplary embodiment of the disclosure, the error correction unit includes an error correction subunit for: acquiring a pattern alignment direction corresponding to a current test product; the pattern alignment direction comprises a first alignment direction and a second alignment direction; determining a first registration error value corresponding to the first alignment direction based on the target center point; determining a second registration error value corresponding to the second alignment direction based on the target center point; and generating a target overlay error value according to the first overlay error value and the second overlay error value.

In an exemplary embodiment of the present disclosure, the overlay error correction apparatus 900 includes a correction result feedback module for: sending the error correction result to exposure alignment equipment; and controlling the exposure alignment equipment to adjust the corresponding pattern alignment parameters based on the error correction result so that the exposure alignment equipment performs exposure alignment processing on the wafers of the next batch based on the pattern alignment parameters.

The details of the virtual modules of each overlay error correction apparatus are already described in detail in the corresponding overlay error correction method, and therefore are not described herein again.

It should be noted that although in the above detailed description several modules or units of the overlay error correction means are mentioned, this division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

In addition, in an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or program product. Accordingly, various aspects of the present invention may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

An electronic device 1000 according to such an embodiment of the present disclosure is described below with reference to fig. 10. The electronic device 1000 shown in fig. 10 is only an example and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 10, the electronic device 1000 is embodied in the form of a general purpose computing device. The components of the electronic device 1000 may include, but are not limited to: the at least one processing unit 1010, the at least one memory unit 1020, a bus 1030 connecting different system components (including the memory unit 1020 and the processing unit 1010), and a display unit 1040.

Wherein the storage unit stores program code that may be executed by the processing unit 1010 to cause the processing unit 1010 to perform the steps according to various exemplary embodiments of the present disclosure described in the "exemplary methods" section above in this specification.

The memory unit 1020 may include readable media in the form of volatile memory units, such as a random access memory unit (RAM) 1021 and/or a cache memory unit 1022, and may further include a read-only memory unit (ROM) 1023.

Storage unit 1020 may also include a program/utility 1024 having a set (at least one) of program modules 1025, such program modules 1025 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.

Bus 1030 may represent one or more of any of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 1000 may also communicate with one or more external devices 1070 (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the electronic device 1000, and/or with any device (e.g., router, modem, etc.) that enables the electronic device 1000 to communicate with one or more other computing devices. Such communication may occur through input/output (I/O) interfaces 1050. Also, the electronic device 1000 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the internet) via the network adapter 1060. As shown, the network adapter 1060 communicates with the other modules of the electronic device 1000 over the bus 1030. It should be understood that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.

Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

In an exemplary embodiment of the present disclosure, there is also provided a computer readable storage medium having stored thereon a program product capable of implementing the above-described method of the present specification. In some possible embodiments, aspects of the invention may also be implemented in the form of a program product comprising program code means for causing a terminal device to carry out the steps according to various exemplary embodiments of the invention described in the above-mentioned "exemplary methods" section of the present description, when said program product is run on the terminal device.

Referring to fig. 11, a program product 1100 for implementing the above method according to an embodiment of the present invention is described, which may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited in this respect, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

A computer readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).

Furthermore, the above-described drawings are only schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.

Claims

1. An overlay error correction method, comprising:

obtaining a current batch of wafers, and determining a plurality of alignment marks corresponding to the current batch of wafers, and an alignment error deviation corresponding to each alignment mark;

determining a mark quality value corresponding to each alignment mark based on the overlay error and the overlay error deviation of each alignment mark;

screening the plurality of alignment marks based on the determined mark quality values to determine a target alignment mark;

and determining an error correction result corresponding to the current batch of wafers based on the target alignment mark, and carrying out exposure alignment processing on the next batch of wafers based on the error correction result.

2. The method of claim 1, wherein said obtaining the current lot of wafers comprises:

acquiring an overlay error identifier corresponding to the current batch of wafers;

respectively acquiring a reference identification signal and an actual identification signal corresponding to the overlay error identification;

determining the mark integrity of the overlay error mark according to the actual mark signal and the reference mark signal;

configuring a plurality of graphical selection boxes to determine a plurality of the alignment marks based on a plurality of the graphical selection boxes if the identity integrity is less than an integrity threshold;

configuring one of the graphic selection boxes to determine the alignment mark based on the graphic selection box if the identity integrity is greater than or equal to an integrity threshold.

3. The method of claim 1, wherein the number of the alignment marks is plural, and the determining the plurality of alignment marks corresponding to the current lot of wafers comprises:

determining a graph selection position corresponding to the current batch of wafers;

acquiring the position number of the graph selection positions, and configuring a corresponding number of graph selection frames according to the position number;

and carrying out graphic marking processing on the wafers in the current batch based on the determined graphic selection position and the determined graphic selection frame to obtain a plurality of alignment marks.

4. The method of claim 3, wherein the determining the pattern selection location corresponding to the current lot of wafers comprises:

obtaining the identification type of the overlay error identification of the current batch of wafers;

determining a symmetrical center point corresponding to the current batch of wafers;

determining at least one figure selection direction corresponding to the current test product based on the symmetrical center point;

and determining the graphic selection position corresponding to each graphic selection direction based on the identification type.

5. The method according to claim 4, wherein the determining the graphic selection position corresponding to each graphic selection direction based on the identification type comprises:

determining the graphic identification characteristics of the wafers of the current batch based on the identification type;

determining an inner border graphic selection position in each graphic selection direction based on the graphic identification features;

and determining the outer frame graph selection position of the current batch of wafers based on the graph identification features.

6. The method of claim 1, wherein determining a mark quality value for each of the alignment marks comprises:

determining overlay errors corresponding to the alignment marks;

determining an alignment error deviation and an alignment error deviation standard deviation corresponding to each alignment mark based on the alignment errors;

determining the mark quality value according to the overlay error, the overlay error deviation and the overlay error deviation standard deviation;

the mark quality value

Wherein MQ represents a mark quality value of the alignment mark, OVL represents an overlay error of the alignment mark, qmerit represents an overlay error deviation of the alignment mark, qmerit δ ² Indicating the standard deviation of the overlay error of the alignment mark.

7. The method of claim 6, wherein determining an overlay error deviation and an overlay error deviation standard deviation for each of the alignment marks based on the overlay errors comprises:

determining an overlay error derivative corresponding to the overlay error;

determining the overlay error bias based on the overlay error and the overlay error derivative;

determining the standard deviation of overlay error based on the overlay error deviation;

the overlay error deviation Qmerit = OVL' -OVL;

wherein Qmerit represents an overlay error deviation of the alignment mark, OVL represents an overlay error of the alignment mark, and OVL' represents an overlay error derivative of the alignment mark.

8. The method of claim 1, wherein the number of alignment marks is plural, and wherein the screening the plural alignment marks to determine a target alignment mark based on the determined mark quality values comprises:

determining a marker quality average value corresponding to a plurality of said marker quality values;

and regarding the alignment mark with the mark quality value smaller than the mark quality average value as the target alignment mark.

9. The method of claim 1, wherein determining the error correction result corresponding to the current lot of wafers based on the target alignment mark comprises:

determining a target mark signal for the target alignment mark;

analyzing and processing the target mark signal, and determining a target central point corresponding to the target alignment mark;

determining a target overlay error value corresponding to the target alignment mark based on the target center point;

performing analog calculation on the target overlay error value, and determining an overlay error compensation value corresponding to the current batch of wafers;

and taking the alignment error compensation value as the error correction result.

10. The method of claim 9, wherein determining a target overlay error value corresponding to the target alignment mark based on the target center point comprises:

acquiring a pattern alignment direction corresponding to the current test product; the pattern alignment direction comprises a first alignment direction and a second alignment direction;

determining a first overlay error value corresponding to the first alignment direction based on the target center point;

determining a second registration error value corresponding to the second alignment direction based on the target center point;

and generating the target overlay error value according to the first overlay error value and the second overlay error value.

11. The method of claim 1, wherein performing exposure alignment processing on the next batch of wafers based on the error correction result comprises:

sending the error correction result to exposure alignment equipment;

and controlling the exposure alignment equipment to adjust corresponding pattern alignment parameters based on the error correction result so that the exposure alignment equipment performs exposure alignment processing on the next batch of wafers based on the pattern alignment parameters.

12. An overlay error correction system, comprising:

the exposure alignment equipment is used for acquiring the initial current batch of wafers and carrying out exposure alignment processing on the initial current batch of wafers to obtain the current batch of wafers;

the mark error measuring equipment is used for determining a specified number of alignment marks based on the alignment error mark integrity of the current batch of wafers and determining the alignment error deviation value corresponding to the current batch of wafers based on the alignment marks;

and the computing equipment is used for determining an alignment error compensation value based on the alignment error deviation value and sending the alignment error compensation value to the exposure alignment equipment.

13. An overlay error correction apparatus, comprising:

the alignment mark determining module is used for acquiring a current batch of wafers, determining a plurality of alignment marks corresponding to the current batch of wafers, and an alignment error deviation corresponding to each alignment mark;

a mark metric value determination module for determining a mark quality value corresponding to each alignment mark based on an overlay error and an overlay error deviation of each alignment mark;

the mark screening module is used for screening the plurality of alignment marks based on the determined mark quality values to determine target alignment marks;

and the error correction module is used for determining an error correction result corresponding to the current batch of wafers based on the target alignment mark so as to perform exposure alignment processing on the next batch of wafers based on the error correction result.

14. An electronic device, comprising:

a processor; and

a memory having computer readable instructions stored thereon which, when executed by the processor, implement the overlay error correction method of any one of claims 1 to 11.

15. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the overlay error correction method according to any one of claims 1 to 11.