CN115952026A - Method, device, equipment and storage medium for positioning abnormity of virtual chip - Google Patents
Method, device, equipment and storage medium for positioning abnormity of virtual chip Download PDFInfo
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Abstract
The invention discloses a method, a device, equipment and a storage medium for positioning an exception of a virtual chip. The method comprises the following steps: acquiring link output values of signal links of the virtual chip aiming at a target excitation signal, and extracting sub-link output values respectively corresponding to signal sub-links of each functional module in the virtual chip from the link output values; detecting a standard mark value pre-inserted for each functional module in the output values of the sublinks of the functional modules, and acquiring a problem module according to the detection result; and successively determining the positions of all the sub-links in the problem signal sub-links of all the problem modules, and positioning the position of the problem sub-link according to the problem sub-link output value output by all the problem signal sub-links under the dual action of the target excitation signal and the fixed signal value in all the sub-link positions. Through the technical scheme, the problem sublink position can be accurately positioned in the virtual chip, so that research personnel can conveniently position the problem trigger in the real chip, and the chip inspection efficiency is improved.
Description
Technical Field
The present invention relates to the field of chip detection technologies, and in particular, to a method, an apparatus, a device, and a storage medium for locating an abnormality of a virtual chip.
Background
With the development of chip technology, the number of flip-flops introduced by a single chip in internal design has reached the level of ten million. In the testing process of the chip, if an error exists in the chip, the reason of the error needs to be determined, and if the trigger in the chip generates the error, the problem trigger generating the error needs to be accurately positioned in a large number of triggers.
In the prior art, the error cause of the chip is usually determined by a series of operations of checking design logic, checking scan configuration sequence, checking clock control logic, and checking register bit mapping file.
However, the existing method for checking the chip consumes a long time and has low efficiency, and when the trigger in the chip generates an error, the problem trigger is difficult to be accurately positioned in a large amount of triggers.
Disclosure of Invention
The invention provides an abnormal positioning method, device, equipment and storage medium of a virtual chip, which can accurately position a problem sublink position in the virtual chip, thereby being convenient for research personnel to position a problem trigger in a real chip and improving the chip inspection efficiency.
According to an aspect of the present invention, there is provided a method for locating an anomaly of a virtual chip, including:
acquiring link output values of signal links of the virtual chip aiming at a target excitation signal, and extracting sub-link output values respectively corresponding to signal sub-links of all functional modules in the virtual chip from the link output values;
detecting a standard mark value pre-inserted for each functional module in the output values of the sublinks of the functional modules, and acquiring a problem module according to the detection result;
and successively determining the positions of the sub-links in the problem signal sub-links of the problem modules, and positioning the positions of the problem sub-links according to the output values of the problem sub-links output by the problem signal sub-links under the dual functions of the target excitation signal and the fixed signal values in the positions of the sub-links.
According to another aspect of the present invention, there is provided an abnormality positioning device for a virtual chip, including:
the sub-link output value acquisition module is used for acquiring link output values of signal links of the virtual chip aiming at the target excitation signal and extracting sub-link output values respectively corresponding to signal sub-links of each functional module in the virtual chip from the link output values;
the problem module acquisition module is used for detecting a standard mark value which is inserted in advance for each functional module in the sub-link output values of the functional modules and acquiring the problem module according to the detection result;
and the problem sublink position positioning module is used for successively determining the position of each sublink in the problem signal sublink of each problem module, and positioning the position of the problem sublink according to the problem sublink output value output by each problem signal sublink under the dual action of the target excitation signal and the fixed signal value in each sublink position.
According to another aspect of the present invention, there is provided an electronic apparatus including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the method for locating the virtual chip exception according to any embodiment of the present invention.
According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the method for locating an anomaly of a virtual chip according to any one of the embodiments of the present invention when the computer instructions are executed.
According to the technical scheme of the embodiment of the invention, the problem sub-link position can be accurately positioned in the virtual chip by acquiring the link output value of the signal link of the virtual chip aiming at the target excitation signal and the sub-link output value respectively corresponding to the signal sub-link of each functional module in the virtual chip, acquiring the problem module according to the standard mark value detection result of each functional module, and positioning the problem sub-link position according to the problem sub-link output value output by each problem signal sub-link under the dual action of the target excitation signal and the fixed signal value in each sub-link position, so that research personnel can conveniently position the problem trigger in the real chip, and the chip inspection efficiency is improved.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1a is a flowchart of an exception handling method for a virtual chip according to an embodiment of the present invention;
FIG. 1b is a schematic diagram of a series connection of functional modules according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating another method for locating an exception of a virtual chip according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of an anomaly locating apparatus for a virtual chip according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device implementing the method for locating an anomaly of a virtual chip according to the embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example one
Fig. 1a is a flowchart of an exception location method for a virtual chip according to an embodiment of the present invention, where the method is applicable to a situation where a signal link of the virtual chip analyzes a link output value of a target excitation signal, and a problem sublink location is located in the signal link of the virtual chip, and the method may be executed by an exception location device of the virtual chip, where the exception location device of the virtual chip may be implemented in a form of hardware and/or software, and may generally be configured in a computer with a data processing function. As shown in fig. 1a, the method comprises:
s110, obtaining link output values of signal links of the virtual chip aiming at the target excitation signals, and extracting sub-link output values respectively corresponding to signal sub-links of each functional module in the virtual chip from the link output values.
Optionally, the virtual chip is a virtual chip built by a technician in a virtual simulation platform according to the same configuration as the real chip. For example, a virtual chip may include 6 serial functional modules, and each functional module may include 500 ten thousand serial flip-flops, so that the virtual chip is actually formed by connecting 3 ten million flip-flops in series. In the virtual chip, all the serially connected flip-flops form a signal link of the virtual chip, and in the previous example, for a virtual chip formed by serially connecting 3 million flip-flops, the 3 million flip-flops form a signal link of the virtual chip. In each functional module of the virtual chip, all the serially connected flip-flops in the functional module form a signal sub-link of the functional module, and in the previous example, for the functional module formed by serially connecting 500 ten thousand flip-flops, the 500 ten thousand flip-flops form a signal sub-link of the functional module. It can also be understood that the signal sub-links of the functional modules in the virtual chip are connected in series to form the signal link of the virtual chip.
It is understood that, when an excitation signal is sent to the flip-flop, an output value of the flip-flop for the excitation signal may be obtained, and the output value of the flip-flop may be 0 or 1. The target excitation signal may be an excitation signal selected by a designer according to actual design requirements, and generally, the target excitation signal may be the same as the excitation signal sent to the real chip, so that the designer further determines whether the target excitation signal is one of factors affecting the performance of the chip, sends the target excitation signal to the signal link of the virtual chip, may obtain an output value of the signal link of the virtual chip for the target excitation signal, that is, an output value of each serially connected flip-flop in the virtual chip for the target excitation signal, for example, for the signal link composed of 10 flip-flops, under the condition that the chip normally operates, an output value of the signal link for the target excitation signal is 10 combined values of 0 or 1, and 1101000011 is an optional link output value example, which is merely for facilitating understanding of the embodiment of the present invention, and does not limit specific values of each output value in this example. It should also be understood that the sub-link output values corresponding to the signal sub-links of each functional module in the virtual chip may be combined to form the link output value of the signal link of the virtual chip for the target excitation signal, and in the case that the signal link formed by 10 flip-flops is formed by two functional modules and each functional module includes 5 flip-flops, the sub-link output values corresponding to the signal sub-links of the two functional modules are 11010 and 00011, respectively.
S120, detecting a standard mark value pre-inserted for each functional module in the sub-link output values of the functional modules, and acquiring a problem module according to the detection result.
Optionally, when the virtual chip is built, a mark value matched with the functional module may be inserted into the designated position of the functional module, and the mark value is used as a standard mark value of the functional module. In general, the standard mark value can be inserted at any designated position of the functional module, and in practical applications, the standard mark value can also be inserted at the head of the functional module in order to distinguish the standard mark value and quickly acquire and detect the standard mark value. For example, for the functional module 1 in the virtual chip, 00001 may be inserted into the header of the functional module 1, where 00001 is the standard tag value of the functional module 1.
It can be understood that, by determining whether the currently detected flag value in the functional module is the same as the standard flag value of the functional module, a preliminary determination may be made as to whether there is a problem with the functional module. In the previous example, the sub-link output value in the function module 1 is obtained, and the first five bits of the sub-link output value of the function module 1 are extracted, and if the sub-link output value is 00010, the sub-link output value does not conform to the pre-inserted standard flag value 00001, and at this time, the function module 1 is a problem module.
FIG. 1b is a schematic diagram of an alternative series connection of functional modules. As shown in fig. 1b, the virtual chip includes 7 functional modules, which are IP1-IP7, and the IP1-IP7 are connected in series according to serial numbers, where TDI is the data input terminal and TDO is the data output terminal. In the process of scan unloading of the signal link, the link output value of the virtual chip is output from the TDO end, and as can be seen from fig. 1b, the sub-link output value of the functional module IP7 is output first from the TDO end, and the sub-link output value of the functional module IP1 is output last, and if there is an error in the sub-link output value output first, the sub-link output value output later is also generally erroneous. Therefore, if a change in the standard flag values in the functional modules IP1 to IP4 is detected, all of the functional modules IP1 to IP4 can be regarded as problem modules, and the cause of the problem can be specifically checked from the functional module IP 4.
S130, successively determining the positions of the sub-links in the problem signal sub-links of the problem modules, and positioning the positions of the problem sub-links according to the problem sub-link output values output by the problem signal sub-links under the dual functions of the target excitation signal and the fixed signal values in the sub-link positions.
In the actual process of analyzing the signal sublinks of the functional modules, because the output value of the sublink output by one functional module can reach millions of digits, if millions of sublink output values are directly analyzed, the analysis efficiency is extremely low, and labor cost and time cost are greatly wasted.
In view of the above problems, the present invention provides a method for locating a faulty sub-link in a faulty sub-link, in which a sub-link position designated in a faulty signal sub-link is set as a fixed signal value, a target excitation signal is made to act on the faulty signal sub-link to obtain a faulty sub-link output value, and the faulty sub-link output value is analyzed to locate a faulty sub-link position in the faulty sub-link.
It can be understood that after the designated sub-link position is set as a fixed signal value, if a stimulus is sent to the sub-link and scan unloading is performed, the signal value of the sub-link position does not jump, the fixed signal value is always maintained, and the signal values after the sub-link position are also all fixed signal values.
In a specific example, an initial sublink position may be selected from the problem sublink, for example, a signal sublink including 500 ten thousand triggers, a position where a 250 th thousand trigger is located may be selected as the initial sublink position, the initial sublink position is set to a fixed signal value, the fixed signal value may be 0 or 1, a target excitation signal is sent to the problem sublink, an output value of the problem sublink is obtained, then the fixed signal value is changed (if the fixed signal value set for the first time is 0, the fixed signal value after the change is 1, if the fixed signal value set for the first time is 1, the fixed signal value after the change is 0), the target excitation signal is sent to the problem sublink, the output value of the problem sublink is obtained, the output values of the two problem sublinks are compared, and according to the comparison result, it can be determined that the problem sublink position is 1 to 250 thousand or 250 to 500 thousand in the signal sublink. And then, new sublink positions can be continuously selected, and the position range of the problem sublink is gradually reduced until the accurate problem sublink position is obtained. By the mode, the position of the problematic sublink can be quickly and accurately positioned in a large number of signal sublinks.
Next, a specific example is described how to compare the output values of the two problem sublinks to obtain a comparison result. In order to make the description more intuitive, a sub-link with 40 output values is taken as an example, and the output values are as follows:
00001 10011 01100 11010 10011 01100 11011 00100
here, for the purpose of visual effect, the output values are displayed in groups of five, and the actual sublink output values are continuous values. First, a 21 st sub-link position may be selected, the 21 st sub-link position is set to be a fixed signal value 0, and after the excitation signal is sent to the problem sub-link, the output values obtained by scan unloading are as follows:
00001 10011 01100 11010 00000 00000 00000 00000
then, the 21 st sub-link position is set as a fixed signal value 1, and after the excitation signal is sent to the problem sub-link, the output values of scan unloading are as follows:
00001 10011 01100 11010 11111 11111 11111 11111
at this time, the two output values after the fixed signal value is set may be compared to obtain a portion where the two output values are different, that is, the sub-link after the 21 st sub-link position is selected. In this example, if the problem sub-link location is before the 21 st sub-link location, the two portions with different output values should be 20 consecutive 1 s, and if the problem sub-link location is after the 21 st sub-link location, one of the possible cases is that the two portions with different output values only have 19 consecutive 1 s. If the problem sub-link position is determined to be located at the 21 st sub-link position, the 31 st sub-link position can be further selected, and the 31 st sub-link position is set to be a fixed signal value, so that the problem sub-link is scanned and stored to obtain an output value until the accurate problem sub-link position is finally located.
According to the technical scheme of the embodiment of the invention, the problem sub-link position can be accurately positioned in the virtual chip by acquiring the link output value of the signal link of the virtual chip aiming at the target excitation signal and the sub-link output value respectively corresponding to the signal sub-link of each functional module in the virtual chip, acquiring the problem module according to the standard mark value detection result of each functional module, and positioning the problem sub-link position according to the problem sub-link output value output by each problem signal sub-link under the dual action of the target excitation signal and the fixed signal value in each sub-link position, so that research personnel can conveniently position the problem trigger in the real chip, and the chip inspection efficiency is improved.
Example two
Fig. 2 is a flowchart of another method for locating an abnormality of a virtual chip according to a second embodiment of the present invention, which specifically describes a method for locating an abnormality of a virtual chip based on the second embodiment. As shown in fig. 2, the method includes:
s210, respectively connecting triggers included in each functional module in the virtual chip in series to obtain signal sub-links respectively corresponding to each functional module.
And S220, respectively connecting the signal sub-links of each functional module in series to obtain a signal link of the virtual chip.
And S230, inputting a target excitation signal to the signal link through the joint test workgroup interface, suspending a clock process in the signal link, and acquiring a link output value of the signal link aiming at the target excitation signal.
The Joint Test Action Group (JTAG) interface is an international standard test protocol mainly used for internal testing of chips. Optionally, the flip-flops inside the virtual chip may be connected in series through the JTAG interface.
Further, after the target excitation signal is input to the signal link, the clock process in the signal link may be suspended, and at this time, the output values of the flip-flops constituting the signal link remain unchanged, and the signal link may be scan-transferred to obtain the link output value of the signal link for the target excitation signal.
S240, sub-link output values corresponding to the signal sub-links of each functional module in the virtual chip are extracted from the link output values.
And S250, judging whether the total length of the signal link of the virtual chip is the same as a preset standard length or not according to the link output value of the signal link of the virtual chip aiming at the target excitation signal.
It can be understood that, for a signal link composed of 3 million triggers, in a normal operating state, the link output value for a target excitation signal is also 3 million, and the preset standard length of the signal link matches with the number of triggers of the signal link.
And S260, if the total length of the signal link of the virtual chip is different from the preset standard length, generating a signal link missing prompt and sending the signal link missing prompt to a user side.
If the total length of the signal link of the virtual chip is different from the preset standard length, the situation may be that the signal link of the virtual chip is disconnected or the signal link is lost, and the like, at this time, it may be preliminarily determined that the signal link of the virtual chip has a problem, a signal link loss prompt may be generated and sent to the user side, and the following steps are performed to obtain a specific position in the signal link where the problem exists.
S270, according to the pre-stored mark positions, the current mark value of each function module is obtained from the sublink output values of each function module, and whether the current mark value of each function module is the same as the standard mark value pre-inserted for the function module is judged.
S280, acquiring a problem module with a current mark value different from a standard mark value in all the functional modules.
And S290, acquiring the position of the target sublink in the current problem signal sublink of the current problem module according to the link positioning interval.
The link positioning interval is a position interval in which the problematic sub-link may be located in the whole signal sub-link, the target sub-link position may be a first sub-link position in the link positioning interval, and when the target sub-link position is determined for the first time, if there is no clear link positioning interval, a possible target sub-link position may be selected according to experience, or may be selected according to other factors, and a method for selecting the target sub-link position is not limited.
S2100, acquiring a first problem sublink output value output by the current problem signal sublink under the dual action of a target excitation signal and a first fixed signal value in the position of the target sublink.
And S2110, acquiring a second problem sublink output value output by the current problem signal sublink under the dual action of the target excitation signal and a second fixed signal value in the target sublink position.
The first fixed signal value is different from the second fixed signal value, the second fixed signal value is 1 when the first fixed signal value is 0, and the second fixed signal value is 0 when the first fixed signal value is 1.
S2120, according to the first problem sublink output value, the second problem sublink output value and the link positioning interval, positioning the current problem sublink position in the current problem module.
The method for locating the position of the sub-link with the current problem in the module with the current problem according to the output value of the sub-link with the first problem, the output value of the sub-link with the second problem and the link locating interval comprises the following steps:
acquiring a first output value set positioned behind the target sublink position in the first problem link output value, and counting the total number of first output values in the output value set;
in the output values of the second problem link, acquiring a second output value set positioned behind the target sublink position, and counting the total number of the second output values in the output value set;
comparing whether the total number of the first output values and the total number of the second output values are consistent;
determining whether the position of the sub-link with the current problem can be positioned according to the comparison result and the link positioning interval;
if so, determining that the positioning is successful, otherwise, updating according to the comparison result to obtain a new link positioning interval.
S2130, if the positioning is successful, outputting the current problem sublink position obtained through the positioning; and if the positioning fails, acquiring a currently updated link positioning interval and returning to execute the operation of acquiring the position of the target sublink in the current problem signal sublink of the current problem module according to the link positioning interval until the current problem sublink position is obtained by positioning.
According to the technical scheme of the embodiment of the invention, whether the signal link of the virtual chip has a problem can be quickly detected by judging whether the total length of the signal link of the virtual chip is the same as the preset standard length or not and generating a signal link missing prompt and sending the signal link missing prompt to the user side when the total length of the signal link of the virtual chip is different from the preset standard length, so that a reliable basis can be provided for further problem analysis.
Optionally, the method for locating the abnormality of the virtual chip according to the present invention may further include:
if no problem module exists in each functional module, acquiring a plurality of target sublink position groups in each functional module according to the prestored trigger group positions;
judging whether the output value of each target sublink position group is the same as a preset standard value of the target sublink position group or not;
and if the output value of the target sublink position group is the same as a preset standard value of the target sublink position group, determining that the signal link of the virtual chip is a correct signal link.
It will be appreciated that the registers may be added to the signal chain in the form of groups of flip-flops. The value in the register does not change with changes in the stimulus signal.
In this embodiment, the target sublink position group may be understood as a position where the register is located, and the standard value of the target sublink position group may be understood as a value of the register.
If the output value of the target sublink position group is the same as the preset standard value of the target sublink position group, the total length of the signal link of the virtual chip in step S250 is the same as the preset standard length, and the current tag value of each functional module in step S270 is the same as the standard tag value pre-inserted for the functional module, it can be preliminarily determined that the virtual chip is correctly built, the selection of the target excitation signal is correct, the scanned data link output value is reliable, and the virtual chip can be used for further chip analysis.
EXAMPLE III
Fig. 3 is a schematic structural diagram of an anomaly locating device of a virtual chip according to a third embodiment of the present invention. As shown in fig. 3, the apparatus includes: a sublink output value acquisition module 310, a problem module acquisition module 320, and a problem sublink position location module 330.
The sub-link output value obtaining module 310 is configured to obtain link output values of the signal links of the virtual chip for the target excitation signal, and extract sub-link output values corresponding to the signal sub-links of each functional module in the virtual chip from the link output values.
The problem module acquiring module 320 is configured to detect a standard flag value pre-inserted for each functional module in the sub-link output values of the functional modules, and acquire a problem module according to a detection result.
The problem sublink position locating module 330 is configured to successively determine positions of the respective problematic sublinks in the problematic signal sublinks of the respective problematic modules, and locate a position of the problematic sublink according to an problematic sublink output value output by the respective problematic signal sublinks under dual actions of a target excitation signal and a fixed signal value in the respective sublink position.
According to the technical scheme of the embodiment of the invention, the problem sub-link position can be accurately positioned in the virtual chip by acquiring the link output value of the signal link of the virtual chip aiming at the target excitation signal and the sub-link output value respectively corresponding to the signal sub-link of each functional module in the virtual chip, acquiring the problem module according to the standard mark value detection result of each functional module, and positioning the problem sub-link position according to the problem sub-link output value output by each problem signal sub-link under the dual action of the target excitation signal and the fixed signal value in each sub-link position, so that research personnel can conveniently position the problem trigger in the real chip, and the chip inspection efficiency is improved.
On the basis of the foregoing embodiments, the sub-link output value obtaining module 310 may specifically be configured to:
respectively connecting triggers included in each functional module in the virtual chip in series to obtain signal sub-links respectively corresponding to each functional module;
respectively connecting the signal sub-links of each functional module in series to obtain a signal link of a virtual chip;
and inputting a target excitation signal to the signal link through the joint test working group interface, suspending a clock process in the signal link, and acquiring a link output value of the signal link aiming at the target excitation signal.
On the basis of the foregoing embodiments, the method may further include a signal link loss prompt generating module, which is specifically configured to:
judging whether the total length of the signal link of the virtual chip is the same as a preset standard length or not according to the link output value of the signal link of the virtual chip aiming at the target excitation signal;
and if the total length of the signal link of the virtual chip is different from the preset standard length, generating a signal link missing prompt and sending the signal link missing prompt to a user side.
On the basis of the foregoing embodiments, the problem module obtaining module 320 may be specifically configured to:
according to the pre-stored mark position, obtaining the current mark value of each functional module from the sub-link output value of each functional module, and judging whether the current mark value of each functional module is the same as the standard mark value pre-inserted for the functional module;
and acquiring a problem module with a current marking value different from the standard marking value in all the functional modules.
On the basis of the above embodiments, the problem sublink position locating module 330 may include:
the target sublink position acquisition unit is used for acquiring a target sublink position in a current problem signal sublink of a current problem module according to the link positioning interval;
a first problem sublink output value acquisition unit, configured to acquire a first problem sublink output value output by a current problem signal sublink under dual actions of a target excitation signal and a first fixed signal value in a target sublink position;
a second problem sublink output value acquiring unit, configured to acquire a second problem sublink output value output by the current problem signal sublink under dual actions of the target excitation signal and a second fixed signal value in the target sublink position;
the problem sublink position positioning unit is used for positioning the current problem sublink position in the current problem module according to the first problem sublink output value, the second problem sublink output value and the link positioning interval;
the repeated positioning unit is used for outputting the current problem sublink position obtained by positioning if the positioning is successful; and if the positioning fails, acquiring a currently updated link positioning interval and returning to execute the operation of acquiring the position of the target sublink in the current problem signal sublink of the current problem module according to the link positioning interval until the current problem sublink position is obtained by positioning.
On the basis of the above embodiments, the problem sublink position locating unit may be specifically configured to:
acquiring a first output value set positioned behind the target sublink position in the first problem link output value, and counting the total number of first output values in the output value set;
acquiring a second output value set positioned behind the target sublink position in the second problem link output values, and counting the total number of the second output values in the output value set;
comparing whether the total number of the first output values and the total number of the second output values are consistent;
determining whether the position of the sub-link with the current problem can be positioned according to the comparison result and the link positioning interval;
if so, determining that the positioning is successful, otherwise, updating according to the comparison result to obtain a new link positioning interval.
On the basis of the above embodiments, the present invention further includes a correct signal link determining module, which is specifically configured to:
if no problem module exists in each functional module, acquiring a plurality of target sublink position groups in each functional module according to the pre-stored trigger group position;
judging whether the output value of each target sublink position group is the same as a preset standard value of the target sublink position group or not;
and if the output value of the target sub-link position group is the same as a preset standard value of the target sub-link position group, determining that the signal link of the virtual chip is a correct signal link.
The anomaly positioning device for the virtual chip provided by the embodiment of the invention can execute the anomaly positioning method for the virtual chip provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
Example four
FIG. 4 shows a schematic block diagram of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 4, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data necessary for the operation of the electronic apparatus 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to the bus 14.
A number of components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, or the like; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.
acquiring link output values of signal links of the virtual chip aiming at a target excitation signal, and extracting sub-link output values respectively corresponding to signal sub-links of each functional module in the virtual chip from the link output values;
detecting a standard mark value pre-inserted for each functional module in the output values of the sublinks of the functional modules, and acquiring a problem module according to the detection result;
and successively determining the positions of the sub-links in the problem signal sub-links of the problem modules, and positioning the positions of the problem sub-links according to the output values of the problem sub-links output by the problem signal sub-links under the dual functions of the target excitation signal and the fixed signal values in the positions of the sub-links.
In some embodiments, the method for exception location for a virtual chip may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the above-described method of anomaly locating for a virtual chip may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the exception locating method of the virtual chip by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. A computer program can execute entirely on a machine, partly on a machine, as a stand-alone software package partly on a machine and partly on a remote machine or entirely on a remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service are overcome.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An abnormal positioning method for a virtual chip is characterized by comprising the following steps:
acquiring link output values of signal links of the virtual chip aiming at a target excitation signal, and extracting sub-link output values respectively corresponding to signal sub-links of each functional module in the virtual chip from the link output values;
detecting a standard mark value inserted in advance for each functional module in the sub-link output values of the functional modules, and acquiring a problem module according to a detection result;
and successively determining the positions of the sub-links in the problem signal sub-links of the problem modules, and positioning the positions of the problem sub-links according to the output values of the problem sub-links output by the problem signal sub-links under the dual functions of the target excitation signal and the fixed signal values in the positions of the sub-links.
2. The method of claim 1, wherein obtaining link output values of signal links of the virtual chip for the target excitation signal comprises:
respectively connecting triggers included in each functional module in the virtual chip in series to obtain signal sub-links respectively corresponding to each functional module;
respectively connecting the signal sub-links of each functional module in series to obtain a signal link of a virtual chip;
and inputting a target excitation signal to the signal link through a joint test working group interface, suspending a clock process in the signal link, and acquiring a link output value of the signal link aiming at the target excitation signal.
3. The method of claim 1, wherein prior to detecting the pre-inserted standard flag value for each functional module in the sublink output value for that functional module, further comprising:
judging whether the total length of the signal link of the virtual chip is the same as a preset standard length or not according to the link output value of the signal link of the virtual chip aiming at the target excitation signal;
and if the total length of the signal link of the virtual chip is different from the preset standard length, generating a signal link missing prompt and sending the signal link missing prompt to the user side.
4. The method of claim 1, wherein detecting a value of a standard flag previously inserted for each functional module among the sublink output values of the functional modules and acquiring a problem module according to the detection result comprises:
according to the pre-stored mark position, obtaining the current mark value of each functional module from the sub-link output value of each functional module, and judging whether the current mark value of each functional module is the same as the standard mark value pre-inserted for the functional module;
and acquiring a problem module with a current marking value different from the standard marking value in all the functional modules.
5. The method of any of claims 1-4, wherein successively determining each sublink location in the problem signal sublink of each problem module, and locating the problem sublink location based on the problem sublink output value of each problem signal sublink as a function of both the target activation signal and the fixed signal value in each sublink location comprises:
acquiring a target sublink position in a current problem signal sublink of a current problem module according to a link positioning interval;
acquiring a first problem sublink output value output by a current problem signal sublink under the dual action of a target excitation signal and a first fixed signal value in a target sublink position;
acquiring a second problem sublink output value output by the current problem signal sublink under the dual action of a target excitation signal and a second fixed signal value in the position of the target sublink;
positioning the position of the sub-link with the current problem in the module with the current problem according to the output value of the sub-link with the first problem, the output value of the sub-link with the second problem and the link positioning interval;
if the positioning is successful, outputting the current problem sublink position obtained by the positioning; and if the positioning fails, acquiring a currently updated link positioning interval and returning to execute the operation of acquiring the position of the target sublink in the current problem signal sublink of the current problem module according to the link positioning interval until the current problem sublink position is obtained by positioning.
6. The method of claim 5, wherein locating the current problem sublink location in the current problem module based on the first problem sublink output value, the second problem sublink output value, and the link locating interval comprises:
acquiring a first output value set positioned behind the target sublink position in the first problem link output value, and counting the total number of first output values in the output value set;
acquiring a second output value set positioned behind the target sublink position in the second problem link output values, and counting the total number of the second output values in the output value set;
comparing whether the total number of the first output values and the total number of the second output values are consistent;
determining whether the position of the sub-link with the current problem can be positioned or not according to the comparison result and the link positioning interval;
if so, determining that the positioning is successful, otherwise, updating according to the comparison result to obtain a new link positioning interval.
7. The method of claim 6, further comprising:
if no problem module exists in each functional module, acquiring a plurality of target sublink position groups in each functional module according to the pre-stored trigger group position;
judging whether the output value of each target sub-link position group is the same as a preset standard value of the target sub-link position group or not;
and if the output value of the target sub-link position group is the same as a preset standard value of the target sub-link position group, determining that the signal link of the virtual chip is a correct signal link.
8. An abnormality positioning device for a virtual chip, comprising:
the sub-link output value acquisition module is used for acquiring link output values of signal links of the virtual chip aiming at the target excitation signal and extracting sub-link output values respectively corresponding to signal sub-links of each functional module in the virtual chip from the link output values;
the problem module acquisition module is used for detecting a standard mark value which is inserted in advance for each functional module in the sub-link output values of the functional modules and acquiring the problem module according to the detection result;
and the problem sublink position positioning module is used for successively determining the position of each sublink in the problem signal sublink of each problem module, and positioning the position of the problem sublink according to the problem sublink output value output by each problem signal sublink under the dual action of the target excitation signal and the fixed signal value in each sublink position.
9. An electronic device, characterized in that the electronic device comprises:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform the method of anomaly location for a virtual chip of any of claims 1-7.
10. A computer-readable storage medium storing computer instructions for causing a processor to implement the method for virtual chip exception location according to any one of claims 1-7 when executed.
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