CN115940937A - Circuit and method for judging in-loop mixing phase-locked loop signal frequency error locking - Google Patents

Abstract

The invention discloses a circuit and a method for judging the frequency error locking of a frequency mixing phase-locked loop signal in a loop, belonging to the technical field of microwave frequency synthesizers. The invention realizes effective judgment of the wrong locking signal, provides basis for timely triggering re-locking after the wrong locking, avoids the problem of output signal error caused by the fact that effective detection cannot be carried out after the wrong locking, and improves the reliability of the in-loop mixing phase-locked loop.

Description

Circuit and method for judging in-loop mixing phase-locked loop signal frequency error locking

Technical Field

The invention relates to the technical field of microwave frequency synthesizers, in particular to a circuit and a method for judging the frequency error locking of a frequency mixing phase-locked loop signal in a loop.

Background

The phase-locked loop signal locking and judging technology is widely applied to the phase-locked frequency synthesis technology, and has the function of judging whether a VCO (voltage controlled oscillator) output signal in a phase-locked loop circuit is locked on a reference signal or not, in a conventional phase-locked loop circuit, a locking and judging circuit is often integrated in a phase discriminator, a typical principle is shown in figure 1, the working principle of the phase-locked loop signal locking and judging circuit is that a loop is locked and outputs a high level when the phase-locked loop is locked and the reference frequency division signal and an RF end feedback frequency division signal fall in a detection window according to a fixed phase difference (time difference) after a reference frequency division ratio and an RF end feedback signal frequency division ratio are set according to a frequency to be locked, and otherwise, the low level is output. When the lock indicating circuit is used in a phase-locked loop single-loop circuit, whether the final VCO output signal is correctly locked can be accurately judged, but when the single integrated lock judging circuit is used in a phase detecting circuit in an in-loop mixing phase-locked circuit shown in figure 2, when the lock detecting circuit detects the lock, the possibility of wrong lock judgment also exists. Those skilled in the art are eagerly required to solve this technical problem.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a circuit and a method for judging the signal frequency error locking of an in-loop mixing phase-locked loop, so that the effective judgment of the signal error locking is realized, a basis is provided for timely triggering the re-locking after the error locking, the problem that the output signal is continuously wrong due to the fact that the effective detection cannot be carried out after the error locking is avoided, and the reliability of the in-loop mixing phase-locked loop is improved.

The purpose of the invention is realized by the following scheme:

a circuit for judging the frequency error locking of in-loop mixing phase-locked loop signal includes the first power divider, in-loop mixing phase-locked loop and error locking judging circuit, which is used to judge the REF signal theta _ref (t) dividing two paths of output by a first power divider with equal phase power, and respectively accessing an in-loop mixing phase-locked loop and a wrong lock judgment circuit as reference signals;

the in-loop mixing phase-locked loop comprises a phase discriminator, a loop filter, a VCO (voltage controlled oscillator), a second power divider and a mixer, and outputs a VCO output signal theta _VCO (t) dividing three paths of output by a second power divider with equal phase power, and respectively using the three paths of output as phase-locked output, a return mixing signal of the in-loop mixing phase-locked loop and a variable frequency divider input signal in a mislocking judgment circuit; one path of which is theta _VCO (t) and the insertion signal θ ₁ (t) after signal frequency mixing and filtering, sending the signal to a phase discriminator;

the mislock judgment circuit comprises a variable frequency divider and a mislock discriminator, wherein the variable frequency divider performs frequency division processing on a VCO output signal output by the power divider and outputs the VCO output signal to the mislock discriminator.

Further, defining the output signal obtained by the in-loop mixing phase-locked loop as theta _VCO (t)＝θ _rf (t)+θ ₁ (t), the control frequency division value of the variable frequency divider is 2;

in the in-loop mixing phase-locked loop, the R frequency division value in the loop filter and the phase discriminator is set as R ₁ N is a frequency division value of N ₁ And other phase discriminator register parameters, so that the in-loop mixing phase-locked loop is locked, and the phase discriminator locking indication outputs high level;

in the false lock judging circuit, the R frequency division value in the false lock judging circuit is set to be R ₁ The N frequency division value is N ₂ When the in-loop mixer-locked phase-locked loop is locked, two situations occur:

a) When the VCO locks at the correct frequency, i.e. θ _VCO (t)＝θ _rf (t)+θ ₁ At (t), N is set by the formula (1) ₂ Locking and detecting signal frequencies of two input ends in error lock judgment after value is addedThe signals are the same and have same source coherence, and after a detection time window is reasonably set at the moment, the locking judgment circuit outputs high level to indicate that the in-loop mixing phase-locked loop is correctly locked;

b) When the VCO locking frequency is not correct, i.e. theta _VCO (t)＝θ ₁ (t)-θ _rf At (t), N is set by the formula (1) ₂ After the value is obtained, the signal frequencies of two input ends of the locking detection are different in the false lock judgment, a detection time window is reasonably set at the moment, the two input ends cannot continuously appear in the detection time window, and the locking judgment circuit can output low level to indicate that the in-loop mixing phase-locked loop is locked by mistake;

wherein, theta _div (t) is the variable divider output signal;

the locking indication level of the mixer-PLL in the fetch loop is defined as b ₁ The lock indication level in the bit-sum false lock discrimination circuit is defined as b ₀ Bit when b ₁ b ₀ When =11, it represents that the output frequency of the in-loop mixing phase-locked loop is correctly locked; when b is ₁ b ₀ When =10, it represents that the output frequency of the in-loop mixing phase-locked loop is locked incorrectly; otherwise unlocked.

Furthermore, the phase discriminator comprises an R frequency divider, a phase discrimination circuit, a CP circuit, an N frequency divider and a locking detection circuit, wherein the R frequency divider divides the frequency of a signal entering the REF end and then enters the phase discrimination circuit and the locking detection circuit, the N frequency divider divides the frequency of the signal entering the RF end and then enters the phase discrimination circuit and the locking detection circuit, and the phase discrimination circuit and the CP circuit convert phase difference information of the two paths of signals which are sent into a current value to be output.

Further, the mixer divides the power into one path of VCO signal θ _VCO (t) and insertion signal θ ₁ (t) after down-mixing, entering the RF end of the phase discriminator; insertion signal theta ₁ (t) frequency dependent on VCO output frequency and mixed frequency θ _rf (t) determining that the phase noise level of the input mixed insertion signal is better than the feedback signal.

Further, the loop filter comprises an active or passive loop filter.

Further, the VCO outputs a sine wave signal of a corresponding frequency according to a given tuning voltage value.

Further, the variable frequency divider comprises a 1/2/4/8 variable frequency divider, and the VCO signal output by power division is subjected to direct-through, 1/2, 1/4 or 1/8 frequency division output according to the frequency of the VCO output signal and the working frequency band of the N frequency divider of the mislock discriminator.

Furthermore, the mislock discriminator comprises an N frequency divider, an R frequency divider and a lock detection circuit, wherein the N frequency division is carried out on a signal input into the RF end of the mislock discriminator, the R frequency division is carried out on a signal input into the REF end of the mislock discriminator, the signal enters the lock detection circuit, a lock discrimination time window is fixed, the number of times that the time difference between the two is continuously smaller than the set time window is recorded, and the mislock can be judged as locking when 2048 times are reached.

A method for determining an in-loop mixer-locked loop signal frequency false lock, based on the circuit for determining an in-loop mixer-locked loop signal frequency false lock as described above, comprising the steps of:

s1, setting a target frequency theta _VCO (t) inserting the mixing signal frequency θ ₁ (t) the insertion signal phase noise level is better than the feedback signal;

s2, controlling each register of a phase discriminator in the in-loop mixing phase-locked circuit, setting the phase discrimination frequency, using a digital mode for locking detection, setting detection window time, and adjusting a circuit to realize locking;

s3, controlling each register of a second phase discriminator in the false locking judging circuit, setting the phase discrimination frequency, opening an internal preceding stage for frequency division by 2, locking detection using a digital mode, setting detection window time, and controlling VCO (voltage controlled oscillator) to be frequency division by 2;

s4, when the locking detection bit b of the phase discriminator I in the in-loop mixing phase-locked circuit ₁ If =1, according to the locking detection bit b of the second phase discriminator in the false locking judging circuit ₀ The state is discriminated as follows:

1) When the error locks the second phase discriminator in the discriminating circuitLocking detection bit b ₀ =1, and when the port voltage is larger than or equal to 2.5V, judging that the in-loop mixing phase-locked circuit is correctly locked;

2) When the error locks the locking detection bit b of the second phase discriminator in the discrimination circuit ₀ And if the port voltage is less than or equal to 0.8V, judging that the in-loop mixing phase-locked loop is locked by mistake.

Further, in setting the phase detection frequency in step S2, divide by R =2, divide by n =40 is set, and in setting the phase detection frequency in step S3, divide by R =2, divide by n =70 is set.

The beneficial effects of the invention include:

(1) The circuit is simple and reliable: the mislock judging circuit can realize the mislock judging function only by using three parts of circuits, namely the power divider, the variable frequency divider and the lock detection, on the basis of the original frequency mixing phase locking circuit in the ring, has a simple structure, does not need complex circuit debugging, calculation and the like, and is simple and reliable.

(2) Wrong locking judgment is accurate and effective: the false lock judgment circuit realizes the false lock judgment by controlling the frequency dividing ratio, the locking detection window time and 2048 times of counting, and ensures the accuracy and the effectiveness because the false lock judgment standard is consistent with the phase-locked single-ring standard (the phase is continuously 2048 times in the window).

(3) The circuit has low cost, low power consumption, small volume and easy integration and use: the mislocking judging circuit is available for mature and available single-chip integrated circuits, the power consumption of the mislocking judging circuit does not exceed 100mw, cost, volume and power consumption evaluation are carried out in the integrated in-loop mixing phase-locked loop circuit, and mislocking judgment along with a main circuit in time is realized.

(4) The working frequency range is wide: the working frequency range of the false lock judging circuit is mainly limited by the working range of the frequency divider, the frequency divider integrated in the same type phase discriminator in the original ring internal mixed frequency phase locking circuit is used in the circuit, and the external frequency divider is added, so that the working frequency range can reach 26GHz, and the requirements of most false lock judging circuits can be met.

(5) The wrong lock judgment signal is easy to collect, and the real-time self-checking capability of the system is improved: the wrong lock judging signal output by the wrong lock judging circuit is a 2.7-3.3V voltage signal, when the wrong lock judging circuit is applied to a system, the system state acquisition board card or a superior circuit can directly receive the wrong lock judging signal, and whether the circuit is in wrong lock or not can be detected in real time according to the wrong lock judging signal, so that the fault self-checking capability of the system is greatly improved.

In summary, in the technical scheme of the present invention, by combining the frequency divider with continuously variable division ratio (integer and decimal division) and the time window counter, and by reasonably setting the division ratio, the number of times that the VCO division signal and the reference division signal fall in the window time together is continuously counted, so as to determine whether the in-loop mixing phase-locked loop locking signal belongs to the mislocking signal, thereby realizing effective determination of the mislocking signal, providing a basis for timely triggering relocking after mislocking, avoiding the problem that the output signal is wrong due to ineffective detection after mislocking, and improving the reliability of the in-loop mixing phase-locked loop.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic block diagram of a single loop phase locked loop and its lock indication decision;

FIG. 2 is a schematic block diagram of an in-loop mixer-phase-locked loop and a single lock indication decision;

FIG. 3 is a graph of the relationship between the in-loop mixing PLL feedback signal and the PLL output signal;

FIG. 4 is a block diagram of an in-loop mixer PLL and a circuit false lock determination circuit according to an embodiment of the present invention;

FIG. 5 is an active loop filter according to an embodiment of the present invention;

fig. 6 is an overall circuit diagram of an embodiment of the present invention.

Detailed Description

All features disclosed in all embodiments in this specification, or all methods or process steps implicitly disclosed, may be combined and/or expanded, or substituted, in any way, except for mutually exclusive features and/or steps.

In view of the technical problems in the background, after further analysis, the inventor of the present invention considers that there is a specific reason for the determination of the lock error as shown in fig. 3, and as can be seen from fig. 2 and 3, the in-loop mixing phase-locked loop is in θ ₁ (t), divide by R, divide by N, and theta _VCO (t) after the associated parameter is determined, the output signal θ is finally locked _VCO (t) is only expected to be one signal, but in practice there are two possible θ' s _VCO (t) = signal ([ theta ]) _rf (t)-θ ₁ (t)]Or [ theta ] ₁ (t)-θ _rf (t)]) The two signals are mixed and then appear as the same signal theta at the RF end of the phase detector _rf (t) of (d). In this case, if only the internal lock determination circuit of the phase detector is used, both are locked by the determination signal according to the determination rule, which may cause a signal θ desired by us to be present _VCO (t)＝θ _rf (t)-θ ₁ (t), but in practice the circuit may latch in on θ _VCO (t)＝θ ₁ (t)-θ _rf (t) and the circuit still determines a correct lock, which presents the lock false determination condition described above.

In the application of the in-loop mixing phase-locked circuit, if the above-mentioned wrong locking occurs, the locking detection circuit of the in-loop mixing phase-locked circuit itself cannot be identified, and whether the circuit has the wrong locking can only be determined correctly by the following means:

1) And accessing the locked signal into a special instrument (a frequency spectrograph or signal frequency acquisition equipment) to read the frequency of the locking signal, and judging whether the signal is wrongly locked or correctly locked according to the actual read frequency value and a formula shown in figure 3. The method belongs to manual judgment, needs to be matched with a special instrument, is complex and low in efficiency, and is only suitable for a circuit debugging stage.

2) If the frequency of the signal output by the in-loop mixing phase-locking circuit is low (generally below 1 GHz), an AD acquisition circuit can be added in the application to acquire the frequency of the locking signal, so as to judge whether the signal is in error locking. The scheme needs to add a special AD acquisition and processing calculation circuit, increases the volume, efficiency and cost of the circuit, and has limited application frequency range.

3) If the frequency of the signal output by the in-loop mixer-phase-locked circuit is high (usually above 1 GHz), a frequency converter circuit is usually needed to convert the high-frequency signal to a low-frequency band (usually below 1 GHz), and the AD acquisition and processing calculation circuit in item 2 is used to determine whether the signal is in error lock. The scheme is more complex, a frequency conversion circuit, an AD acquisition circuit, a digital processing circuit and the like need to be added, the efficiency, the volume and the cost of the judgment circuit are far higher than those of an intra-loop mixing phase-locked circuit, and the engineering practicability is not achieved.

In view of the above, a simpler, convenient and practical auxiliary circuit is urgently needed in practical engineering application to correctly determine whether the in-loop mixer phase-locked circuit is correctly locked (identify a wrong lock), so as to provide guarantee for correct and reliable locking of the circuit.

In order to solve the technical problem, in the technical scheme of the invention, a VCO signal and a reference signal which are locked by an in-loop mixed frequency phase-locked loop are divided and divided by power respectively by combining a continuously variable frequency division ratio (integer and decimal frequency division) frequency divider and a time window counter, and the frequency of two paths of signals after frequency division falling into window time together is continuously counted, so that whether the signal locked by the in-loop mixed frequency phase-locked loop is correctly locked is judged, the problem that the signal cannot be effectively detected after being incorrectly locked is solved, and the invention has the characteristics of reliable mislocking judgment mechanism, simple circuit structure, easy integration realization and the like.

In a further embodiment, the present invention provides a circuit for determining an in-loop mixer-locked-loop signal frequency error lock, as shown in fig. 4, where solid arrows in fig. 4 indicate signal flow. The features of the respective components in fig. 4 are explained as follows.

The phase detector has the following characteristics: 1) An R frequency divider, a phase discrimination circuit, a CP circuit, an N frequency divider and a locking detection circuit are integrated inside; 2) The R frequency divider divides the frequency of a signal entering the REF end and then enters a phase identification circuit and a locking identification circuit; 3) The N frequency divider divides the frequency of a signal entering an RF end and then enters a phase discrimination circuit and a locking discrimination circuit; 4) The phase discrimination and CP circuit converts the phase difference information of the two paths of signals into a current value to be output.

The power divider has the following characteristics: and performing equal power distribution on the input signals according to the number of output paths.

The mixing has the following characteristics: 1) One path of VCO signal theta for power division output _VCO (t) and the insertion signal θ ₁ (t) entering an RF end after down-mixing; 2) Insertion signal theta ₁ (t) frequency dependent on VCO output frequency and mixed frequency θ _rf (t) determining; 3) The inserted signal phase noise level of the input mixing is generally required to be better than the feedback signal; 4) The mixing output may require the use of a filter.

The loop filter has the following characteristics: 1) The loop filter can be an active loop filter or a passive loop filter, and is specifically determined according to a tuning voltage required by the VCO and the highest voltage of the phase detector CP; 2) The loop filter circuit parameter value needs to be calculated and determined according to the technical index of the whole phase-locked loop.

The VCO has the following characteristics: 1) The sine wave signal with corresponding frequency can be output according to a given tuning voltage value; 2) The phase noise of the VCO output signal needs to meet design specification requirements.

The 1/2/4/8 variable frequency divider has the following characteristics: 1) According to the frequency of the VCO output signal and the working frequency band of the N frequency divider of the mislocking discriminator, the VCO signal output by power division can be subjected to direct connection, 1/2, 1/4 or 1/8 frequency division output; 2) The divider output may require the use of filters as required.

The false lock discriminator has the following characteristics: 1) An N frequency divider, an R frequency divider and a locking judging circuit are arranged in the locking circuit; 2) The partial circuit in the main integrated phase discriminator can be used for realization; 3) And dividing the frequency of the signal N input into the RF end and the frequency of the signal R input into the REF end, then entering a locking judgment circuit, fixing a locking judgment time window, recording the times that the time difference between the two is continuously smaller than the time window, and judging the locking state when the time difference reaches 2048 times.

The operation of the circuit for determining the mislocking of the in-loop mixer-locked loop signal is described below with reference to fig. 3.

Defining the output signal obtained by the in-loop mixing phase-locked loop as theta _VCO (t)＝θ _rf (t)+θ ₁ And (t), the control frequency division value of the variable frequency divider is 2.

Process 1: the REF signal theta _ref And (t) dividing the equiphase power into two paths for output, and respectively accessing the in-loop mixing phase-locked loop and the mislocking decision circuit as reference signals.

And (2) a process: outputting the VCO output signal theta _VCO And (t) dividing the equal phase power into three paths of outputs which are respectively used as a phase-locked output, a return mixing signal of the in-loop mixing phase-locked loop and a variable frequency divider input signal in the mislocking judging circuit.

And 3, process: one path of which is theta _VCO (t) and the insertion signal θ ₁ (t) after mixing and filtering, the signal is sent to a phase discriminator, and the R frequency division value in the loop filter and the phase discriminator is set as R ₁ The N frequency division value is N ₁ And other phase detector register parameters to cause the in-loop mixing phase-locked loop to lock, which indicates an output high level (circuit lock).

And 4, process 4: setting the R frequency division value in the false lock judgment circuit to be R ₁ The N frequency division value is N ₂ (value calculation see equation 1), when the in-loop mixer-locked phase-locked loop is locked, two cases occur:

a) When the VCO locks at the correct frequency, i.e. θ _VCO (t)＝θ _rf (t)+θ ₁ In the case of (t), N is set as shown in the formula 1 ₂ After the value is obtained, the signal frequencies of the two input ends of the locking judgment in the wrong locking judgment are the same and are homologous, and at the moment, after the detection time window is reasonably set, the locking judgment circuit can output high level to indicate that the in-loop mixing phase-locked loop is correctly locked.

b) When the VCO locking frequency is not correct, i.e. theta _VCO (t)＝θ ₁ (t)-θ _rf In the case of (t), N is set as shown in the formula 1 ₂ After the value is reached, the signal frequencies of the two input ends of the locking judgment are different in the wrong locking judgment, the detection time window is reasonably set at the moment, the two input ends of the locking judgment cannot continuously appear in the time window, and the locking judgment circuit can output low level to indicate that the in-loop mixing phase-locked loop is locked wrongly.

And (5) a process: the lock indication level (defined as b) of the fetch in-loop mixer PLL ₁ Bit) and a lock indication level (defined as b) in a false lock discrimination circuit ₀ Bit) when b ₁ b ₀ When =11, it represents that the output frequency of the in-loop mixing phase-locked loop is correctly locked; when b is ₁ b ₀ When =10, it represents that the output frequency of the in-loop mixing phase-locked loop is locked incorrectly; otherwise unlocked.

Two explanations are needed:

1. the R and N frequency dividers and the lock detection circuit are integrated in most phase-locked loop devices on the market at present, and the lock detection in the in-loop mixing and mis-lock judgment circuit directly uses the function integrated in the phase-locked loop devices.

2. The 1/2/4/8 variable frequency divider is added into the false lock judging circuit, so that when the output frequency of the VCO is considered to be greater than the N frequency division working frequency band in the false lock judging circuit, the output frequency of the VCO can be divided firstly, the signal frequency is reduced to the N frequency division working frequency band, and the specific frequency division ratio can be determined according to the output frequency of the VCO and the N frequency division working frequency band.

The technical scheme of the invention realizes the judgment of the mislocking of the in-loop mixing phase-locked signal by using the reference frequency and the VCO output frequency (each power is divided into one path for output) of the original in-loop mixing phase-locked loop and matching with an additional frequency division circuit and a locking judgment circuit on the basis of the traditional in-loop mixing phase-locked loop circuit, and has the following beneficial effects:

1) The circuit is simple and reliable: the mislock judging circuit can realize the mislock judging function only by using three parts of circuits, namely the power divider, the variable frequency divider and the lock detection, on the basis of the original frequency mixing phase locking circuit in the ring, has a simple structure, does not need complex circuit debugging, calculation and the like, and is simple and reliable.

2) Wrong locking judgment is accurate and effective: the false lock judgment circuit realizes the false lock judgment by controlling the frequency dividing ratio, the locking detection window time and 2048 times of counting, and ensures the accuracy and the effectiveness because the false lock judgment standard is consistent with the phase-locked single-ring standard (the phase is continuously 2048 times in the window).

3) The circuit has low cost, low power consumption, small volume and easy integration and use: the mislocking judging circuit is available for mature and available single-chip integrated circuits, the power consumption of the mislocking judging circuit does not exceed 100mw, cost, volume and power consumption evaluation are carried out in the integrated in-loop mixing phase-locked loop circuit, and mislocking judgment along with a main circuit in time is realized.

4) The working frequency range is wide: the working frequency range of the false lock judging circuit is mainly limited by the working range of the frequency divider, the frequency divider integrated in the same type phase discriminator in the original ring internal mixed frequency phase locking circuit is used in the circuit, and the external frequency divider is added, so that the working frequency range can reach 26GHz, and the requirements of most false lock judging circuits can be met.

5) The wrong lock judgment signal is easy to collect, and the real-time self-checking capability of the system is improved: the wrong lock judging signal output by the wrong lock judging circuit is a 2.7-3.3V voltage signal, when the wrong lock judging circuit is applied to a system, the system state acquisition board card or a superior circuit can directly receive the wrong lock judging signal, and whether the circuit is in wrong lock or not can be detected in real time according to the wrong lock judging signal, so that the fault self-checking capability of the system is greatly improved.

The method for judging the signal error locking of the in-loop mixing type phase-locked loop described based on the technical scheme of the embodiment of the invention develops circuit design. The peripheral configuration circuit of the device can be built according to a device manual and a reference circuit provided by a manufacturer, and detailed description is omitted. Four aspects of main device type selection, key signal and connection with the device, working process and test result are mainly described below.

1. Device model selection

a) The phase discriminator adopts HMC704LP4E, and its internal integrated circuits such as R frequency divider, phase discriminator, lock detection, N frequency divider and charge pump CP, and N frequency divider possesses decimal frequency division function, sets frequency division value through dividing R and N frequency, discriminates phase difference information in the phase discriminator after frequency division to the signal that gets into both, and converts to current output through CP. When the phase difference between the two signals is stable, the frequency of the output signals of the two frequency dividers is the same, the time difference of the two frequency-divided signals continuously falls in a time window set in the locking detection circuit, and when the time difference meets continuous 2048 times, a high level is output, and the VCO is judged to be correctly locked on the reference signal.

b) The VCO selects HMC6380LC4B, the output frequency is 8-16 GHz, and the tuning voltage is 0-23V.

c) The loop filter is in active form and the op-amp uses OPA211 airgr.

d) The mixer uses GNM3104.

e) The 1/2/4/8 variable frequency divider adopts HMC862ALP3E and the working frequency band is 0.1-15 GHz.

f) The mislock discrimination uses an R-divider, an N-divider and its lock detection part functional circuit integrated in HMC704LP 3E.

2. Emphasis signals and connections to devices

a) Reference signal theta _ref And (t) respectively connecting two paths of 100MHz signals generated by a constant-temperature crystal oscillator into XREFP (No. 19 pin) of two HMC704LP4E1 respectively through equal power division of a power divider 1.

b) The phase detection output signal A is led out from a CP (No. 16 pin) of the HMC704LP4E (2) and is connected to a loop filter. The tuning control voltage B is integrated by the loop filter and then connected to Vtune (pin 4) of HMC6380LC4B, as shown in fig. 6.

c) RFOUT (pin 15) output theta of HMC6380LC4B _VCO The (t) signal is divided into three paths by a power divider 2 with equal phase power, wherein one path is connected to an LO port of GNM3104 (a bare chip), and a mixing signal theta is inserted ₁ (t) accessing the RF port, low-pass filtering the output signal of the IF port to generate theta _rf (t) VCOIP (pin number 6) to HMC704LP4E (1).

d) Another path theta of the output of the power divider 2 _VCO (t) the signal is connected into RFIN (pin 2) of HMC862ALP3E, and the RFOUT (pin 11) output frequency division signal is low-pass filtered

Signal VCOIP (pin No. 6) to HMC704LP4E (2)

The built circuit is integrated, and a peripheral circuit irrelevant to the core idea of the technical scheme is omitted, and the figure is 6.

3. Working process

The operation of the embodiment is described below, and the control of each device is performed by default using the control method given in the device manual.

a) Setting a target frequency θ _VCO (t) =14GHz, insertion mixing signal frequency θ ₁ (t) =12GHz, and the insertion signal phase noise level is better than the feedback signal.

b) The method comprises the steps of controlling registers of an HMC704LP4E (1) in an in-loop mixing phase-locked circuit, setting the phase discrimination frequency to be 50MHz, namely R frequency division =2 and N frequency division =40, using a digital mode for locking detection, setting the detection window time to be 12.8ns, and adjusting a circuit to realize locking.

c) The method comprises the steps of controlling registers of an HMC704LP4E (2) in an error locking judging circuit, setting the phase discrimination frequency to be 50MHz, opening an internal front stage to divide by 2, namely R frequency division =2 and N frequency division =70, using a digital mode for locking detection, setting the detection window time to be 11ns, and controlling the HMC862ALP3E to divide by 2.

d) Lock detect bit b for HMC704LP4E (1) in-loop mixer-locked loop ₁ If =1 (port voltage ≧ 2.5V), the error lock determination circuit detects the bit b based on the lock detection of the HMC704LP4E (2) ₀ The states can be distinguished as follows:

1) When the error locking judges the locking detection bit b of HMC704LP4E (2) in the circuit ₀ When the voltage of the port is not less than 2.5V, the correct locking of the in-loop mixing phase-locked loop circuit can be judged, namely theta _VCO (t)＝14GHz；

2) When the error lock determination circuit has the lock detection bit b of HMC704LP4E (2) ₀ When the port voltage is not more than 0.8V, the error locking of the in-loop mixer-locked phase circuit can be judged, namely theta _VCO (t)＝10GHz。

4. Test results

It is verified through the above example experiment that when the in-loop mixer-phase lock circuit is properly locked, i.e., θ _VCO (t) =14GHz; test b Using a three-purpose Meter ₁ 、b ₀ The voltage values of the two locking detection bits are both 2.7V, namely b ₁ b ₀ =11; when the in-loop mixer-phase-locked circuit is mis-locked, i.e. theta _VCO (t) =10 GHz; test b Using a three-purpose Meter ₁ 、b ₀ Two lock detectionBit, b ₁ The voltage value is 2.7V,b ₀ The voltage value is 0.2V, i.e. b ₁ b ₀ =10; the above tests show that the method for judging the in-loop mixing phase-locked signal mislocking in the technical scheme of the invention can be realized and has obvious beneficial effects.

It should be noted that the following embodiments can be combined and/or expanded, replaced in any way that is logical in any way from the above detailed description, such as the technical principles disclosed, the technical features disclosed or the technical features implicitly disclosed, etc., within the scope of protection defined by the claims of the present invention.

Example 1

A circuit for judging the frequency error locking of in-loop mixing phase-locked loop signal includes the first power divider, in-loop mixing phase-locked loop and error locking judging circuit, which is used to judge the REF signal theta _ref (t) dividing two paths of output by a first power divider with equal phase power, and respectively accessing an in-loop mixing phase-locked loop and a wrong lock judgment circuit as reference signals;

the in-loop mixing phase-locked loop comprises a phase discriminator, a loop filter, a VCO (voltage controlled oscillator), a second power divider and a mixer, and outputs a VCO output signal theta _VCO (t) dividing three paths of output by a second power divider with equal phase power, and respectively using the three paths of output as phase-locked output, a return mixing signal of an in-loop mixing phase-locked loop and a variable frequency divider input signal in a mislocking judgment circuit; one path of which is theta _VCO (t) and the insertion signal θ ₁ (t) after signal mixing and filtering, sending the signal into a phase discriminator;

the mislock judging circuit comprises a variable frequency divider and a mislock discriminator, wherein the variable frequency divider performs frequency division processing on a VCO output signal output by power division and outputs the VCO output signal to the mislock discriminator.

Example 2

On the basis of embodiment 1, the output signal obtained by the in-loop mixing phase-locked loop is defined as theta _VCO (t)＝θ _rf (t)+θ ₁ (t), the control frequency division value of the variable frequency divider is 2;

in the in-loop mixing phase-locked loop, the R frequency division value in the loop filter and the phase discriminator is set as R ₁ The N frequency division value is N ₁ And other phase detector registersParameters enable the in-loop mixing phase-locked loop to be locked, and the phase discriminator is locked to indicate and output high level;

in the false lock judging circuit, the frequency division value R in the false lock judging circuit is also set to be R ₁ The N frequency division value is N ₂ When the in-loop mixer-locked phase-locked loop is locked, two situations occur:

a) When the VCO locks at the correct frequency, i.e. θ _VCO (t)＝θ _rf (t)+θ ₁ At time (t), N is set by the formula (1) ₂ After the value is obtained, the signal frequencies of two input ends of the locking detection in the false locking judgment are the same and are in same source coherence, and then after a detection time window is reasonably set, the locking judgment circuit outputs high level to indicate that the in-loop mixing phase-locked loop is correctly locked;

b) When the VCO locking frequency is not correct, i.e. theta _VCO (t)＝θ ₁ (t)-θ _rf At (t), N is set by the formula (1) ₂ After the value is reached, the signal frequencies of two input ends of the locking detection are different in the false lock judgment, at the moment, a locking detection time window is reasonably set, the two input ends of the locking detection time window cannot continuously appear in the locking detection time window, and the locking judgment circuit can output low level to indicate that the in-loop mixing phase-locked loop is locked in error;

wherein, theta _div (t) is the variable divider output signal;

the locking indication level of the mixer-PLL in the fetch loop is defined as b ₁ The lock indication level in the bit-sum false lock discrimination circuit is defined as b ₀ Bit when b ₁ b ₀ When =11, it represents that the output frequency of the in-loop mixing phase-locked loop is correctly locked; when b is ₁ b ₀ When =10, it represents that the output frequency of the in-loop mixing phase-locked loop is locked incorrectly; otherwise unlocked.

Example 3

On the basis of the embodiment 1, the phase discriminator comprises an R frequency divider, a phase discrimination circuit, a CP circuit, an N frequency divider and a locking detection circuit, wherein the R frequency divider divides the frequency of a signal entering a REF end and then enters the phase discrimination circuit and the locking detection circuit, the N frequency divider divides the frequency of the signal entering an RF end and then enters the phase discrimination circuit and the locking detection circuit, and the phase discrimination circuit and the CP circuit convert phase difference information of the two paths of signals into a current value to be output.

Example 4

On the basis of embodiment 1, the mixer divides the power into one path of VCO signal θ _VCO (t) and the insertion signal θ ₁ (t) after down-mixing, entering the RF end of the phase discriminator; insertion signal theta ₁ (t) frequency dependent on VCO output frequency and mixed frequency θ _rf (t) determining that the phase noise level of the input mixed insertion signal is better than the feedback signal.

Example 5

On the basis of embodiment 1, the loop filter comprises an active or passive loop filter.

Example 6

On the basis of embodiment 1, the VCO outputs a sine wave signal of a corresponding frequency according to a given tuning voltage value.

Example 7

On the basis of the embodiment 1, the variable frequency divider comprises a 1/2/4/8 variable frequency divider, and the VCO signal output by power division is directly output, and is output by 1/2, 1/4 or 1/8 frequency division according to the frequency of the VCO output signal and the working frequency band of the N frequency divider of the mislocking discriminator.

Example 8

On the basis of embodiment 1, the mislock discriminator includes an N frequency divider, an R frequency divider, and a lock detection circuit, and divides the frequency of the signal input to the RF end of the mislock discriminator by N and the frequency of the signal input to the REF end of the mislock discriminator by R, and then enters the lock detection circuit, and fixes the lock discrimination time window, and records the number of times that the time difference between the two is continuously smaller than the set time window, and can determine that the lock is performed when 2048 times are reached.

Example 9

A method for determining an in-loop mixer-locked loop signal frequency mislocking, based on the circuit for determining an in-loop mixer-locked loop signal frequency mislocking as described in any of embodiments 1 to 9, comprising the steps of:

s1, setting a target frequency theta _VCO (t) inserting the mixing signal frequency θ ₁ (t) the insertion signal phase noise level is better than the feedback signal;

s2, controlling each register of a phase discriminator in the in-loop mixing phase-locked circuit, setting the phase discrimination frequency, using a digital mode for locking detection, setting detection window time, and adjusting a circuit to realize locking;

s3, controlling each register of a second phase discriminator in the false locking judging circuit, setting the phase discrimination frequency, opening an internal preceding stage for frequency division by 2, locking detection using a digital mode, setting detection window time, and controlling VCO (voltage controlled oscillator) to be frequency division by 2;

s4, when the locking detection bit b of the first phase discriminator in the in-loop mixing phase-locked circuit ₁ If =1, the circuit is judged according to the locking detection bit b of the second phase discriminator in the false locking judgment circuit ₀ The state is distinguished as follows:

1) When the error locks the locking detection bit b of the second phase discriminator in the discrimination circuit ₀ If the port voltage is larger than or equal to 2.5V, judging that the in-loop mixing phase-locked circuit is correctly locked;

2) When the error locks the locking detection bit b of the second phase discriminator in the discrimination circuit ₀ And if the port voltage is less than or equal to 0.8V, judging that the in-loop mixing phase-locked loop is locked by mistake.

Example 10

On the basis of embodiment 1, in setting the phase detection frequency in step S2, divide by R =2 and divide by n =40 are set, and in setting the phase detection frequency in step S3, divide by R =2 and divide by n =70 are set.

The units described in the embodiments of the present invention may be implemented by software, or may be implemented by hardware, and the described units may also be disposed in a processor. Wherein the names of the elements do not in some way constitute a limitation on the elements themselves.

According to an aspect of an embodiment of the present invention, there is provided a computer program product or a computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the method provided in the various alternative implementations described above.

As another aspect, an embodiment of the present invention further provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may be separate and not incorporated into the electronic device. The computer readable medium carries one or more programs which, when executed by an electronic device, cause the electronic device to implement the method described in the above embodiments.

The parts not involved in the present invention are the same as or can be implemented using the prior art.

The above-described embodiment is only one embodiment of the present invention, and it will be apparent to those skilled in the art that various modifications and variations can be easily made based on the application and principle of the present invention disclosed in the present application, and the present invention is not limited to the method described in the above-described embodiment of the present invention, so that the above-described embodiment is only preferred, and not restrictive.

Other embodiments than the above examples may be devised by those skilled in the art based on the foregoing disclosure, or by adapting and using knowledge or techniques of the relevant art, and features of various embodiments may be interchanged or substituted and such modifications and variations that may be made by those skilled in the art without departing from the spirit and scope of the present invention are intended to be within the scope of the following claims.

Claims (10)

1. A circuit for judging the frequency error locking of the in-loop mixing phase-locked loop signal is characterized by comprising a first power divider, an in-loop mixing phase-locked loop and an error locking judging circuit, wherein the in-loop mixing phase-locked loop judges a REF signal theta _ref (t) dividing two paths of output by a first power divider with equal phase power, and respectively accessing an in-loop mixing phase-locked loop and a wrong lock judgment circuit as reference signals;

in the ringThe frequency mixing phase-locked loop comprises a phase discriminator, a loop filter, a VCO, a second power divider and a frequency mixer, and outputs a VCO output signal theta _VCO (t) dividing three paths of output by a second power divider with equal phase power, and respectively using the three paths of output as phase-locked output, a return mixing signal of an in-loop mixing phase-locked loop and a variable frequency divider input signal in a mislocking judgment circuit; one path of which is theta _VCO (t) and the insertion signal θ ₁ (t) after signal frequency mixing and filtering, sending the signal to a phase discriminator;

the mislock judgment circuit comprises a variable frequency divider and a mislock discriminator, wherein the variable frequency divider performs frequency division processing on a VCO output signal output by the power divider and outputs the VCO output signal to the mislock discriminator.

2. The circuit for determining in-loop mixing PLL signal frequency false lock of claim 1,

defining the output signal obtained by the in-loop mixing phase-locked loop as theta _VCO (t)＝θ _rf (t)+θ ₁ (t), the control frequency division value of the variable frequency divider is 2;

in the in-loop mixing phase-locked loop, the R frequency division value in the loop filter and the phase discriminator is set as R ₁ The N frequency division value is N ₁ And other phase discriminator register parameters, so that the in-loop mixing phase-locked loop is locked, and the phase discriminator locking indication outputs high level;

in the false lock judging circuit, the R frequency division value in the false lock judging circuit is set to be R ₁ The N frequency division value is N ₂ When the in-loop mixer-locked phase-locked loop is locked, two situations occur:

a) When the VCO locks at the correct frequency, i.e. θ _VCO (t)＝θ _rf (t)+θ ₁ At time (t), N is set by the formula (1) ₂ After the value is obtained, the signal frequencies of the two input ends of the locking detection in the wrong locking judgment are the same and are homologous, and then after a detection time window is reasonably set, the locking judgment circuit can output high level to indicate that the in-loop mixing phase-locked loop is correctly locked;

b) When the VCO locking frequency is not correct, i.e. theta _VCO (t)＝θ ₁ (t)-θ _rf At time (t), N is set by the formula (1) ₂ After the value is counted, the lock is mistakenIn the judgment, the signal frequencies of the two input ends of the locking detection are different, a detection time window is reasonably set at the moment, the two input ends of the locking detection cannot continuously appear in the detection time window, and the locking judgment circuit can output low level to indicate that the in-loop mixing phase-locked loop is locked wrongly;

wherein, theta _div (t) is the variable divider output signal;

the locking indication level of the mixer-PLL in the fetch loop is defined as b ₁ The lock indication level in the bit-sum false lock discrimination circuit is defined as b ₀ Bit when b ₁ b ₀ When =11, it represents that the output frequency of the in-loop mixing phase-locked loop is correctly locked; when b is ₁ b ₀ When =10, it represents that the output frequency of the in-loop mixing phase-locked loop is locked incorrectly; otherwise unlocked.

3. The circuit for determining the frequency error locking of the in-loop mixing phase-locked loop signal according to claim 1, wherein the phase detector comprises an R frequency divider, a phase detector circuit, a CP circuit, an N frequency divider, and a lock detector circuit, the R frequency divider divides the frequency of the signal entering the REF terminal and then enters the phase detector circuit and the lock detector circuit, the N frequency divider divides the frequency of the signal entering the RF terminal and then enters the phase detector circuit and the lock detector circuit, and the phase detector circuit and the CP circuit convert the phase difference information of the two signals into a current value to be output.

4. The circuit for determining in-loop mixer-locked loop signal frequency error locking of claim 1, wherein the mixer divides the power of the output one of the VCO signals θ _VCO (t) and the insertion signal θ ₁ (t) after down-mixing, entering the RF end of the phase discriminator; insertion signal theta ₁ (t) frequency dependent on VCO output frequency and mixed frequency θ _rf (t) determining that the phase noise level of the input mixed insertion signal is better than the feedback signal.

5. The circuit for determining in-loop mixer-locked loop signal frequency mislocking of claim 1, wherein the loop filter comprises an active or passive loop filter.

6. The circuit for determining in-loop mixer-locked loop signal frequency mislocking of claim 1, wherein the VCO outputs a sine wave signal of a corresponding frequency according to a given tuning voltage value.

7. The circuit for determining in-loop mixing pll signal frequency false lock of claim 1, wherein the variable frequency divider comprises a 1/2/4/8 variable frequency divider, and the VCO signal with power division output is output by direct-through, 1/2, 1/4 or 1/8 frequency division according to the VCO output signal frequency and the operating frequency band of the N frequency divider of the false lock discriminator.

8. The circuit for determining the frequency error locking of the in-loop mixer-locked loop signal according to claim 1, wherein the mislock discriminator comprises an N-divider, an R-divider, and a lock detection circuit, wherein the N-divider divides a frequency of the signal input to the RF terminal of the mislock discriminator by N and the R-divider divides a frequency of the signal input to the REF terminal of the mislock discriminator by R, and then the lock detection circuit determines that the lock is performed when the lock determination time window is fixed, and records the number of times that the time difference between the two is continuously smaller than the set time window, and the lock is determined when 2048 times is reached.

9. A method for determining the frequency error locking of a signal of an in-loop mixer-locked loop, based on the circuit for determining the frequency error locking of a signal of an in-loop mixer-locked loop as claimed in any one of claims 1 to 9, comprising the steps of:

s1, setting a target frequency theta _VCO (t) inserting the mixing signal frequency θ ₁ (t), the insertion signal phase noise level is better than the feedback signal;

s2, controlling each register of a phase discriminator in the in-loop mixing phase-locked circuit, setting the phase discrimination frequency, using a digital mode for locking detection, setting the time of a detection window, and adjusting a circuit to realize locking;

s3, controlling each register of a second phase discriminator in the false locking judging circuit, setting the phase discrimination frequency, opening an internal preceding stage for frequency division by 2, locking detection using a digital mode, setting detection window time, and controlling VCO (voltage controlled oscillator) to be frequency division by 2;

s4, when the locking detection bit b of the first phase discriminator in the in-loop mixing phase-locked circuit ₁ If =1, the circuit is judged according to the locking detection bit b of the second phase discriminator in the false locking judgment circuit ₀ The state is distinguished as follows:

1) When the error locks the locking detection bit b of the second phase discriminator in the discrimination circuit ₀ If the port voltage is larger than or equal to 2.5V, judging that the in-loop mixing phase-locked circuit is correctly locked;

2) When the error locks the locking detection bit b of the second phase discriminator in the discrimination circuit ₀ And if the port voltage is less than or equal to 0.8V, judging that the in-loop mixing phase-locked loop is locked by mistake.

10. The method of determining in-loop mixer-locked loop signal frequency false lock of claim 1, wherein in step S2 setting the phase detection frequency, divide by R =2,divide by n =40 is set, and in step S3 setting the phase detection frequency, divide by R =2,divide by n =70 is set.

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