CN115940882B

CN115940882B - Multiplexing error correction circuit and method in high-pass mode and low-pass mode

Info

Publication number: CN115940882B
Application number: CN202310076283.7A
Authority: CN
Inventors: 李闻界; 管逸; 耿鹏飞
Original assignee: Shanghai Taorun Semiconductor Co ltd
Current assignee: Shanghai Taorun Semiconductor Co ltd
Priority date: 2023-02-08
Filing date: 2023-02-08
Publication date: 2023-05-05
Anticipated expiration: 2043-02-08
Also published as: CN115940882A

Abstract

The invention discloses a multiplexing error correction circuit and a method under a high-pass mode and a low-pass mode, wherein the circuit comprises a high-pass/low-pass filtering module, a high-pass filtering module and a low-pass filtering module, wherein the high-pass/low-pass filtering module is used for carrying out high-pass filtering on an input signal when a spurious spectrum of a spurious wave signal is in a high frequency and carrying out low-pass filtering when the spurious spectrum is in a low frequency; the time sequence path/direct current bias module is used for outputting a clock signal subjected to level shift when the stray wave signal is in a high-frequency state and outputting a direct current bias signal when the stray wave signal is in a low-frequency state; the frequency mixing amplifying module is respectively connected with the high-pass/low-pass filtering module and the time sequence path/direct current bias module and is used for mixing an input signal at a high frequency to a low frequency when receiving the high-pass filtering signal and the clock signal and amplifying the input signal at the low frequency when receiving the low-pass filtering signal and the direct current bias signal. The invention realizes the functions of screening and mixing frequency amplifying high and low frequency stray wave signals, reduces the chip size and reduces the chip cost.

Description

Multiplexing error correction circuit and method in high-pass mode and low-pass mode

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a multiplexing error correction circuit and method in a high-pass mode and a low-pass mode.

Background

In high-speed optical communication design, a time domain interleaving mode is often required to improve the speed of signals, and the difficulty of the time domain interleaving technology is that the clocks of multiple channels are synchronized, when the clocks between the channels have phase errors, the output signals of the transmitting end can show nonlinearities, and the nonlinearities can be reflected as spurious of specific frequencies in the frequency domain.

In order to eliminate the phase error between the detection channels and avoid the interference of the stray wave signals, a low-pass filter is needed to suppress the interference of the high-frequency stray wave signals, and a high-pass filter is needed to suppress the interference of the low-frequency stray wave signals, and the low-frequency stray wave signals are amplified by using an amplifier, and are mixed to low frequency by using a mixer and provide gain, so that a post-stage module is convenient for carrying out quantization processing on the stray wave signals, therefore, the high-pass filter is needed to integrate the low-pass filter in a chip to respectively filter the stray wave signals, and the mixer and the amplifier are integrated to carry out corresponding processing.

Therefore, a multiplexing error correction circuit in a high-pass mode and a low-pass mode is needed at present, and the chip size and the chip cost are reduced while the functions of screening and mixing amplification of high-frequency and low-frequency stray wave signals are realized.

Disclosure of Invention

In order to solve the technical problem that the chip size and cost are affected by eliminating the phase error between detection channels, the invention provides a multiplexing error correction circuit and method in a high-pass mode and a low-pass mode, and the specific technical scheme is as follows:

the invention provides a multiplexing error correction circuit in a high-pass mode and a low-pass mode, which comprises the following components:

the high-pass/low-pass filtering module is used for receiving a stray wave signal and an input signal, carrying out high-pass filtering on the input signal when the stray spectrum of the stray wave signal is at a high frequency, and carrying out low-pass filtering on the input signal when the stray spectrum of the stray wave signal is at a low frequency;

the time sequence path/direct current bias module is used for receiving a clock signal, a direct current bias signal and an enabling signal representing the high-low frequency state of the stray wave signal, outputting the clock signal subjected to level shift when the stray wave signal is in the high-frequency state, and outputting the direct current bias signal when the stray wave signal is in the low-frequency state;

the frequency mixing amplifying module is respectively connected with the high-pass/low-pass filtering module and the time sequence path/direct current bias module and is used for inhibiting a low-frequency interference signal and mixing the input signal at a high frequency to a low frequency when receiving the high-pass filtering signal and the clock signal, and inhibiting the high-frequency interference and amplifying the input signal at a low frequency when receiving the low-pass filtering signal and the direct current bias signal.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode provided by the invention realizes the effects of high-frequency filtering and mixing the high-frequency signal to a low frequency position when receiving the high-frequency signal, and low-frequency filtering and signal amplification when receiving the low-frequency signal through module multiplexing, so that the influence of a stray wave signal on the communication effect of a chip is avoided, the chip size is reduced, and the chip cost is reduced.

In some embodiments, the high/low pass filtering module includes a first high/low pass filtering unit, the first high/low pass filtering unit includes two first differential branches that are arranged in a mirror image and receive different differential input signals, and each first differential branch includes:

a grounding switch;

a first filter capacitor;

a first filter resistor;

the grid electrode of the first PMOS tube is connected with the stray wave signal input end;

the grid electrode of the second PMOS tube is connected with the common mode signal input end;

the grid electrode of the third PMOS tube is connected with an externally input bias voltage signal input end;

the input end of the differential input signal is respectively connected with the first end of the first PMOS tube and the first end of the third PMOS tube, the second end of the first PMOS tube is respectively connected with the first end of the second PMOS tube and the first end of the first filter resistor, the second end of the first filter resistor is respectively connected with the first end of the first filter capacitor and the signal output end of the first differential branch, and the second end of the first filter capacitor is respectively connected with the second ends of the grounding switch and the third PMOS tube;

And the two first differential branches arranged in a mirror image mode are connected through the second end of the second PMOS tube.

The invention provides a multiplexing error correction circuit in a high-pass mode and a low-pass mode, and particularly discloses a circuit structure of a high-pass/low-pass filtering module, which realizes the technical effects of performing high-pass filtering on an input signal when a stray wave signal is in a high frequency and performing low-pass filtering on the input signal when the stray wave signal is in a low frequency.

In some embodiments, when the spurious spectrum of the stray wave signal is at a high frequency, the grounding switch is turned off, the gates of the second PMOS transistor and the third PMOS transistor are both at a low level, and the differential input signal is sequentially subjected to high frequency filtering by the third PMOS transistor and the first filter capacitor and then is output at the signal output end of the first differential branch;

when the stray frequency spectrum of the stray wave signal is in a low frequency, the grounding switch is closed, the grid electrodes of the second PMOS tube and the third PMOS tube are in a high level, and the differential input signal sequentially passes through the first PMOS tube and the first filter resistor, is subjected to low frequency filtering according to the first filter capacitor connected with the grounding switch, and is output at the signal output end of the first differential branch.

In some embodiments, the high/low pass filter module includes at least two first high/low pass filter units, and the differential input signal input terminal of the last first high/low pass filter unit is connected between the first filter capacitor and the first filter resistor in the previous first high/low pass filter unit.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode improves the filtering effect of the high-pass/low-pass filtering module by integrating a plurality of first high-pass/low-pass filtering units in the circuit structure of the high-pass/low-pass filtering module.

In some embodiments, the high/low pass filtering module includes at least one first high/low pass filtering unit and at least one second high pass filtering unit therein;

the differential input signal input end of the second high-pass filtering unit is connected between the first filter capacitor and the first filter resistor in the last high-pass/low-pass filtering unit;

the second high-pass filtering unit comprises two second differential branches which are arranged in a mirror image mode and receive different differential input signals, and each second differential branch comprises:

A second filter capacitor;

a second filter resistor;

the grid electrode of the fourth PMOS tube is connected with the stray wave signal input end;

the grid electrode of the fifth PMOS tube is connected with the common mode signal input end;

the input end of the differential input signal is connected with the first end of the second filter capacitor, the second end of the second filter capacitor is respectively connected with the first end of the second filter resistor and the signal output end of the second differential branch, the second end of the second filter resistor is connected with the first end of the fifth PMOS tube, and the fourth PMOS tube is connected in parallel with the two ends of the second filter capacitor;

and the two second differential branches arranged in a mirror image manner are connected through the second ends of the fifth PMOS tubes.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode provided by the invention sequentially integrates at least one first high-pass/low-pass filter unit and at least one second high-pass filter unit in the high-pass/low-pass filter module, and specifically discloses the circuit structures of the first high-pass/low-pass filter unit and the second high-pass filter unit, so that only high-pass filtering is carried out on signals filtered by a plurality of first high-pass/low-pass filter units, and the chip cost is further reduced under the condition of ensuring the filtering effect.

In some embodiments, when the spurious spectrum of the spurious wave signal is at a high frequency, the gate of the fifth PMOS transistor is at a low level, and the differential input signal is output at the signal output end of the second differential branch after being subjected to high frequency filtering by the second filter capacitor;

when the stray frequency spectrum of the stray wave signal is in a low frequency, the grid electrode of the fifth PMOS tube is in a high level, and the differential input signal is sequentially output at the signal output end of the second differential branch through the fifth PMOS tube.

In some embodiments, the gate voltage of the third PMOS transistor is kept constant by a gate voltage bootstrap branch, and the gate voltage bootstrap branch includes:

a gate voltage bootstrap capacitor;

a sixth PMOS tube;

the switching device comprises a first linkage switch, a second linkage switch, a third linkage switch and a fourth linkage switch, wherein the switching states of the first linkage switch and the second linkage switch are the same, and the switching states of the third linkage switch and the fourth linkage switch are the same;

the input end of the differential input signal is connected with the source electrode of the third PMOS tube, the input end of the differential input signal is connected with the grid electrode of the third PMOS tube sequentially through the first linkage switch, the grid voltage bootstrap capacitor and the second linkage switch, a first bias voltage signal input end is connected between the first linkage switch and the grid voltage bootstrap capacitor through the second linkage switch, a second bias voltage signal input end is connected between the grid voltage bootstrap capacitor and the second linkage switch through the sixth PMOS tube, and a third bias voltage signal input end is connected between the second linkage switch and the grid electrode of the third PMOS tube through the fourth linkage switch.

The invention provides a multiplexing error correction circuit in a high-pass mode and a low-pass mode, which discloses a grid voltage bootstrap branch structure connected to a third PMOS (P-channel metal oxide semiconductor) tube in a high-pass/low-pass filter module, and aims to prevent grid voltage bootstrap capacitance in the grid voltage bootstrap branch from being discharged due to electric leakage of the third PMOS tube, realize the technical effect of grid voltage stabilizing input of the third PMOS tube and inhibit nonlinearity of a signal transmission path in the high-pass/low-pass filter module.

In some embodiments, when the gate voltage bootstrapping branch is in a reset state, the first linkage switch and the second linkage switch are opened, the third linkage switch and the fourth linkage switch are closed, the gate of the first PMOS transistor is communicated with the third bias voltage signal input end, the first PMOS transistor is in an off state, and the charging voltages at the two ends of the gate voltage bootstrapping capacitor are the voltage of the first bias voltage signal input end and the voltage of the second bias voltage signal input end respectively;

when the grid voltage bootstrapping branch is in a working state, the first linkage switch and the second linkage switch are closed, the third linkage switch and the fourth linkage switch are opened, the grid electrode of the first PMOS tube is connected with the grid voltage bootstrapping capacitor in a discharging state, and the grid voltage bootstrapping capacitor is conducted with the sixth PMOS tube in the discharging state.

In some embodiments, the first PMOS transistor is a PMOS transistor with an adjustable cutoff frequency;

the filter coefficient of the first differential branch circuit changes along with the cut-off frequency change of the first PMOS tube.

In some embodiments, the timing path/dc offset module includes two third differential branches configured in a mirror image and receiving different differential timing signals, and each third differential branch includes:

a buffer, the input end of which receives the differential time sequence signal and the enabling signal;

the third capacitor is connected between the output end of the buffer and the signal output end of the third differential branch;

the common mode voltage signal input end is connected between the third capacitor and the signal output end of the third differential branch;

the third resistor is connected between the common-mode voltage signal input end and the signal output end of the third differential branch through the first node;

a fifth interlock switch connected between the third resistor and the first node;

the two third differential branches arranged in a mirror image mode are connected in parallel to the common-mode voltage signal input end, the first node in one third differential branch is also connected to a third bias voltage signal input end, and the first node in the other third differential branch is also connected to a fifth bias voltage signal input end;

A sixth linkage switch is arranged between the first node and the third bias voltage signal input end, and a seventh linkage switch is arranged between the first node and the grounding end.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode provided by the invention discloses a circuit structure of a third differential branch, which is used for carrying out level shift on clock input signals through a buffer and a third capacitor in the high-pass mode, and is convenient for realizing the functions of mixing and amplifying according to output signals of the circuit of the third differential branch through the effect of direct current bias signals output by a common-mode voltage signal input end in the low-pass mode.

In some embodiments, the buffer is enabled when the buffer receives the enable signal indicating that the stray wave signal is in a high frequency state, the fifth ganged switch is closed, the sixth ganged switch and the seventh ganged switch are both open, the differential timing signal is level-shifted through the buffer and the third capacitor, and the clock signal after the level shift is output at the signal output end of the third differential branch;

the buffer is blocked when the buffer receives the enabling signal representing that the stray wave signal is in a low frequency state, the fifth linkage switch is opened, the sixth linkage switch and the seventh linkage switch are both closed, one signal output end of the third differential branch circuit outputs a first direct current bias voltage signal, and the other signal output end of the third differential branch circuit outputs a second direct current bias voltage signal.

In some embodiments, the mixer amplifier module includes two fourth differential branches disposed in an image, and each fourth differential branch includes:

a fourth bias voltage signal input;

a seventh PMOS transistor, where a source of the seventh PMOS transistor is connected to the fourth bias voltage signal input end, and provides bias current for the fourth differential branch;

an eighth PMOS tube, the source of which is connected with the drain of the seventh PMOS tube, the grid of which is connected with the signal output end of the high-pass/low-pass filter module;

a ninth PMOS transistor, the source of which is connected to the drain of the eighth PMOS transistor, the gate of which is connected to the signal output end of the third differential branch in the timing path/dc bias module, and the drain of which is connected to the first signal output end of the fourth differential branch through a fourth resistor;

and the source stage of the tenth PMOS tube is connected with the drain electrode of the eighth PMOS tube, the grid electrode of the tenth PMOS tube is connected with the signal output end of the other third differential branch in the time sequence path/direct current bias module, the drain electrode of the tenth PMOS tube is connected with the fourth resistor in the other fourth differential branch in the mirror image setting, and the drain electrode of the tenth PMOS tube is connected with the first signal output end of the other fourth differential branch through the fourth resistor in the other fourth differential branch.

The invention provides a multiplexing error correction circuit in a high-pass mode and a low-pass mode, which particularly discloses a circuit structure diagram of a frequency mixing amplifying module.

In some embodiments, when the gate of the eighth PMOS transistor receives the high-pass filtered signal, the gates of the ninth PMOS transistor and the tenth PMOS transistor respectively receive the clock signals output by the signal output ends of the two third differential branches, and the fourth differential branch operates in a mixing mode;

when the grid electrode of the eighth PMOS tube receives the low-pass filtering signal, the grid electrode of the ninth PMOS tube receives the low-level direct-current bias signal, the grid electrode of the tenth PMOS tube receives the high-level direct-current bias signal, and the fourth differential branch circuit works in an amplifying mode.

In some embodiments, the fourth differential leg further comprises:

the drain electrode of the first NMOS tube is connected with the drain electrode of the eighth PMOS tube, the grid electrode of the first NMOS tube is connected with the pole voltage signal input end, and the source stage of the first NMOS tube is connected with the second signal output end of the fourth differential branch through a current source.

According to the multiplexing error correction circuit in the high-pass mode and the low-pass mode, the first NMOS tube is integrated in the operation of the fourth differential branch, so that the transconductance of the eighth PMOS tube is increased, and the gain effect of the fourth differential branch is further increased.

In some embodiments, according to another aspect of the present invention, the present invention further provides a method for correcting multiplexing errors in a high-pass mode and a low-pass mode, including the steps of:

receiving a stray wave signal and an input signal, performing high-pass filtering on the input signal when the stray spectrum of the stray wave signal is at a high frequency, and performing low-pass filtering on the input signal when the stray spectrum of the stray wave signal is at a low frequency;

receiving a clock signal, a direct current bias signal and an enabling signal, outputting the clock signal subjected to level shift when the stray wave signal is in a high-frequency state, and outputting the direct current bias signal when the stray wave signal is in a low-frequency state, wherein the enabling signal is used for representing the high-frequency and low-frequency states of the stray wave signal;

suppressing a low frequency interference signal and mixing the input signal at a high frequency to a low frequency while receiving a high pass filtered signal and the clock signal;

When receiving the low-pass filtered signal and the DC offset signal, high-frequency interference is suppressed and the input signal at low frequencies is amplified.

The multiplexing error correction circuit and method in the high-pass mode and the low-pass mode provided by the invention have at least one of the following technical effects:

(1) The same circuit is realized through module multiplexing, so that the effects of high-frequency filtering and mixing the high-frequency signal to a low-frequency position when receiving the high-frequency signal, and low-frequency filtering and signal amplification when receiving the low-frequency signal are realized, the influence of stray wave signals on the chip communication effect is avoided, the chip size is reduced, and the chip cost is reduced;

(2) The circuit structure of the high-pass/low-pass filtering module is particularly disclosed, so that the technical effect of high-pass filtering the input signal when the stray wave signal is at high frequency and low-pass filtering the input signal when the stray wave signal is at low frequency is realized;

(3) The filtering effect of the high-pass/low-pass filtering module is improved by integrating a plurality of first disclosed high-pass/low-pass filtering units in the circuit structure of the high-pass/low-pass filtering module;

(4) The high-pass/low-pass filter module is sequentially integrated with at least one first high-pass/low-pass filter unit and at least one second high-pass filter unit, and the circuit structures of the first high-pass/low-pass filter unit and the second high-pass filter unit are specifically disclosed, so that only high-pass filtering is carried out on signals filtered by the plurality of first high-pass/low-pass filter units, and the chip cost is further reduced under the condition of ensuring the filtering effect;

(5) The grid voltage bootstrap branch structure of the third PMOS tube connected to the high-pass/low-pass filtering module is disclosed, the grid voltage bootstrap capacitor in the grid voltage bootstrap branch is prevented from being discharged due to electric leakage of the third PMOS tube, the technical effect of stabilizing voltage input of the grid electrode of the third PMOS tube is realized, and nonlinearity of a signal transmission path in the high-pass/low-pass filtering module is restrained;

(6) The circuit structure of the third differential branch is disclosed, so that the level shift of clock input signals is realized through a buffer and a third capacitor in a high-pass mode, and the effect of direct-current bias signals output by a common-mode voltage signal input end in a low-pass mode is realized, thereby being convenient for realizing the functions of mixing and amplifying according to the output signals of the circuit of the third differential branch;

(7) The circuit structure diagram of the frequency mixing amplifying module is disclosed, the frequency mixing and amplifying functions are integrated in the same frequency mixing amplifying module, the frequency mixing function is implemented in a high-pass mode, and the technical effect of the amplifying function is implemented in a low-pass mode;

(8) And the transconductance of the eighth PMOS tube is increased by integrating the first NMOS tube in the operation of the fourth differential branch, so that the gain effect of the fourth differential branch is increased.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it will be apparent that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a multiplexing error correction circuit in a high-pass mode and a low-pass mode according to the present invention;

FIG. 2 is a schematic diagram of a high/low pass filter module in a multiplexing error correction circuit in a high pass mode and a low pass mode according to the present invention;

FIG. 3 is a schematic diagram of a gate voltage bootstrap branch in a multiplexing error correction circuit in a reset state in a high-pass mode and a low-pass mode according to the present invention;

FIG. 4 is a schematic diagram of a gate voltage bootstrap branch in a multiplexing error correction circuit in a high-pass mode and a low-pass mode in an operating state according to the present invention;

FIG. 5 is a schematic diagram of a timing path/DC offset module in a multiplexing error correction circuit in a high-pass mode and a low-pass mode according to the present invention;

FIG. 6 is a schematic diagram of a mixer amplifier module in a multiplexing error correction circuit in a high-pass mode and a low-pass mode according to the present invention;

Fig. 7 is a flowchart of a method for multiplexing error correction in high-pass mode and low-pass mode according to the present invention.

Reference numerals in the drawings: the high-pass/low-pass filter module-100, the first high-pass/low-pass filter unit-110, the first differential branch-111, the second high-pass filter unit-120, the second differential branch-121, the time sequence path/direct current bias module-200, the third differential branch-210, the mixing amplifying module-300, the fourth differential branch-310, the grounding switch-S0, the gate voltage bootstrap capacitor-C, the first filter capacitor-C1, the second filter capacitor-C2, the third capacitor-C3, the first filter resistor-R1, the second filter resistor-R2, the third resistor-R3, the first PMOS tube-MP 1, the second PMOS tube-MP 2, the third PMOS tube-MP 3, the fourth PMOS tube-MP 4, the fifth PMOS tube-MP 5, the sixth PMOS tube-MP 6 the system comprises a seventh PMOS tube-MP 7, an eighth PMOS tube-MP 8, a ninth PMOS tube-MP 9, a tenth PMOS tube-MP 10, a first NMOS tube-MN 1, a first linkage switch-S1, a second linkage switch-S2, a third linkage switch-S3, a fourth linkage switch-S4, a fifth linkage switch-S5, a sixth linkage switch-S6, a seventh linkage switch-S7, a buffer-B1, an enable signal-EN, a common-mode voltage signal input end-VCM, an input end-Vin of a differential input signal in a grid voltage bootstrap branch, a first bias voltage signal input end-Vup, a second bias voltage signal input end-Vdn, a third bias voltage signal input end-V3 and a fourth bias voltage signal input end-V4.

Description of the embodiments

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

For the sake of simplicity of the drawing, the parts relevant to the present invention are shown only schematically in the figures, which do not represent the actual structure thereof as a product. Additionally, in order to facilitate a concise understanding of the drawings, components having the same structure or function in some of the drawings are depicted schematically only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.

In one embodiment of the present invention, as shown in fig. 1, the present invention provides a multiplexing error correction circuit in a high-pass mode and a low-pass mode, which includes a high-pass/low-pass filter module 100, a timing path/dc bias module 200, and a mixer amplifier module 300.

For example, when the sampling frequency of the transmitting end adopting the 8-channel time domain interleaving structure is fs and the signal frequency is fin, the frequency corresponding to the stray wave is n×fs/8±fin, where N is an integer between 0 and 8. Taking the example of a stray wave at fs/8-fin, the frequency of the stray wave approaches 0 when fin approaches fs/8; when fin is close to 0, the frequency of the stray wave is close to fs/8. For the former case, the multiplexing error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment is required to operate in the low-pass filter mode, so as to suppress the interference at the high frequency, and meanwhile, the spurious amplification at the low frequency is performed by using the amplifier, so that the spurious amplification is provided for the post-stage module to perform quantization processing; in the latter case, the multiplexing error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment is required to operate in a high-pass filter mode to suppress interference at a low frequency, and at the same time, a mixer is used to mix spurious frequencies at a high frequency to a low frequency and provide a certain gain to perform quantization processing for a later module.

The high-pass/low-pass filtering module 100 is configured to receive a stray wave signal and an input signal, perform high-pass filtering on the input signal when a stray spectrum of the stray wave signal is at a high frequency, and perform low-pass filtering on the input signal when the stray spectrum of the stray wave signal is at a low frequency.

The timing path/dc bias module 200 is configured to receive the clock signal, the dc bias signal, and an enable signal indicating a high-low frequency state of the stray wave signal, output the level shifted clock signal when the stray wave signal is in the high frequency state, and output the dc bias signal when the stray wave signal is in the low frequency state;

the mixing amplification module 300 is connected to the high/low pass filtering module 100 and the timing path/dc offset module 200, respectively, and is configured to suppress the low frequency interference signal and mix the input signal at the high frequency to the low frequency when receiving the high pass filtering signal and the clock signal, and suppress the high frequency interference signal and amplify the input signal at the low frequency when receiving the low pass filtering signal and the dc offset signal.

Illustratively, when fin is near 0, spurious spectra fs/8-fin are at high frequencies, the input signal is high pass filtered by the high pass/low pass filter module 100 to the filtered signal input of the mixer amplifier module 300, the clock of frequency fs/8 in the timing path/dc offset module 200 reaches the signal input of the mixer amplifier module 300, the mixer amplifier module 300 suppresses low frequency interference signals and mixes the input signal at high frequencies to low frequencies;

When fin is close to fs/8, the spurious spectrum fs/8-fin is at low frequency, the input signal is low-pass filtered by the high-pass/low-pass filtering module 100 to reach the filtering signal input end of the mixing amplifying module 300, the clock path with fs/8 frequency in the time sequence path/direct current offset module 200 is turned off, the time sequence path/direct current offset module 200 provides direct current offset voltage to reach the signal input end of the mixing amplifying module 300, and the mixing amplifying module 300 suppresses high-frequency interference and amplifies the input signal at low frequency.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode provided by the embodiment realizes the effects of high-frequency filtering and mixing the high-frequency signal to a low-frequency position when receiving the high-frequency signal, and low-frequency filtering and signal amplification when receiving the low-frequency signal through module multiplexing, so that the influence of the stray wave signal on the chip communication effect is avoided, the chip size is reduced, and the chip cost is reduced.

In one embodiment, as shown in fig. 2, the high-pass/low-pass filtering module 100 includes a first high-pass/low-pass filtering unit 110, where the first high-pass/low-pass filtering unit 110 includes two first differential branches that are arranged in a mirror image and receive different differential input signals, and each first differential branch includes a ground switch S0, a first filter capacitor C1, a first filter resistor R1, a first PMOS transistor MP1, a second PMOS transistor MP2, and a third PMOS transistor MP3.

The grid electrode of the first PMOS tube MP1 is connected with the stray wave signal input end, the grid electrode of the second PMOS tube MP2 is connected with the common mode signal input end, the grid electrode of the third PMOS tube MP3 is connected with the bias voltage signal input end which is input externally, the input end of the differential input signal is respectively connected with the first end of the first PMOS tube MP1 and the first end of the third PMOS tube MP3, the second end of the first PMOS tube MP1 is respectively connected with the first end of the second PMOS tube MP2 and the first end of the first filter resistor R1, the second end of the first filter resistor R1 is respectively connected with the first end of the first filter capacitor R1 and the signal output end of the first differential branch, the second end of the first filter capacitor C1 is respectively connected with the second end of the grounding switch S0 and the second end of the third PMOS tube MP3, and the two first differential branches arranged in a mirror image are connected with the second end of the second PMOS tube MP 2.

Specifically, when the spurious spectrum of the stray wave signal is at a high frequency, the grounding switch S0 is controlled to be turned off in a numerical control mode, the grid electrode of the second PMOS tube MP2 and the grid electrode of the third PMOS tube MP3 are both at a low level, the first PMOS tube MP1 is turned off, the second PMOS tube MP2 and the third PMOS tube MP3 are turned on, and the differential input signal is output at the signal output end of the first differential branch after being subjected to high frequency filtering sequentially through the third PMOS tube MP3 and the first filter capacitor C1.

When the stray spectrum of the stray wave signal is in low frequency, the grounding switch S0 is controlled to be closed in a numerical control mode, the grid electrode of the second PMOS tube MP2 and the grid electrode of the third PMOS tube MP3 are both in high level, the first PMOS tube MP1 is conducted, the second PMOS tube MP2 and the third PMOS tube MP3 are cut off, the differential input signal sequentially passes through the first PMOS tube MP1 and the first filter resistor R1, and is output at the signal output end of the first differential branch after being subjected to low frequency filtration according to the first filter capacitor C1 connected with the grounding switch S0.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode specifically discloses a circuit structure of a high-pass/low-pass filtering module, and achieves the technical effects of performing high-pass filtering on an input signal when a stray wave signal is high frequency and performing low-pass filtering on the input signal when the stray wave signal is low frequency.

In one embodiment, as shown in fig. 2, the high-pass/low-pass filter module 100 includes at least two first high-pass/low-pass filter units 110, and the differential input signal input terminal of the following first high-pass/low-pass filter unit 110 is connected between the first filter capacitor C1 and the first filter resistor R1 in the preceding first high-pass/low-pass filter unit 110.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment improves the filtering effect of the high-pass/low-pass filtering module by integrating a plurality of first disclosed high-pass/low-pass filtering units in the circuit structure of the high-pass/low-pass filtering module.

In one embodiment, as shown in fig. 2, the high-pass/low-pass filtering module 100 includes at least one first high-pass/low-pass filtering unit 110 and at least one second high-pass filtering unit 120, and a differential input signal input end of the second high-pass filtering unit 120 is connected between a first filter capacitor C1 and a first filter resistor R1 in the last first high-pass/low-pass filtering unit 110, where the second high-pass filtering unit 120 includes two second differential branches that are arranged in a mirror image and receive different differential input signals, and each second differential branch includes a second filter capacitor C2, a second filter resistor R2, a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5.

The grid electrode of the fourth PMOS tube MP4 is connected with the stray wave signal input end, the grid electrode of the fifth PMOS tube MP5 is connected with the common mode signal input end, the input end of the differential input signal is connected with the first end of the second filter capacitor C2, the second end of the second filter capacitor C2 is respectively connected with the first end of the second filter resistor R2 and the signal output end of the second differential branch, the second end of the second filter resistor R2 is connected with the first end of the fifth PMOS tube MP5, the fourth PMOS tube MP4 is connected in parallel with the two ends of the second filter capacitor C2, and the two second differential branches arranged in a mirror image mode are connected through the second end of the fifth PMOS tube MP5.

Specifically, when the spurious spectrum of the spurious signal is at high frequency, the gate of the fifth PMOS transistor MP5 is at low level, and the differential input signal is subjected to high-pass filtering by the first high-pass/low-pass filtering unit 110, then subjected to high-frequency filtering by the second filter capacitor C2 in the second high-pass/low-pass filtering unit 120, and then output at the signal output end of the second differential branch.

When the spurious spectrum of the spurious wave signal is at a low frequency, the gate of the fifth PMOS transistor MP5 is at a high level, and the differential input signal is output at the signal output end of the second differential branch directly through the fifth PMOS transistor MP5 after being subjected to low-pass filtering by the first high-pass/low-pass filtering unit 110.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode provided in this embodiment sequentially integrates at least one first high-pass/low-pass filter unit and at least one second high-pass filter unit in the high-pass/low-pass filter module, and specifically discloses circuit structures of the first high-pass/low-pass filter unit and the second high-pass filter unit, and only performs high-pass filtering on signals filtered by the plurality of first high-pass/low-pass filter units, so that chip cost is further reduced under the condition of ensuring filtering effects.

In one embodiment, as shown in fig. 3 and fig. 4, the gate voltage of the third PMOS transistor MP3 is kept constant by a gate voltage bootstrap branch, and the gate voltage bootstrap branch includes a gate voltage bootstrap capacitor C, a sixth PMOS transistor MP6, a first linkage switch S1, a second linkage switch S2, a third linkage switch S3, and a fourth linkage switch S4.

The switching states of the first linkage switch S1 and the second linkage switch S2 controlled by numerical control are the same, the switching states of the third linkage switch S3 and the fourth linkage switch S4 are the same, an input end Vin of a differential input signal in a grid voltage bootstrap branch is connected with a source electrode of a third PMOS tube MP3, the input end Vin of the differential input signal in the grid voltage bootstrap branch is also connected with a grid electrode of the third PMOS tube MP3 sequentially through the first linkage switch S1, a grid voltage bootstrap capacitor C and the second linkage switch S2, a first bias voltage signal input end Vup is connected between the first linkage switch S1 and the grid voltage bootstrap capacitor C through the second linkage switch S2, a second bias voltage signal input end Vdn is connected between the grid voltage bootstrap capacitor C and the second linkage switch S2 through a sixth PMOS tube MP6, and a third bias voltage signal input end VDD is connected between the second linkage switch S2 and the grid electrode of the third PMOS tube MP3 through the fourth linkage switch S4.

Specifically, as shown in fig. 3, when the gate voltage bootstrapping branch is in a reset state, the first linkage switch S1 and the second linkage switch S2 are opened, the third linkage switch S3 and the fourth linkage switch S4 are closed, the gate of the first PMOS transistor MP1 is communicated with the third bias voltage signal input end VDD, the first PMOS transistor MP1 is in an off state, and the charging voltages at the two ends of the gate voltage bootstrapping capacitor C are the voltage of the first bias voltage signal input end Vup and the voltage of the second bias voltage signal input end Vdn, respectively, so that the charging voltage of the gate voltage bootstrapping capacitor C is Vup-Vdn;

as shown in fig. 4, when the gate voltage bootstrap branch is in an operating state, the first linkage switch S1 and the second linkage switch S2 are closed, the third linkage switch S3 and the fourth linkage switch S4 are opened, the gate of the first PMOS transistor MP1 is connected with the gate voltage bootstrap capacitor C in a discharging state, the gate voltage bootstrap capacitor C in the discharging state is conducted with the sixth PMOS transistor MP6, the upper plate voltage of the gate voltage bootstrap capacitor C is Vin, the initial voltage of the lower plate is Vin-vup+vdn, therefore, the absolute value of the gate-source voltage of the first PMOS transistor MP1 is Vup-Vdn, which is independent of the input voltage of the input end Vin of the differential input signal in the gate voltage bootstrap branch, the weak-opened sixth PMOS transistor MP6 is equivalent to a large resistor when being opened, when the gate voltage bootstrap capacitor C discharges charges, the weak-opening current of the sixth PMOS transistor MP6 is increased, when the weak-opening current is equal to the leakage current of the first PMOS transistor MP1, the charges on the gate voltage bootstrap capacitor C are no longer discharged, and thus the constant bootstrap voltage of the gate voltage C is maintained.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode provided by the embodiment discloses a grid voltage bootstrap branch structure connected to a third PMOS tube in a high-pass/low-pass filter module, avoids the discharge of a grid voltage bootstrap capacitor in the grid voltage bootstrap branch caused by electric leakage of the third PMOS tube, achieves the technical effect of stabilizing voltage input of a grid electrode of the third PMOS tube, and inhibits nonlinearity of a signal transmission path in the high-pass/low-pass filter module.

In one embodiment, the first PMOS transistor MP1 is a PMOS transistor with an adjustable cutoff frequency, and the filter coefficient of the first differential branch circuit changes with the cutoff frequency of the first PMOS transistor MP 1.

In one embodiment, as shown in fig. 5, the timing path/dc bias module 200 includes two third differential branches that are mirror images and receive different differential timing signals, and each third differential branch includes a buffer B1, a third capacitor C3, a common-mode voltage signal input VCM, a third bias voltage signal input V3, a third resistor R3, and a fifth link switch S5.

The input end of the buffer B1 receives the differential timing signal and the enable signal EN, the third capacitor C3 is connected between the output end of the buffer B1 and the signal output end of the third differential branch, the common-mode voltage signal input end VCM is connected between the third capacitor C3 and the signal output end of the third differential branch, the third resistor R3 is connected between the common-mode voltage signal input end VCM and the signal output end of the third differential branch through a first node, the fifth linkage switch S5 is connected between the third resistor R3 and the first node, two third differential branches in mirror image setting are connected in parallel to the common-mode voltage signal input end VCM, the first node is further connected to the third bias voltage signal input end V3 in one third differential branch, the first node is further connected to the fifth bias voltage signal input end V5 in the other third differential branch, a sixth linkage switch S6 is disposed between the first node and the third bias voltage signal input end V3, and a seventh linkage switch S7 is disposed between the first node and the fifth bias voltage signal input end V5.

Specifically, when the buffer B1 receives the enable signal EN indicating that the stray wave signal is in a high frequency state, the buffer B1 is enabled, the fifth linkage switch S5 is closed, the sixth linkage switch S6 and the seventh linkage switch are both opened, the differential timing signal is subjected to level shift through the buffer B1 and the third capacitor, and the signal output end of the third differential branch circuit outputs the clock signal subjected to level shift; when the buffer B1 receives an enable signal EN indicating that the stray wave signal is in a low frequency state, the buffer B1 blocks, the fifth linkage switch S5 is opened, the sixth linkage switch S6 and the seventh linkage switch are both closed, the signal output end LON of the third differential branch circuit outputs a high-level first direct-current bias voltage signal in combination with the third bias voltage signal input end V3 and the common-mode voltage signal input end VCM, and the signal output end LOP of the third differential branch circuit outputs a low-level second direct-current bias voltage signal in combination with the fifth bias voltage signal input end V5 and the common-mode voltage signal input end VCM.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode provided by the embodiment discloses a circuit structure of a third differential branch, which realizes level shift of clock input signals through a buffer and a third capacitor in the high-pass mode, and facilitates the functions of mixing and amplifying according to output signals of the circuit of the third differential branch through the effect of direct current bias signals output by a common-mode voltage signal input end in the low-pass mode.

In one embodiment, as shown in fig. 6, the mixer amplifier module 300 includes two fourth differential branches with mirror image arrangement, and each fourth differential branch includes a fourth bias voltage signal input end V4, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, and a tenth PMOS transistor MP10.

The source stage of the seventh PMOS transistor MP7 is connected to the fourth bias voltage signal input terminal V4, and provides bias current for the fourth differential branch, the source stage of the eighth PMOS transistor MP8 is connected to the drain of the seventh PMOS transistor MP7, the gate of the eighth PMOS transistor MP8 is connected to the signal output terminal of the high pass/low pass filter module 100, the source stage of the ninth PMOS transistor MP9 is connected to the drain of the eighth PMOS transistor MP8, the gate of the ninth PMOS transistor MP9 is connected to the signal output terminal of one of the third differential branches in the timing path/dc bias module 200, the drain of the ninth PMOS transistor MP9 is connected to the first signal output terminal of the fourth differential branch through the fourth resistor R4, the source stage of the tenth PMOS transistor MP10 is connected to the drain of the eighth PMOS transistor MP8, the gate of the tenth PMOS transistor MP10 is connected to the signal output terminal of the other third differential branch in the timing path/dc bias module 200, the drain of the tenth PMOS transistor MP10 is connected to the fourth resistor R4 in the other differential branch in the mirror image arrangement, and is connected to the fourth signal output terminal of the fourth differential branch through the other differential branch.

Specifically, when the gate of the eighth PMOS transistor MP8 receives the high-pass filtered signal, the gates of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 respectively receive the clock signals output by the signal output ends of the two third differential branches, and the fourth differential branch operates in the mixing mode.

When the grid electrode of the eighth PMOS tube MP8 receives the low-pass filtering signal, the grid electrode of the ninth PMOS tube MP9 receives the low-level direct-current bias signal, the grid electrode of the tenth PMOS tube MP10 receives the high-level direct-current bias signal, and the fourth differential branch circuit works in an amplifying mode.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode provided by the embodiment specifically discloses a circuit structure diagram of a mixing amplification module, integrates mixing and amplification functions in the same mixing amplification module, and achieves the technical effects of executing the mixing function in the high-pass mode and executing the amplification function in the low-pass mode.

In some embodiments, as shown in fig. 6, the fourth differential branch further includes a first NMOS transistor MN1.

The drain electrode of the first NMOS tube MN1 is connected to the drain electrode of the eighth PMOS tube MP8, the gate electrode of the first NMOS tube MN1 is connected to the pole voltage signal input end, and the source stage of the first NMOS tube MN1 is connected to the second signal output end of the fourth differential branch through a current source.

The multiplexing error correction circuit in the high-pass mode and the low-pass mode provided by the embodiment increases the transconductance of the eighth PMOS transistor by integrating the first NMOS transistor in the operation of the fourth differential branch, thereby increasing the gain effect of the fourth differential branch.

In one embodiment, as shown in fig. 7, according to another aspect of the present invention, the present invention further provides a method for correcting multiplexing errors in a high-pass mode and a low-pass mode, including the steps of:

s100 receives a stray wave signal and an input signal, performs high-pass filtering on the input signal when the stray spectrum of the stray wave signal is at a high frequency, and performs low-pass filtering on the input signal when the stray spectrum of the stray wave signal is at a low frequency.

S200 receives the clock signal, the DC offset signal and the enable signal, outputs the clock signal subjected to level shift when the stray wave signal is in a high frequency state, and outputs the DC offset signal when the stray wave signal is in a low frequency state.

Specifically, the enable signal is used to represent the high-low frequency state of the stray wave signal, where step S100 and step S200 are not limited in order.

S310 suppresses the low frequency interference signal and mixes the input signal at the high frequency to the low frequency when receiving the high pass filtered signal and the clock signal.

S320 suppresses high frequency interference and amplifies the input signal at low frequency while receiving the low pass filtered signal and the dc offset signal.

For example, when the sampling frequency of the transmitting end adopting the 8-channel time domain interleaving structure is fs and the signal frequency is fin, the frequency corresponding to the stray wave is n×fs/8±fin, where N is an integer between 0 and 8. Taking the example of a stray wave at fs/8-fin, the frequency of the stray wave approaches 0 when fin approaches fs/8; when fin is close to 0, the frequency of the stray wave is close to fs/8. For the former case, interference at high frequency needs to be suppressed, and meanwhile, stray at low frequency is amplified by an amplifier to be subjected to quantization processing by a later module; in the latter case, it is necessary to suppress the interference at the low frequency, and at the same time, mix the spurious at the high frequency to the low frequency using a mixer, and provide a certain gain to the post-stage module for quantization processing.

When fin is near 0, the spurious spectrum fs/8-fin is at a high frequency, the input signal is filtered by high pass, the low frequency interference signal is suppressed and the input signal at the high frequency is mixed to a low frequency according to a clock with the frequency fs/8, when fin is near fs/8, the spurious spectrum fs/8-fin is at a low frequency, the input signal is filtered by low pass, the clock path is turned off, the high frequency interference is suppressed and the input signal at the low frequency is amplified according to the direct current offset voltage.

The multiplexing error correction method in the high-pass mode and the low-pass mode provided by the embodiment realizes the effects of high-frequency filtering and mixing the high-frequency signal to a low frequency position when the same circuit receives the high-frequency signal, and low-frequency filtering and signal amplification when the same circuit receives the low-frequency signal through module multiplexing, so that the influence of the stray wave signal on the chip communication effect is avoided, the chip size is reduced, and the chip cost is reduced.

In the foregoing embodiments, the descriptions of the embodiments are focused on, and the parts of a certain embodiment that are not described or depicted in detail may be referred to in the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the elements and steps of the examples described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed direct fractional frequency divider circuit and method may be implemented in other ways. For example, a direct fractional frequency divider circuit and method embodiment described above is merely illustrative, e.g., the division of the modules or units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the communications links shown or discussed may be through some interface, device or unit communications link or integrated circuit, whether electrical, mechanical or otherwise.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

It should be noted that the foregoing is only a preferred embodiment of the present invention, and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.

Claims

1. A multiplexing error correction circuit in a high-pass mode and a low-pass mode, comprising:

2. The high-pass and low-pass mode multiplexing error correction circuit according to claim 1, wherein the high-pass/low-pass filter module comprises a first high-pass/low-pass filter unit, the first high-pass/low-pass filter unit comprises two first differential branches arranged in a mirror image manner and receiving different differential input signals, and each first differential branch comprises:

A grounding switch;

a first filter capacitor;

a first filter resistor;

3. A high-pass mode and low-pass mode multiplexing error correction circuit as defined in claim 2, wherein,

when the stray frequency spectrum of the stray wave signal is in high frequency, the grounding switch is disconnected, the grid electrodes of the second PMOS tube and the third PMOS tube are in low level, and the differential input signal is output at the signal output end of the first differential branch after being subjected to high frequency filtering sequentially through the third PMOS tube and the first filter capacitor;

4. A high-pass mode and low-pass mode multiplexing error correction circuit as claimed in any one of claim 2 or 3,

the high-pass/low-pass filter module comprises at least two first high-pass/low-pass filter units, and the differential input signal input end of the latter first high-pass/low-pass filter unit is connected between the first filter capacitor and the first filter resistor in the former first high-pass/low-pass filter unit.

5. A high-pass mode and low-pass mode multiplexing error correction circuit as defined in claim 4, wherein,

the high-pass/low-pass filtering module comprises at least one first high-pass/low-pass filtering unit and at least one second high-pass filtering unit;

a second filter capacitor;

a second filter resistor;

6. A high-pass mode and low-pass mode multiplexing error correction circuit as defined in claim 5, wherein,

When the stray frequency spectrum of the stray wave signal is in high frequency, the grid electrode of the fifth PMOS tube is in low level, and the differential input signal is output at the signal output end of the second differential branch after being subjected to high frequency filtering through the second filter capacitor;

when the stray frequency spectrum of the stray wave signal is in a low frequency, the grid electrode of the fifth PMOS tube is in a high level, and the differential input signal is output at the signal output end of the second differential branch through the fifth PMOS tube.

7. A high-pass mode and low-pass mode multiplexing error correction circuit according to any one of claims 2 or 3, wherein the gate voltage of the third PMOS transistor is kept constant by a gate voltage bootstrap branch, the gate voltage bootstrap branch comprising:

a gate voltage bootstrap capacitor;

a sixth PMOS tube;

8. A high-pass mode and low-pass mode multiplexing error correction circuit as defined in claim 7, wherein,

when the grid voltage bootstrapping branch circuit is in a reset state, the first linkage switch and the second linkage switch are opened, the third linkage switch and the fourth linkage switch are closed, the grid electrode of the first PMOS tube is communicated with the third bias voltage signal input end, the first PMOS tube is in an off state, and charging voltages at two ends of the grid voltage bootstrapping capacitor are respectively the voltage of the first bias voltage signal input end and the voltage of the second bias voltage signal input end;

9. A high-pass mode and low-pass mode multiplexing error correction circuit as claimed in any one of claim 2 or 3,

the first PMOS tube is a PMOS tube with an adjustable cut-off frequency;

10. The high-pass and low-pass mode multiplexing error correction circuit according to claim 1, wherein said timing path/dc offset module comprises two third differential branches arranged in mirror image and receiving different differential timing signals, each of said third differential branches comprising:

11. A high-pass mode and low-pass mode multiplexing error correction circuit as defined in claim 10, wherein,

the buffer is enabled when the buffer receives the enabling signal representing that the stray wave signal is in a high-frequency state, the fifth linkage switch is closed, the sixth linkage switch and the seventh linkage switch are both opened, the differential time sequence signal is subjected to level shift through the buffer and the third capacitor, and the clock signal subjected to level shift is output at the signal output end of the third differential branch circuit;

12. The multiplexing error correction circuit in both high-pass and low-pass modes of claim 10, wherein said mixer amplifier module comprises two fourth differential branches arranged in mirror image, each of said fourth differential branches comprising:

a fourth bias voltage signal input;

13. A high-pass mode and low-pass mode multiplexing error correction circuit as defined in claim 12, wherein,

when the grid electrode of the eighth PMOS tube receives the high-pass filtering signal, the grid electrodes of the ninth PMOS tube and the tenth PMOS tube respectively receive the clock signals output by the signal output ends of the two third differential branches, and the fourth differential branch works in a frequency mixing mode;

14. A high-pass mode and low-pass mode multiplexing error correction circuit according to any of claims 12 or 13 and wherein said fourth differential branch further comprises:

15. The multiplexing error correction method in the high-pass mode and the low-pass mode is characterized by comprising the following steps: