CN115938436A - Storage circuit and storage array - Google Patents
Storage circuit and storage array Download PDFInfo
- Publication number
- CN115938436A CN115938436A CN202210225369.7A CN202210225369A CN115938436A CN 115938436 A CN115938436 A CN 115938436A CN 202210225369 A CN202210225369 A CN 202210225369A CN 115938436 A CN115938436 A CN 115938436A
- Authority
- CN
- China
- Prior art keywords
- circuit
- electrically connected
- control
- gate
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Read Only Memory (AREA)
Abstract
The invention discloses a storage circuit and a storage array, relates to the technical field of semiconductors, and aims to avoid the situation of error writing to a certain extent when a user writes data into the storage circuit, so that the reliability of the storage circuit is improved. The memory circuit includes an access unit circuit and a first control circuit. The input end of the first control circuit is correspondingly and electrically connected with the m bit signal input ends, the output end of the first control circuit is electrically connected with the power end of the access unit circuit, and the power end of the first control circuit is electrically connected with the fuse signal end. The first control circuit is used for supplying power to the access unit circuit under the condition that the m bit signals meet a first preset condition and the fuse signals meet a second preset condition. Wherein m is a positive integer. And the data storage end of the access unit circuit is electrically connected with the fuse signal end, and when the fuse signal meets a second preset condition, the access unit circuit is used for storing the data written in the data writing end. The storage array comprises the storage circuit provided by the technical scheme.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a memory circuit and a memory array.
Background
An Electrically programmable Fuse (eFuse) is a one-time programmable memory developed by using electromigration, fuse programming is performed based on the principle of electromigration, and information after programming can be permanently stored.
At present, eFuse storage circuits are widely used in the fields of aviation, mobile devices, routers and the like, and higher requirements are also put forward on the reliability of eFuse storage circuits. However, in some existing eFuse storage circuits, data is still written by a user by mistake, and reliability of the eFuse storage circuits cannot be improved.
Disclosure of Invention
The invention aims to provide a storage circuit and a storage array, so that when a user writes data into the storage circuit, the situation of error writing is avoided to a certain extent, and the reliability of the storage circuit is improved.
In a first aspect, the present invention provides a memory circuit comprising: an access unit circuit and a first control circuit. The input end of the first control circuit is correspondingly and electrically connected with the m bit signal input ends, the output end of the first control circuit is electrically connected with the power end of the access unit circuit, and the power end of the first control circuit is electrically connected with the fuse signal end. The first control circuit is used for supplying power to the access unit circuit under the condition that the m bit signals meet a first preset condition and the fuse signals meet a second preset condition. Wherein m is a positive integer. And the data storage end of the access unit circuit is electrically connected with the fuse signal end, and when the fuse signal meets a second preset condition, the access unit circuit is used for storing the data written in the data writing end.
Compared with the prior art, in the storage circuit provided by the invention, the input end of the first control circuit is correspondingly and electrically connected with the m bit signal input ends, the output end of the first control circuit is electrically connected with the power supply end of the access unit circuit, and the power supply end of the first control circuit is electrically connected with the fuse wire signal end. When the m bit signals input by the m bit signal terminals satisfy a first preset condition and the fuse signals input by the fuse signal terminals satisfy a second preset condition, the first control circuit can provide the required power supply voltage for the access unit circuit, and the access circuit can normally write data. Therefore, the invention can control the m bit signals and the fuse signals to enable the first control circuit to supply power to the access unit circuit, and the access unit circuit can write data normally, thereby avoiding the situation that a user writes data by mistake. Meanwhile, the data storage end of the access unit circuit is electrically connected with the fuse wire signal end, and when the fuse wire signal meets a second preset condition, the access unit circuit can store the data written in the data writing end under the action of the fuse wire signal, so that the reliability of the storage circuit is further improved. Therefore, the storage circuit provided by the invention can store the data written in the data writing end only under the condition that the m bit signals meet the first preset condition and the fuse signals meet the second preset condition. Therefore, the storage circuit provided by the invention can avoid the situation that a user wrongly writes data to a certain extent, thereby improving the reliability of the storage circuit.
In a second aspect, the present invention further provides a memory array, comprising a plurality of memory circuits according to the first aspect, wherein the plurality of memory circuits are arranged in an array. The write data control end of each memory circuit is electrically connected with other write data control ends of the row, and the read data control end of each memory circuit is electrically connected with other read data control ends of the row. The write data end of each storage circuit is electrically connected with other write data ends of the column, and the read data end of each storage circuit is electrically connected with other read data ends of the column.
Compared with the prior art, the beneficial effects of the memory array provided by the invention are the same as those of the memory circuit in the first aspect, and are not described herein again.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not limit the invention. In the drawings:
FIG. 1 is a schematic structural diagram of a memory circuit according to an embodiment of the present invention;
fig. 2 to fig. 4 are schematic structural diagrams of a first control sub-circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an access unit circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a sense amplifier provided in an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a second control circuit according to an embodiment of the present invention;
fig. 8 to fig. 10 are schematic structural diagrams of a second control sub-circuit according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a memory array according to an embodiment of the present invention.
Reference numerals:
1-a memory circuit, 11-a first control circuit,
12-access unit circuit, 111-first control sub-circuit,
112-a first voltage generation sub-circuit, 1111-a multi-bit enable control module,
1111 a-the first nor gate, 1111 b-the and gate,
1112-a first nand gate, 1113-not gate,
121-a write sub-circuit, 1211-a second nor gate,
122-fuses, 123-read subcircuits,
13-a second control circuit, 14-a sense amplifier,
131-a second control sub-circuit, 132-a second voltage generating sub-circuit,
1311-a second nand gate, 2-a memory array.
Detailed Description
In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish identical items or similar items with substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.
It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.
In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
An Electrically programmable Fuse (eFuse) is a one-time programmable memory developed by using electromigration, fuse programming is performed based on the principle of electromigration, and information after programming can be permanently stored. The eFuse circuit can be used as a storage circuit to store important information in the chip and also as a redundancy circuit to improve the reliability of the chip.
At present, eFuse storage circuits are widely used in the fields of aviation, mobile devices, routers and the like, and higher requirements are also put forward on the reliability of eFuse storage circuits. However, in some existing eFuse storage circuits, data is still written by a user by mistake, and reliability of the eFuse storage circuits cannot be improved.
In view of the above problems, an embodiment of the invention provides a memory circuit 1. As shown in fig. 1, a memory circuit 1 according to an embodiment of the present invention includes: an access unit circuit 12 and a first control circuit 11. The input terminal of the first control circuit 11 is electrically connected to the m-bit signal input terminals, the output terminal is electrically connected to the power terminal of the access unit circuit 12, and the power terminal of the first control circuit 11 is electrically connected to the fuse signal terminal FS. The first control circuit 11 is configured to supply power to the access unit circuit 12 if the m-bit signals satisfy a first preset condition and the fuse signal satisfies a second preset condition. Wherein m is a positive integer. The data storage terminal of the access unit circuit 12 is electrically connected to the fuse signal terminal FS, and when the fuse signal satisfies a second predetermined condition, the access unit circuit 12 is configured to store data written in the write data terminal.
As can be seen from the schematic structural diagram of the memory circuit 1 provided in the embodiment of the present invention, in the memory circuit 1 provided in the embodiment of the present invention, the input terminal of the first control circuit 11 is electrically connected to the m bit signal input terminals, the output terminal is electrically connected to the power terminal of the access unit circuit 12, and the power terminal of the first control circuit 11 is electrically connected to the fuse signal terminal FS. Moreover, when the m bit signals inputted from the m bit signal terminals satisfy the first predetermined condition and the fuse signal inputted from the fuse signal terminal FS satisfies the second predetermined condition, the first control circuit 11 can provide the required power voltage VDD _ CELL to the access unit circuit 12, and the access circuit 1 can normally write data. Based on this, the embodiment of the present invention can control the m bit signals and the fuse signal to enable the first control circuit 11 to supply power to the access unit circuit 12, and the access unit circuit 12 can write data normally, so that the embodiment of the present invention can avoid the situation that a user writes data by mistake. Meanwhile, the data storage terminal of the access unit circuit 12 is also electrically connected to the fuse signal terminal FS, and when the fuse signal satisfies the second preset condition, the access unit circuit 12 can store the data written in the data writing terminal under the action of the fuse signal, so that the reliability of the memory circuit 1 is further improved. As can be seen from this, the memory circuit 1 according to the embodiment of the present invention can store data written in the write data terminal only when the m bit signals satisfy the first preset condition and the fuse signal satisfies the second preset condition. Therefore, the memory circuit 1 provided by the embodiment of the invention can avoid the situation that the user wrote the data to a certain extent, thereby improving the reliability of the memory circuit 1.
In practical application. In order to reduce the probability of the user wrongly writing data to the maximum extent, preferably, m is larger than or equal to 4. When m =4, the probability that data can be normally written is only 1/16, and the probability that data cannot be written is 15/16, so that the occurrence of data being wrongly written by a user can be avoided to the greatest extent.
In one possible implementation, as shown in fig. 1, the first control circuit 11 includes a first control sub-circuit 111 and a first voltage generation sub-circuit 112. Input terminal of the first control sub-circuit 111 and m bit signal input terminals I 1 、I 2 、I 3 、I 4 Correspondingly, the output terminal of the first control sub-circuit 111 is electrically connected to the control terminal of the first voltage generation sub-circuit 112, and is configured to control the on/off of the first voltage generation sub-circuit 112 under the action of the m bit signals. The power supply terminal of the first voltage generation sub-circuit 112 is electrically connected to the fuse signal terminal FS, and the output terminal of the first voltage generation sub-circuit 112 is electrically connected to the power supply terminal of the access unit circuit 12 for supplying power to the access unit circuit 12.
In a specific implementation process, by controlling the input of the m bit signals so as to satisfy the first preset condition, under the action of the m bit signals, the output signal of the first control sub-circuit 111 controls the first voltage generation sub-circuit 112 to be turned on. In the case of conduction of the first voltage generation sub-circuit 112, when the fuse signal satisfies the second preset condition, the first voltage generation sub-circuit 112 supplies power to the access unit circuit 12. Based on this, when the m bit signals do not satisfy the first predetermined condition, the output signal of the first control sub-circuit 111 cannot turn on the first voltage generating sub-circuit 112, and at this time, the first voltage generating sub-circuit 112 cannot supply power to the access unit circuit 12, so as to prevent the user from writing data by mistake. In addition, even if the first voltage generation sub-circuit 112 is turned on by the m bit signals, that is, if the m bit signals satisfy the first preset condition, but the fuse signal does not satisfy the second preset condition, the first voltage generation sub-circuit 112 cannot generate the power supply voltage VDD _ CELL required by the access unit circuit 12, and the access unit circuit 12 cannot write data without power supply, thereby avoiding the situation that the user wrongly writes data.
Referring to fig. 1 to 4, in some embodiments, the first control sub-circuit 111 includes at least one multi-bit enable control module 1111, a first nand gate 1112, and a not gate 1113. An input terminal of the at least one multi-bit enable control module 1111 is electrically connected to the m-bit signal input terminals; the output end of the at least one multi-bit enable control module 1111 is correspondingly connected to the input end of the first nand gate 1112, and the output end of the first nand gate 1112 is electrically connected to the input end of the not gate 1113.
The first voltage generation sub-circuit 112 includes a first transistor T1, a second transistor T2, a first resistor R1, and a second resistor R2. The output end of the nand 1113 is electrically connected to the control end of the first transistor T1, the first electrode of the first transistor T1 is electrically connected to the fuse signal end FS through the first resistor R1, the first electrode of the first transistor T1 is also electrically connected to the control end of the second transistor T2, and the second electrode of the first transistor T1 is grounded. A first electrode of the second transistor T2 is electrically connected to the fuse signal terminal FS, a second electrode of the second transistor T2 is grounded through the second resistor R2, and a second electrode of the second transistor T2 is further electrically connected to a power supply terminal of the access unit circuit 12.
It is understood that the first transistor T1 is an N-type transistor, i.e., the control terminal is turned on when the control terminal is at a high level (logic "1"). The second transistor T2 is a P-type transistor, i.e., it is turned on when the control terminal is at a low level (logic "0"). The second predetermined condition is that the fuse signal terminal FS is at a high level (logic "1").
In a specific implementation, when the first transistor T1 needs to be turned on, the level of the control terminal of the first transistor T1 must be made to be a high level (logic "1"). When the first transistor T1 is turned on, the first electrode and the second electrode are directly turned on, and since the second electrode is directly grounded, the first electrode is also at a low level (logic "0"). Since the first resistor R1 is further disposed between the first electrode of the first transistor T1 and the fuse signal terminal FS, the fuse signal terminal FS can be prevented from being directly connected to the ground terminal and set to a low level (logic "0"). At this time, the first electrode of the first transistor T1 outputs a low level (logic "0") signal to the control terminal of the second transistor T2, thereby turning on the second transistor T2. When the signal at the fuse signal terminal FS is at a low level (logic "0"), a voltage signal is not generated even if the second transistor T2 is turned on, that is, the power supply voltage VDD _ CELL required by the access unit circuit 12 cannot be generated. The second electrode of the second transistor T2 generates the power voltage VDD _ CELL required by the access unit circuit 12 only when the fuse signal terminal FS is at a high level. Similarly, the second resistor R2 is set to a low level (logic "0") in order to avoid the second electrode of the second transistor T2 being directly grounded.
Furthermore, as shown in FIGS. 2-4, the multi-bit enable control module 1111 of the above-mentioned embodiment comprises at least one first NOR gate 1111a and at least one AND gate 1111b, and m ≧ 4. The input terminal of each first nor gate 1111a is electrically connected to at least two bit signal input terminals, respectively, and the output terminal of each first nor gate 1111a is electrically connected to the first input terminal of the first nand gate 1112. The input end of each and gate 1111b is electrically connected to at least two bit signal input ends, and the output end of each and gate 1111b is connected to the second input end of the first nand gate 1112.
In practical applications, when the input terminal of the multi-bit enable control module 1111 is connected to the bit signal input terminal, the input terminals of the first nor gate 1111a and the and gate 1111b may be connected to the input terminal of the bit signal in an interleaved manner, that is, the input terminal of the bit signal ordered as odd number is connected to the input terminal of the first nor gate 1111a, and the input terminal of the bit signal ordered as even number is connected to the input terminal of the and gate 1111 b. In this way, the m bit signals can be made to satisfy the first preset condition only in the case where "0" and "1" are staggered. That is, when m =4, the m bit signals are always "0101", and the case where the m bit signals are "0011" due to noise interference or the like is avoided, so that the probability of erroneous writing can be further reduced, and the reliability of the memory circuit 1 can be improved. Furthermore, after changing the connection order, that is, connecting the even-ordered bit signal input terminal to the input terminal of the first nor gate 1111a and connecting the odd-ordered bit signal input terminal to the input terminal of the and gate 1111b, the order of the m bit signals needs to be adjusted accordingly, and at this time, when m =4, the m bit signals are "1010". The embodiment of the present invention is not particularly limited.
It is understood that nand, nor, and nor are all basic logic circuits in a digital circuit.
The NAND gate has at least two input ends and one output end, when all the input ends are at high level (logic '1'), the output is at low level (logic '0'); when at least one of the input terminals is at a low level (logic "0"), the output is at a high level (logic "1").
The NOR gate is provided with at least two input ends and an output end, and when any input end is at a high level (logic '1'), the output is at a low level (logic '0'); when all inputs are low (logic "0"), the output is high (logic "1").
The and gate has at least two inputs and an output, and the circuit output is high (logic "1") only when all inputs are high (logic "1") and low (logic "0") otherwise.
The not gate has an input end and an output end, and when the input end is at a high level (logic '1'), the output end is at a low level (logic '0'); conversely, when the input terminal is at a low level (logic "0"), the output terminal is at a high level (logic "1").
Exemplarily, as shown in fig. 2, when m =4, i.e. there are 4 bit signal inputs, then the first control sub-circuit 111 should also have 4 inputs accordingly. The first control sub-circuit 111 may include 1 more multi-bit enable control modules 1111, a first nand gate 1112, and a not gate 1113. Specifically, the first control sub-circuit 111 includes 1 first nor gate 1111a, 1 and gate 1111b, 1 first nand gate 1112, and 1 not gate 1113. A first input terminal of the first nor gate 1111a and a first bit signal input terminal I 1 Electrically connected to the second input terminal of the first NOR gate 1111a and the third bit signal input terminal I 3 Electrically, the output terminal of the first nor gate 1111a is electrically connected to the first input terminal of the first nand gate 1112. First input terminal and second bit signal input terminal I of AND gate 1111b 2 Electrically connected to the second input of the AND gate 1111b and the fourth bit signal input I 4 And the output end of the and gate 1111b is electrically connected to the second input end of the first nand gate 1112, and the output end of the first nand gate 1112 is electrically connected to the input end of the not gate 1113. At this time, the first preset condition is: the m bit signals are '0101', that is, the first bit signal is '0', the second bit signal is '1', the third bit signal is '0', and the fourth bit signal is '1'. The output of the first nor gate 1111a is "0" and the output of the and gate 1111b is "1", the output of the first nand gate 1112 is "0", and the output of the not gate 1113 is "1", so that the first transistor T1 can be turned on.
Exemplarily, as shown in fig. 3, when m =6, i.e. there are 6 bit signal inputs, then the first control sub-circuit 111 should also have 6 inputs accordingly. The first control sub-circuit 111 may include 1 multi-bit enable control module 1111 as well as a first nand gate 1112 and a not gate 1113. Specifically, the first control sub-circuit 111 includes 1 first nor gate 1111a, 1 and gate 1111b, and 1 first nand gate 1112 to control the first and second gatesAnd 1 not gate 1113. The first nor gate 1111a has 3 inputs, and the and gate 1111b has 3 inputs. A first input terminal of the first nor gate 1111a and a first bit signal input terminal I 1 Electrically connected, the second input of the first NOR gate 1111a and the third bit signal input I 3 Electrically connected to the third input of the first NOR gate 1111a and the fifth bit signal input I 5 Electrically, the output terminal of the first nor gate 1111a is electrically connected to the first input terminal of the first nand gate 1112. First input terminal and second bit signal input terminal I of AND gate 1111b 2 Electrically connected to the second input terminal of the AND gate 1111b and the fourth bit signal input terminal I 4 Electrically connected to the third input terminal of the AND gate 1111b and the sixth bit signal input terminal I 6 And the output end of the and gate 1111b is electrically connected to the second input end of the first nand gate 1112, and the output end of the first nand gate 1112 is electrically connected to the input end of the not gate 1113. At this time, the first preset condition is that the m bit signals are "010101", that is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", the fourth bit signal is "1", the fifth bit signal is "0", and the sixth bit signal is "1". The output of the first nor gate 1111a is "0", the output of the and gate 1111b is "1", the output of the first nand gate 1112 is "0", the output of the not gate 1113 is "1", and the first transistor T1 can be turned on. It should be understood that, in the above embodiment, when m =6, there may also be 1 first nor gate 1111a having 4 input terminals and 1 and gate 1111b having 2 input terminals in the multi-bit enable control module 1111, which is not specifically limited in this embodiment of the present invention.
Exemplarily, as shown in fig. 4, when m =8, i.e. there are 8 bit signal inputs, then the first control sub-circuit 111 should correspondingly also have 8 inputs. The first control sub-circuit 111 may include 2 multi-bit enable control modules 1111, a first nand gate 1112, and a not gate 1113. Specifically, the first control sub-circuit 111 includes 2 first nor gates 1111a, 2 and gates 1111b, 1 first nand gate 1112, and 1 not gate 1113. The 2 first nor gates 1111a have 4 inputsRespectively connected to a first bit signal input terminal I 1 A third bit signal input terminal I 3 A fifth bit signal input terminal I 5 And a seventh bit signal input terminal I 7 The output ends of the 2 first nor gates 1111a are electrically connected to the first input end and the third input end of the first nand gate 1112, respectively. 2 AND gates 1111b have 4 input terminals respectively connected to the second bit signal input terminal I 2 A fourth bit signal input terminal I 4 A sixth bit signal input terminal I 6 And an eighth bit signal input terminal I 8 The output ends of the 2 and gates 1111b are electrically connected to the second input end and the fourth input end of the first nand gate 1112, respectively, and the output end of the first nand gate 1112 is electrically connected to the input end of the not gate 1113. At this time, the first preset condition is that the m bit signals are "01010101", that is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", the fourth bit signal is "1", the fifth bit signal is "0", the sixth bit signal is "1", the seventh bit signal is "0", and the eighth bit signal is "1". The outputs of the 2 first nor gates 1111a and 1111b are all "1" and "1", respectively, the output of the first nand gate 1112 is "0", and the output of the not gate 1113 is "1", so that the first transistor T1 is turned on. It is to be understood that, when m =8, the first control sub-circuit 111 may further include only 1 multi-bit enable control module 1111, the first nand gate 1112 and the not gate 1113, in which case, the first nor gate 1111a and the and gate 1111b in the multi-bit enable control module 1111 may have 4 inputs respectively; alternatively, the first nor gate 1111a in the multi-bit enable control module 1111 has 3 inputs, and the and gate 1111b has 5 inputs; alternatively, 1 first nor gate 1111a in the multi-bit enable control module 1111 has 3 inputs, 1 and gate 1111b has 2 inputs, and the other and gate 1111b has 3 inputs. The number of the convertible cases is too many to be exhaustive, and the embodiments of the present invention do not limit this.
It should be understood that, in the above embodiment, the order of the m bit signals is only related to the type of the digital logic gates connected to the m bit signals, that is, if the order of the first nor gate 1111a and the and gate 1111b in the multi-bit enable control module 1111 is adjusted in actual operation, the first preset condition should be adjusted accordingly, and the embodiment of the present invention is not limited in this respect.
In one possible implementation, as shown in fig. 5, the access unit circuit 12 includes a write sub-circuit 121, a read sub-circuit 123, and a fuse 122. A first terminal of the write-in sub-circuit 121 is electrically connected to the write-in data terminal BS and the write-in data control terminal WL, a second terminal of the write-in sub-circuit 121 is electrically connected to a first terminal of the read sub-circuit 123, and a power source terminal of the write-in sub-circuit 121 is electrically connected to an output terminal of the first control circuit 11. The first terminal of the fuse 122 is electrically connected to the fuse signal terminal FS, and the second terminal of the fuse 122 is electrically connected to the second terminal of the write sub-circuit 121 and the first terminal of the read sub-circuit 123. The control end of the reading sub-circuit 123 is electrically connected to the read data control end RL, and the second end of the reading sub-circuit 123 is electrically connected to the read data end BL.
In some embodiments, the write sub-circuit 121 includes a second nor gate 1211 and a third transistor T3. A first input terminal of the second nor gate 1211 is electrically connected to the write data terminal BS, a second input terminal of the second nor gate 1211 is electrically connected to the write data control terminal WL, an output terminal of the second nor gate 1211 is electrically connected to the control terminal of the third transistor T3, and a power supply terminal of the second nor gate 1211 is electrically connected to the output terminal of the first control circuit 11. A first electrode of the third transistor T3 is electrically connected to the fuse signal terminal FS through the fuse 122, and a second electrode of the third transistor T3 is grounded. The reading sub-circuit 123 includes a fourth transistor T4. A control end of the fourth transistor T4 is electrically connected to the read data control end RL, a first electrode of the fourth transistor T4 is electrically connected to a first electrode of the third transistor T3, and a second electrode of the fourth transistor T4 is electrically connected to the read data end BL.
It is understood that the third transistor T3 and the fourth transistor T4 are both N-type transistors, i.e., are turned on when the control terminal is at a high level (logic "1").
In the data writing phase, the write data control terminal WL is at a low level (logic "0"), i.e., the input signal of the second input terminal of the second nor gate 1211 is at a low level (logic "0"). In the case where the second nor gate 1211 can normally write, it may be determined that the fuse signal still satisfies the above-described second preset condition at this time, that is, the fuse signal terminal is at a high level (logic "1"). At this time, since the first end of the fuse 122 is electrically connected to the fuse signal terminal FS and the second end of the fuse 122 is connected to the first electrode of the third transistor T3, the fuse 122 is blown if the third transistor T3 is turned on, and the fuse 122 is not blown if the third transistor T3 is turned off. I.e., whether the fuse 122 is blown or not, is determined by whether the third transistor T3 is turned on or not. Since the control terminal of the third transistor T3 is electrically connected to the output terminal of the second nor gate 1211, when the input signal at the second input terminal of the second nor gate 1211 is at a low level (logic "0"), the input signal at the first input terminal of the second nor gate 1211 directly determines the output signal of the second nor gate 1211. For example, when the input signal at the first input terminal of the second nor gate 1211 is at a low level (logic "0"), the second nor gate 1211 outputs a high level (logic "1"), the third transistor T3 is turned on, the fuse 122 is blown, and the stored data is coded "1"; when the input signal of the first input terminal of the second nor gate 1211 is at a high level (logic "1"), the second nor gate 1211 outputs a low level (logic "0"), the third transistor T3 is not turned on, the fuse 122 is not blown, and the stored data is encoded "0".
In the data reading phase, the read data control terminal RL is at a high level (logic "1"), thereby controlling the fourth transistor T4 to be turned on. In order to avoid erroneous writing, the fuse signal terminal FS needs to be set to a low level (logic "0"). The first electrode and the second electrode of the fourth transistor T4 are directly electrically connected, i.e. the state of the fuse 122 can be read from the read data terminal BL. If the fuse 122 is blown, the impedance becomes infinite, and if the fuse 122 is not blown and remains connected, the impedance becomes approximately infinite.
In one possible implementation, as shown in fig. 6 and 7, the memory circuit 1 further includes a sense amplifier 14 and a second control circuit 13. The input end of the second control circuit 13 is electrically connected to the input end of the m bit signals correspondingly, the output end of the second control circuit is electrically connected to the power supply end of the sense amplifier 14, and the second control circuit 13 is configured to supply power to the sense amplifier 14 when the m bit signals satisfy a first preset condition. An input terminal of sense amplifier 14 is electrically connected to an output terminal of access unit circuit 12 for reading data stored in access unit circuit 12.
As shown in fig. 6, the input terminal of the sense amplifier 14 is electrically connected to the read data terminal BL. The sense amplifier 14 is configured to detect a blown state of the fuse 122, and convert the blown state into a corresponding voltage signal for outputting, so as to complete reading of data stored in the memory circuit 1. In fig. 6, CK is a clock signal terminal, VDD _ AMP is a power source terminal of the sense amplifier 14, AP is a first node, AN is a second node, and VOP is AN output terminal of the sense amplifier 14. The sense amplifier 14 has a mirror-symmetrical structure, so that the comparison result can be output through the output terminal VOP by comparing the resistance of the fuse 122 with the resistance of the fourth resistor R4. If the fuse 122 is in the blown state, the impedance is infinite, i.e., greater than the resistance of the fourth resistor R4, the output terminal VOP outputs a high level (logic "1"), i.e., reads that the data stored in the access unit circuit 12 is a code "1"; if the fuse 122 is in the connection state, the impedance is approximately infinitesimal, i.e. smaller than the resistance of the fourth resistor R4, the output VOP will output a low level (logic "0"), i.e. the data stored in the access unit circuit 12 is read as a code "0".
In some embodiments, as shown in fig. 7, the second control circuit 13 includes a second control sub-circuit 131 and a second voltage generation sub-circuit 132. The input end of the second control sub-circuit 131 is electrically connected to the m bit signal input ends correspondingly, and the output end of the second control sub-circuit 131 is electrically connected to the control end of the second voltage generation sub-circuit 132, for controlling the on/off of the second voltage generation sub-circuit 132 under the action of the m bit signals. A power supply terminal of the second voltage generating sub-circuit 132 is electrically connected to the common power supply terminal VDD, and an output terminal of the second voltage generating sub-circuit 132 is electrically connected to a power supply terminal of the sense amplifier 14 for supplying power to the sense amplifier 14.
In a specific implementation process, by controlling the input of the m bit signals so as to satisfy the first preset condition, under the action of the m bit signals, the output signal of the second control sub-circuit 131 controls the second voltage generating sub-circuit 132 to be turned on. In the case of conduction of the second voltage generation sub-circuit 132, the second voltage generation sub-circuit 132 supplies power to the sense amplifier 14. Based on this, when the m bit signals do not satisfy the first preset condition, the output signal of the second control sub-circuit 131 cannot turn on the second voltage generating sub-circuit 132, at this time, the second voltage generating sub-circuit 132 cannot generate the power voltage VDD _ AMP required by the sense amplifier 14, that is, the second voltage generating sub-circuit 132 cannot supply power to the sense amplifier 14, and the sense amplifier 14 cannot normally read data without power supply, so that the data security is ensured, and the reliability of the storage circuit 1 is further improved.
In some embodiments, as shown in fig. 7 to 10, the second control sub-circuit 131 includes at least one multi-bit enable control module 1111 and a second nand gate 1311. The second voltage generation sub-circuit 132 includes a fifth transistor T5 and a third resistor R3. The input terminal of the at least one multi-bit enable control module 1111 is electrically connected to the m-bit signal input terminals, the output terminal of the at least one multi-bit enable control module 1111 is electrically connected to the input terminal of the second nand gate 1311, and the output terminal of the second nand gate 1311 is electrically connected to the control terminal of the fifth transistor T5. A first electrode of the fifth transistor T5 is electrically connected to the common power supply terminal VDD, a second electrode of the fifth transistor T5 is grounded through a third resistor R3, and a second electrode of the fifth transistor T5 is also electrically connected to the power supply terminal of the sense amplifier 14.
It is understood that the fifth transistor T5 is a P-type transistor, i.e., turned on at a low level (logic "0").
In practical implementation, when the fifth transistor T5 needs to be turned on, the control terminal of the fifth transistor T5 must be at a low level (logic "0"). When the fifth transistor T5 is turned on, the first electrode and the second electrode are directly turned on, and because the first electrode is electrically connected to the common power source terminal VDD and the third resistor R3 is further present between the second electrode and the ground terminal, both the first electrode and the second electrode are at a high level (logic "1") under the action of the common power source terminal VDD. The second electrode of the fifth transistor T5 is electrically connected to the power source terminal of the sense amplifier 14, and thus the power source voltage VDD _ AMP required by the sense amplifier 14 is generated.
Exemplarily, as shown in fig. 8, when m =4, i.e. there are 4 bit signal inputs, the second control sub-circuit 131 should accordingly also have 4 inputs. The second control sub-circuit 131 may include 1 multi-bit enable control module 1111 and a second nand gate 1311. Specifically, the second control sub-circuit 131 includes 1 first nor gate 1111a, 1 and gate 1111b, and 1 second nand gate 1311. A first input terminal of the first nor gate 1111a and a first bit signal input terminal I 1 Electrically connected, the second input of the first NOR gate 1111a and the third bit signal input I 3 And the output end of the first nor gate 1111a is electrically connected with the first input end of the second nand gate 1311. First input terminal and second bit signal input terminal I of AND gate 1111b 2 Electrically connected to the second input of the AND gate 1111b and the fourth bit signal input I 4 And the output end of the and gate 1111b is electrically connected to the second input end of the second nand gate 1311, and the output end of the second nand gate 1311 is electrically connected to the control end of the fifth transistor T5. At this time, the first preset condition is that the m bit signals are "0101", that is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", and the fourth bit signal is "1". The output of the first nor gate 1111a is "0" and the output of the and gate 1111b is "1", and the output of the second nand gate 1311 is "0", so that the fifth transistor T5 is turned on.
Exemplarily, as shown in fig. 9, when m =6, i.e. there are 6 bit signal inputs, then the second control sub-circuit 131 should also have 6 inputs accordingly. The second control sub-circuit 131 may include 1 multi-bit enable control module 1111 and a second nand gate 1311. Specifically, the second control sub-circuit 131 includes 1 first nor gate 1111a, 1 and gate 1111b, and 1 second nand gate 1311. The first nor gate 1111a has 3 inputs, and the and gate 1111b has 3 inputs. A first input terminal of the first nor gate 1111a and a first bit signal input terminal I 1 Electrically connected, the second input of the first NOR gate 1111a and the third bit signal input I 3 Electrically connected to the third input of the first NOR gate 1111a and the fifth bit signal input I 5 And the output end of the first nor gate 1111a is electrically connected with the first input end of the second nand gate 1311. First input terminal and second bit signal input terminal I of AND gate 1111b 2 Electrically connected to the second input of the AND gate 1111b and the fourth bit signal input I 4 Electrically connected to the third input terminal of the AND gate 1111b and the sixth bit signal input terminal I 6 And the output end of the and gate 1111b is electrically connected to the second input end of the second nand gate 1311, and the output end of the second nand gate 1311 is electrically connected to the control end of the fifth transistor T5. At this time, the first preset condition is that the m bit signals are "010101", that is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", the fourth bit signal is "1", the fifth bit signal is "0", and the sixth bit signal is "1". The output of the first nor gate 1111a is "0" and the output of the and gate 1111b is "1", and then the output of the second nand gate 1311 is "0", so that the fifth transistor T5 can be turned on. It should be understood that, in the above embodiment, when m =6, there may also be 1 first nor gate 1111a having 4 input terminals and 1 and gate 1111b having 2 input terminals in the multi-bit enable control module 1111, which is not specifically limited in this embodiment of the present invention.
Exemplarily, as shown in fig. 10, when m =8, i.e. there are 8 bit signal inputs, the second control sub-circuit 131 should accordingly also have 8 inputs. The second control sub-circuit 131 may include 2 multi-bit enable control modules 1111 and a second nand gate 1311. Specifically, the second control sub-circuit 131 includes 2 first nor gates 1111a, 2 and gates 1111b, and 1 second nand gate 1311. The 2 first nor gates 1111a have 4 input terminals respectively connected to the first bit signal input terminal I 1 Third bit informationNumber input terminal I 3 A fifth bit signal input terminal I 5 And a seventh bit signal input terminal I 7 And the output ends of the 2 first nor gates 1111a are electrically connected to the first input end and the third input end of the second nand gate 1311, respectively. 2 AND gates 1111b have 4 input terminals respectively connected to the second bit signal input terminal I 2 A fourth bit signal input terminal I 4 A sixth bit signal input terminal I 6 And an eighth bit signal input terminal I 8 The output ends of the 2 and gates 1111b are electrically connected to the second input end and the fourth input end of the second nand gate 1311, respectively, and the output end of the second nand gate 1311 is electrically connected to the control end of the fifth transistor T5. At this time, the first preset condition is that the m bit signals are "01010101", that is, the first bit signal is "0", the second bit signal is "1", the third bit signal is "0", the fourth bit signal is "1", the fifth bit signal is "0", the sixth bit signal is "1", the seventh bit signal is "0", and the eighth bit signal is "1". The outputs of the 2 first nor gates 1111a and 1111b are all "1" and the outputs of the 2 and gates 1111b are all "1", and then the output of the second nand gate 1311 is "0", so that the fifth transistor T5 is turned on. It is to be understood that when m =8, the second control sub-circuit 131 may further include only 1 multi-bit enable control module 1111 and the second nand gate 1311, and in this case, the first nor gate 1111a and the and gate 1111b in the multi-bit enable control module 1111 may have 4 input terminals respectively; alternatively, the first nor gate 1111a in the multi-bit enable control module 1111 has 3 inputs, and the and gate 1111b has 5 inputs; alternatively, 1 first nor gate 1111a in the multi-bit enable control module 1111 has 3 inputs, 1 and gate 1111b has 2 inputs, and the other and gate 1111b has 3 inputs. The number of the convertible cases is too many to be exhaustive, and the embodiments of the present invention do not limit this.
With reference to fig. 2 to 4 and fig. 8 to 10, it can be seen that the circuit structure of the first control sub-circuit 111 is similar to that of the second control sub-circuit 131, and therefore, in practical applications, in order to save cost, the first control sub-circuit 111 and the second control sub-circuit 131 may also be integrated into one, that is, the input terminal of the not-gate 1113 in the first control sub-circuit 111 is directly electrically connected to the control terminal of the fifth transistor T5.
As shown in fig. 11, an embodiment of the present invention further provides a memory array 2, which includes a plurality of memory circuits 1 according to the first aspect, and the plurality of memory circuits 1 are arranged in an array. The write data control terminal WL of each memory circuit 1 is electrically connected to the other write data control terminals WL in the row, and the read data control terminal RL of each memory circuit 1 is electrically connected to the other read data control terminals RL in the row. The write data end BS of each memory circuit 1 is electrically connected to the other write data ends BS of the column where it is located, and the read data end BL of each memory circuit 1 is electrically connected to the other read data ends BL of the column where it is located.
As shown in fig. 11, the memory array 2 is an 8 × 8 array, i.e., each row and each column has 8 memory circuits. The write data control terminals WL of the 8 memory circuits 1 per row are connected together in common, and the read data control terminals RL of the 8 memory circuits 1 per row are also connected together in common. The write data terminals BS of 8 memory circuits 1 in each column are connected together, and the read data terminals BL of 8 memory circuits 1 in each column are also connected together. The fuse signal terminals FS of the 64 memory circuits 1 are connected in common, and the power supply terminals VDD _ CELL of the 64 memory circuits 1 are also connected in common.
Compared with the prior art, the beneficial effects of the memory array 2 provided by the embodiment of the present invention are the same as the beneficial effects of the memory circuit 1, and are not described herein again.
While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely illustrative of the invention as defined by the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A memory circuit, comprising: an access unit circuit and a first control circuit; the input end of the first control circuit is correspondingly and electrically connected with the m bit signal input ends, the output end of the first control circuit is electrically connected with the power end of the access unit circuit, the power end of the first control circuit is electrically connected with the fuse signal end, and the first control circuit is used for supplying power to the access unit circuit under the condition that the m bit signals meet a first preset condition and the fuse signal meets a second preset condition; wherein m is a positive integer;
and the data storage end of the access unit circuit is electrically connected with the fuse signal end, and when the fuse signal meets the second preset condition, the access unit circuit is used for storing data written in the data writing end.
2. The memory circuit of claim 1, wherein the first control circuit comprises a first control sub-circuit and a first voltage generation sub-circuit;
the input end of the first control sub-circuit is correspondingly and electrically connected with the m bit signal input ends, and the output end of the first control sub-circuit is electrically connected with the control end of the first voltage generation sub-circuit and is used for controlling the on-off of the first voltage generation sub-circuit under the action of the m bit signals;
the power supply terminal of the first voltage generation sub-circuit is electrically connected to the fuse signal terminal, and the output terminal of the first voltage generation sub-circuit is electrically connected to the power supply terminal of the access unit circuit, and is configured to supply power to the access unit circuit.
3. The memory circuit of claim 2, wherein the first control sub-circuit comprises at least one multi-bit enable control module, a first nand gate, and a not gate;
the input end of the at least one multi-bit enabling control module is electrically connected with the m bit signal input ends; the output end of the at least one multi-bit enable control module is correspondingly connected with the input end of the first NAND gate, and the output end of the first NAND gate is electrically connected with the input end of the NOT gate;
the first voltage generation sub-circuit comprises a first transistor, a second transistor, a first resistor and a second resistor; the control end of the first transistor is electrically connected with the output end of the not gate, the first electrode of the first transistor is electrically connected with the fuse signal end through the first resistor, the first electrode of the first transistor is also electrically connected with the control end of the second transistor, and the second electrode of the first transistor is grounded; the first electrode of the second transistor is electrically connected to the fuse signal terminal, the second electrode of the second transistor is grounded through the second resistor, and the second electrode of the second transistor is also electrically connected to the power supply terminal of the access unit circuit.
4. The memory circuit of claim 3, wherein the multi-bit enable control module comprises at least one first NOR gate and at least one AND gate, and m ≧ 4, wherein:
the input end of each first NOR gate is electrically connected with at least two bit signal input ends respectively, and the output end of each first NOR gate is electrically connected with the first input end of the first NAND gate; the input end of each AND gate is electrically connected with at least two bit signal input ends respectively, and the output end of each AND gate is connected with the second input end of the first NAND gate.
5. The memory circuit according to any one of claims 1 to 4, wherein the access cell circuit includes a write sub-circuit, a read sub-circuit, and a fuse;
the first end of the write-in sub-circuit is respectively electrically connected with the write-in data end and the write-in data control end, the second end of the write-in sub-circuit is electrically connected with the first end of the read-out sub-circuit, and the power supply end of the write-in sub-circuit is electrically connected with the output end of the first control circuit;
the first end of the fuse is electrically connected with the fuse signal end, and the second end of the fuse is simultaneously electrically connected with the second end of the writing sub-circuit and the first end of the reading sub-circuit;
the control end of the reading sub-circuit is electrically connected with the read data control end, and the second end of the reading sub-circuit is electrically connected with the read data end.
6. The memory circuit according to claim 5, wherein the write sub-circuit includes a second nor gate and a third transistor; a first input end of the second nor gate is electrically connected with the write-in data terminal, a second input end of the second nor gate is electrically connected with the write-in data control terminal, an output end of the second nor gate is electrically connected with a control terminal of the third transistor, and a power supply end of the second nor gate is electrically connected with an output end of the first control circuit; a first electrode of the third transistor is electrically connected to the fuse signal terminal through the fuse, and a second electrode of the third transistor is grounded;
the read sub-circuit comprises a fourth transistor; the control end of the fourth transistor is electrically connected with the read data control end, the first electrode of the fourth transistor is electrically connected with the first electrode of the third transistor, and the second electrode of the fourth transistor is electrically connected with the read data end.
7. The memory circuit according to claim 4, wherein the memory circuit further comprises a sense amplifier and a second control circuit; wherein:
the input end of the second control circuit is correspondingly electrically connected with the input ends of the m bit signals, the output end of the second control circuit is electrically connected with the power supply end of the sense amplifier, and the second control circuit is used for supplying power to the sense amplifier under the condition that the m bit signals meet the first preset condition;
and the input end of the sensitive amplifier is electrically connected with the output end of the access unit circuit and is used for reading the data stored in the access unit circuit.
8. The memory circuit of claim 7, wherein the second control circuit comprises a second control sub-circuit and a second voltage generation sub-circuit;
the input end of the second control sub-circuit is correspondingly and electrically connected with the m bit signal input ends, and the output end of the second control sub-circuit is electrically connected with the control end of the second voltage generation sub-circuit and is used for controlling the on-off of the second voltage generation sub-circuit under the action of the m bit signals;
the power supply end of the second voltage generation sub-circuit is electrically connected with a public power supply end, and the output end of the second voltage generation sub-circuit is electrically connected with the power supply end of the sense amplifier and used for supplying power to the sense amplifier.
9. The memory circuit of claim 8, wherein the second control sub-circuit comprises at least one of the multi-bit enable control module and a second nand gate; the second voltage generation sub-circuit comprises a fifth transistor and a third resistor;
the input end of the at least one multi-bit enable control module is electrically connected with the m bit signal input ends, the output end of the at least one multi-bit enable control module is electrically connected with the input end of the second nand gate, and the output end of the second nand gate is electrically connected with the control end of the fifth transistor;
the first electrode of the fifth transistor is electrically connected with the public power supply end, the second electrode of the fifth transistor is grounded through the third resistor, and the second electrode of the fifth transistor is further electrically connected with the power supply end of the sense amplifier.
10. A memory array comprising a plurality of memory circuits according to any of claims 1 to 9, the plurality of memory circuits being arranged in an array; wherein:
the write data control end of each memory circuit is electrically connected with other write data control ends of the row, and the read data control end of each memory circuit is electrically connected with other read data control ends of the row;
the write data end of each memory circuit is electrically connected with the other write data ends of the column where the memory circuit is located, and the read data end of each memory circuit is electrically connected with the other read data ends of the column where the memory circuit is located.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210225369.7A CN115938436B (en) | 2022-03-09 | 2022-03-09 | Memory circuit and memory array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210225369.7A CN115938436B (en) | 2022-03-09 | 2022-03-09 | Memory circuit and memory array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115938436A true CN115938436A (en) | 2023-04-07 |
| CN115938436B CN115938436B (en) | 2023-09-15 |
Family
ID=86651364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210225369.7A Active CN115938436B (en) | 2022-03-09 | 2022-03-09 | Memory circuit and memory array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115938436B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877988A (en) * | 1996-07-26 | 1999-03-02 | Lg Semicon Co., Ltd. | Read/write control circuit for semiconductor memory device |
| US6208549B1 (en) * | 2000-02-24 | 2001-03-27 | Xilinx, Inc. | One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS |
| CN102460586A (en) * | 2009-06-15 | 2012-05-16 | 索尼公司 | Semiconductor device |
| CN103730163A (en) * | 2013-12-27 | 2014-04-16 | 深圳市国微电子有限公司 | Programmable storage system |
| CN112003606A (en) * | 2020-07-27 | 2020-11-27 | 北京炎黄国芯科技有限公司 | E-fuse programming and reading circuit |
-
2022
- 2022-03-09 CN CN202210225369.7A patent/CN115938436B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877988A (en) * | 1996-07-26 | 1999-03-02 | Lg Semicon Co., Ltd. | Read/write control circuit for semiconductor memory device |
| US6208549B1 (en) * | 2000-02-24 | 2001-03-27 | Xilinx, Inc. | One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS |
| CN102460586A (en) * | 2009-06-15 | 2012-05-16 | 索尼公司 | Semiconductor device |
| CN103730163A (en) * | 2013-12-27 | 2014-04-16 | 深圳市国微电子有限公司 | Programmable storage system |
| CN112003606A (en) * | 2020-07-27 | 2020-11-27 | 北京炎黄国芯科技有限公司 | E-fuse programming and reading circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115938436B (en) | 2023-09-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108694335B (en) | SRAM-based physical unclonable function and method for generating PUF response | |
| US7397714B2 (en) | Setting method of chip initial state | |
| KR0142277B1 (en) | Memory system | |
| CN112582013A (en) | Anti-fuse memory cell circuit, array circuit and read-write method thereof | |
| JP2008521157A (en) | Word line driver circuit for static random access memory | |
| US20080094898A1 (en) | Non-volatile semiconductor storage device | |
| US8483003B2 (en) | Semiconductor device and data processor | |
| CN210271793U (en) | Anti-fuse memory cell circuit and array circuit | |
| JP4478980B2 (en) | Fuse circuit and semiconductor device using the same | |
| KR20090121295A (en) | Integrated circuit fuse array | |
| US7848170B2 (en) | Nonvolatile semiconductor memory | |
| US10559350B2 (en) | Memory circuit and electronic device | |
| CN114765050A (en) | Memory device for detecting error bit and method thereof | |
| US6418045B2 (en) | Efficient and robust random access memory cell suitable for programmable logic configuration control | |
| CN115938436B (en) | Memory circuit and memory array | |
| US20050264334A1 (en) | Semiconductor integrated circuit using latch circuit with noise tolerance | |
| US7639551B2 (en) | Sense amplifiers operated under hamming distance methodology | |
| US6998873B2 (en) | Data input/output buffer and semiconductor memory device using the same | |
| US6392940B2 (en) | Semiconductor memory circuit | |
| EP1303044B1 (en) | Diode-based multiplexer | |
| US11928362B2 (en) | Fuse latch of semiconductor device for latching data of a repair fuse cell | |
| US10720190B2 (en) | Semiconductor devices and semiconductor systems including the same | |
| JP2010102779A (en) | Semiconductor storage device | |
| CN116564370A (en) | Power supply switching circuit and one-time programmable memory | |
| KR0182011B1 (en) | Write driver for stable output data |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |