CN115934029B

CN115934029B - Method, device, multiplier and medium for converting multiplication operation resources into logic resources

Info

Publication number: CN115934029B
Application number: CN202310133142.4A
Authority: CN
Inventors: 李艳华; 刘松涛; 刘海涛; 林永龙; 郝明星; 曲星; 徐沛庆
Original assignee: Chenxing Tianjin Automation Equipment Co ltd
Current assignee: Chenxing Tianjin Automation Equipment Co ltd
Priority date: 2023-02-20
Filing date: 2023-02-20
Publication date: 2023-05-30
Anticipated expiration: 2043-02-20
Also published as: CN115934029A

Abstract

The present disclosure relates to the field of numerical computer chip design technologies, and in particular, to a method, an apparatus, a multiplier, and a medium for converting multiplication resources into logic resources. The method comprises the following steps: setting storage variable information according to the acquired multiplication operation information, wherein the storage variable information comprises the bit width of a storage variable; if a preset relation is met between a value corresponding to a first preset bit of the bit width of the storage variable and a value corresponding to a second preset bit of the bit width of the storage variable in a preset calculation period, determining a processing mode of the storage variable information from the shift rule and/or the numerical calculation rule based on the shift rule and/or the numerical calculation rule corresponding to the preset relation, and determining final storage variable information according to the processing mode; based on a preset conversion rule, the final stored variable information is subjected to conversion processing, and operation result information corresponding to multiplication operation information is determined.

Description

Method, device, multiplier and medium for converting multiplication operation resources into logic resources

Technical Field

The present disclosure relates to the field of numerical computer chip design technologies, and in particular, to a method, an apparatus, a multiplier, and a medium for converting multiplication resources into logic resources.

Background

The current Zynq7020 integrates an ARM dual-core ex-A9 processor and an Xilinx7 series FPGA architecture, so that the Zynq7020 as a master control MCU integrating driving and controlling has great advantages in energy consumption, performance and the like; the zone control integrated system needs to meet the requirement of processing numerous functions, and the Zynq7020 has 53200 logic resources and 1330 chip selection resources, so that the processing of numerous functions can be efficiently finished.

However, the Zynq7020 has only 220 DSP (Digital Signal Processing, digital signal processor) operation resources, which is very limited, and when the motor is finely controlled by ynq7020, the operation amount is huge when the motor is finely controlled, the multiplication is performed by simply using DSP resources, and the operation is easily insufficient.

Disclosure of Invention

In order to improve multiplication capacity, the application provides a method, a device, a multiplier and a medium for converting multiplication resources into logic resources.

In a first aspect, the present application provides a method for converting multiplication resources into logic resources, which adopts the following technical scheme:

a method for converting logical resources by multiplication resources, comprising:

setting storage variable information according to the acquired multiplication operation information, wherein the storage variable information comprises the bit width of a storage variable;

If a preset relation is met between a value corresponding to a first preset bit of the bit width of the storage variable and a value corresponding to a second preset bit of the bit width of the storage variable in a preset calculation period, determining a processing mode of the storage variable information from the shifting rule and/or the numerical calculation rule based on the shifting rule and/or the numerical calculation rule corresponding to the preset relation, and determining final storage variable information according to the processing mode;

and based on a preset conversion rule, converting the final stored variable information to determine operation result information corresponding to the multiplication operation information.

By adopting the technical scheme, multiplication information is acquired, storage variable information containing the bit width of a storage variable is set according to the multiplication information, then, in a preset calculation period, a value corresponding to a first preset bit of the bit width of the storage variable is compared with a value corresponding to a second preset bit, the relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit is determined, the relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit is judged to meet the preset relation, the processing mode of the storage variable information is determined from a shift rule and/or a numerical calculation rule corresponding to the preset relation, final storage variable information is determined according to the corresponding processing mode, the final storage variable information contains an operation result corresponding to the multiplication information, and finally, the final storage variable information is converted based on a preset conversion rule, so as to further determine operation result information corresponding to the multiplication information; the shift and/or numerical calculation processing is carried out on the stored variable information to replace the multiplication processing on the multiplication information, so that the utilization of multiplication resources is reduced, and the calculation capability of the calculation processing process with huge calculation amount is improved.

In one possible implementation manner, the multiplication information includes a multiplier value, a multiplier bit width, and a multiplicand bit width, the storage variable information further includes an initial value of the storage variable information, and the setting the storage variable information according to the acquired multiplication information includes:

setting a bit width of the storage variable information based on the multiplier bit width and the multiplicand bit width;

setting an initial value of the storage variable information based on the multiplier value;

setting the storage variable information according to the bit width of the storage variable information and the initial value of the storage variable.

By adopting the technical scheme, the multiplication information comprises a multiplier value, a multiplier bit width and a multiplicand bit width, the multiplier bit width and the multiplicand bit width are used as information for setting the bit width of the storage variable information, the multiplier value is used as an initial value for setting the storage variable information, and then the storage variable information is set according to the bit width of the storage variable information and the initial value of the storage variable so as to determine the corresponding result of the multiplication information.

In one possible implementation, setting the storage variable information according to the obtained multiplication information further includes:

And setting a preset calculation period based on the multiplier bit width, wherein the preset calculation period is a calculation period which is undergone by shifting and/or calculating the storage variable information.

In one possible implementation, the setting the bit width of the storage variable information based on the multiplier bit width and the multiplicand bit width includes:

setting a first bit width of the storage variable information based on the multiplicand bit width;

setting a second bit width corresponding to the storage variable information based on the multiplier bit width;

setting a third bit width corresponding to the storage variable based on a preset bit width;

the bit width of the storage variable information is set based on the first bit width, the second bit width, and the third bit width.

By adopting the technical scheme, the bit width of the storage variable information is set to three areas, each area is set based on different information, the first bit width of the storage variable information is set based on the multiplicand bit width, the second bit width of the storage variable is set based on the multiplication bit width, and the third bit width corresponding to the storage variable is set based on the preset bit width.

In one possible implementation manner, if a preset relationship is satisfied between a value corresponding to a first preset bit of the bit width of the storage variable and a value corresponding to a second preset bit of the bit width of the storage variable in a preset calculation period, determining, based on a shift rule and/or a numerical calculation rule corresponding to the preset relationship, a processing manner of the storage variable information from the shift rule and/or the numerical calculation rule, where the processing manner includes:

If the value corresponding to the first preset bit of the bit width of the storage variable is equal to the value corresponding to the second preset bit in the preset calculation period, shifting the storage variable information based on a shifting rule that the value corresponding to the first preset bit is equal to the value corresponding to the second preset bit;

and if the value corresponding to the first preset bit of the bit width of the storage variable is not equal to the value corresponding to the second preset bit in the preset calculation period, carrying out shift and numerical calculation on the storage variable information based on a shift rule and a numerical calculation rule corresponding to the value corresponding to the first preset bit.

By adopting the technical scheme, the preset calculation period starts, the value corresponding to the first preset bit of the bit width of the storage variable is compared with the value corresponding to the second preset bit, the corresponding relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit is judged, and if the value corresponding to the first preset bit is determined to be equal to the value corresponding to the second preset bit, the rule of the processing mode of the corresponding storage variable is determined to be a displacement rule from the displacement rule and/or the numerical calculation rule, namely the storage variable information is subjected to displacement processing based on the displacement rule; and at the beginning of a preset calculation period, comparing a value corresponding to a first preset bit of the bit width of the storage variable with a value corresponding to a second preset bit, and judging that the value corresponding to the first preset bit is different from the value corresponding to the second preset bit, wherein at the moment, the rule of the processing mode corresponding to the storage variable information is determined as a displacement rule and a numerical calculation rule from the displacement rule and the numerical calculation rule, namely, the storage variable information is subjected to displacement processing and numerical calculation processing.

In one possible implementation manner, the preset computing period includes a plurality of preset sub-computing periods, and if in the preset computing period, a value corresponding to a first preset bit of the bit width of the storage variable and a value corresponding to a second preset bit of the bit width of the storage variable satisfy a preset relationship, determining a processing manner of the storage variable information from the shift rule and/or the numerical computing rule based on a shift rule and/or a numerical computing rule corresponding to the preset relationship, and determining final storage variable information according to the processing manner, where the determining includes:

in each preset sub-calculation period, judging the relation between the value corresponding to the first preset bit of the bit width of the storage variable and the value corresponding to the second preset bit of the bit width of the storage variable, determining the corresponding processing mode of the judged relation from a shift rule and/or a numerical calculation rule, processing the storage variable information, determining the corresponding sub-storage variable information in each preset sub-calculation period, and taking the preset sub-storage variable information determined in the last preset sub-calculation period as final storage variable information;

the sub-stored variable information corresponding to each preset sub-calculation period is used as the stored variable information of the next preset sub-calculation period adjacent to the preset sub-calculation period.

By adopting the technical scheme, the preset computing period comprises a plurality of preset sub-computing periods, each preset sub-computing period is a processing process, namely in each preset sub-computing period, a value corresponding to a first preset bit of the bit width of the storage variable is compared with a value corresponding to a second preset bit, the relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit is determined, then, the initial value of the storage variable is processed based on a shift rule and/or a numerical computing rule corresponding to the relation between the determined value corresponding to the first preset bit and the value corresponding to the second preset bit, and sub-storage variable information corresponding to each preset sub-computing period is determined, wherein the sub-storage variable information corresponding to each preset sub-computing period is used as storage variable information corresponding to the next sub-preset sub-computing period adjacent to each preset sub-computing period.

In one possible implementation manner, the shifting and numerical calculation of the storage variable information based on the shifting rule and the numerical calculation rule corresponding to the value corresponding to the first preset bit being not equal to the value corresponding to the second preset bit includes:

If the value corresponding to the first preset bit is larger than the value corresponding to the second preset bit, subtracting the value corresponding to the first bit width of the storage variable information from the multiplicand value based on the numerical calculation rule, and determining a new value corresponding to the first bit width;

determining first intermediate storage variable information based on the new value corresponding to the first bit width, the value corresponding to the second bit width, and the value corresponding to the third bit width;

based on the shift rule, discarding the third bit width and the value of the third bit width corresponding to the first intermediate storage variable information;

and supplementing the bit width of the highest bit in the first bit width corresponding to the first intermediate storage variable information and the value corresponding to the bit width of the highest bit to the highest bit corresponding to the first intermediate storage variable information after the discarding process is completed.

By adopting the technical scheme, when the value corresponding to the first preset bit is larger than the value of the second preset bit, determining that the rule for processing the storage variable information is a calculation rule and a displacement rule, at this time, calculating the difference between the value corresponding to the first bit width of the storage variable information and the multiplicand based on the determined corresponding calculation rule and displacement rule, further determining a new value corresponding to the first bit width, then constructing new storage variable information, namely first intermediate variable information, by the new value corresponding to the first bit width, the value corresponding to the second bit width and the value corresponding to the third bit width, then performing displacement processing on the first intermediate storage variable information based on the displacement rule, specifically discarding the value corresponding to the third bit width and the third bit width of the first intermediate storage variable information, at this time, reducing the bit width of the first intermediate storage variable to one bit width of the previous storage variable, then supplementing the bit width of the highest bit contained in the first bit width corresponding to the first intermediate storage variable information and the value corresponding to the first intermediate variable information after the first intermediate variable information has been subjected to displacement processing, and then completing the computation of the storage variable information.

In one possible implementation manner, the multiplication information includes a multiplicand value, and performing shift and numerical calculation on the storage variable information based on a shift rule and a numerical calculation rule corresponding to a value corresponding to the first preset bit being different from a value corresponding to the second preset bit, including:

if the value corresponding to the first preset bit is smaller than the value of the second preset bit, adding the value corresponding to the first bit width of the storage variable information to the multiplicand value based on the numerical calculation rule, and determining a new value corresponding to the first bit width;

determining second intermediate storage variable information based on the new value corresponding to the first bit width, the value corresponding to the second bit width, and the value corresponding to the third bit width;

and supplementing the bit width of the highest bit in the first bit width corresponding to the second intermediate storage variable information and the value corresponding to the bit width of the highest bit to the highest bit corresponding to the second intermediate storage variable information after the discarding process is completed.

By adopting the technical scheme, when the value corresponding to the first preset bit is smaller than the value of the second preset bit, determining that the rule for processing the storage variable information is a calculation rule and a displacement rule, at this time, adding the value corresponding to the first bit width of the storage variable information and a multiplicand based on the determined corresponding calculation rule and displacement rule, further determining a new value corresponding to the first bit width, then constructing new storage variable information, namely second intermediate variable information, by the new value corresponding to the first bit width, the value corresponding to the second bit width and the value corresponding to the third bit width, then carrying out displacement processing on the second intermediate storage variable information based on the displacement rule, specifically discarding the value corresponding to the third bit width and the third bit width of the second intermediate storage variable information, at this time, adding the bit width of the second intermediate storage variable with the bit width of the previous storage variable by one bit, complementing the bit width of the highest bit contained in the first bit width corresponding to the second intermediate storage variable information and the value corresponding to the second intermediate variable after the second intermediate variable information has been subjected to displacement processing, and then completing the displacement processing of the storage variable information.

In one possible implementation manner, the determining the new value corresponding to the first bit width further includes:

and if the bit width of the new value corresponding to the first bit width is larger than the first bit width, discarding the value corresponding to the part of the new value exceeding the first bit width.

By adopting the technical scheme, the new value with the first bit width is obtained by calculation processing based on the calculation rule, and the bit width of the new value is possibly larger than the bit width before calculation processing, so that after the new value with the first bit width is obtained by calculation processing, the bit width of the new value with the first bit width is compared with the bit width of the new value with the first bit width, and when the bit width of the new value with the first bit width is larger than the first bit width, the bit width of the new value needs to be subjected to bit reduction processing, namely, the value corresponding to the part of the bit width of the new value exceeding the first bit width is discarded, so that the bit width of the new value is ensured to be identical with the first bit width.

In one possible implementation manner, the converting the final stored variable information based on a preset conversion rule to determine operation result information corresponding to the multiplication operation information includes:

discarding the bit width and the value of the lowest bit corresponding to the final storage variable information, converting the final storage variable information of which the bit width and the value of the lowest bit are discarded, and determining operation result information corresponding to the multiplication operation information.

By adopting the technical scheme, the obtained final storage variable information contains the final result of multiplication, at this time, the lowest value corresponding to the final storage variable information is firstly abandoned, the binary final result is further obtained, and then the binary final result is converted, so that the final operation result information is obtained.

In a second aspect, the present application provides a device for converting multiplication resources into logic resources, which adopts the following technical scheme:

a multiplication resource conversion logic resource apparatus comprising: a variable information setting module, a final variable information determining module and an operation result information determining module, wherein,

the variable information setting module is used for setting storage variable information according to the acquired multiplication operation information, wherein the storage variable information comprises the bit width of a storage variable;

the final variable information determining module is used for determining a processing mode of the storage variable information from the shifting rule and/or the numerical value calculating rule based on the shifting rule and/or the numerical value calculating rule corresponding to the preset relation if the preset relation is met between the value corresponding to the first preset bit of the bit width of the storage variable and the value corresponding to the second preset bit of the bit width of the storage variable in the preset calculating period, and determining the final storage variable information according to the processing mode;

And the operation result information determining module is used for converting the final stored variable information based on a preset conversion rule and determining operation result information corresponding to the multiplication operation information.

By adopting the technical scheme, the variable information setting module acquires multiplication information, sets storage variable information comprising an initial value of a storage variable and a bit width of the storage variable according to the multiplication information, then, the final variable information determining module compares a value corresponding to a first preset bit of the storage variable with a value corresponding to a second preset bit in a preset calculation period, determines a relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit, judges that the relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit meets the preset relation, determines a processing mode of the storage variable information from a shift rule and/or a numerical calculation rule corresponding to the preset relation, determines final storage variable information according to the corresponding processing mode, and further determines an operation result corresponding to the multiplication information in the final storage variable information, wherein the final storage variable information is converted based on a preset conversion rule, and further determines operation result information corresponding to the multiplication information; the shift and/or numerical calculation processing is carried out on the stored variable information to replace the multiplication processing on the multiplication information, so that the utilization of multiplication resources is reduced, and the calculation capability of the calculation processing process with huge calculation amount is improved.

In one possible implementation, the multiplication information includes a multiplier value, a multiplier bit width, and a multiplicand bit width, and the storage variable information further includes: storing an initial value of variable information; the variable information setting module further includes:

a bit width setting unit configured to set a bit width of the storage variable information based on the multiplier bit width and the multiplicand bit width;

an initial value setting unit configured to set an initial value of the storage variable information based on the multiplier value;

and the variable information setting unit is used for setting the storage variable information according to the bit width of the storage variable information and the initial value of the storage variable.

In one possible implementation manner, the multiplication resource conversion logic resource device further includes: a period setting module, wherein,

and the period setting module is used for setting a preset calculation period based on the multiplier bit width, wherein the preset calculation period is a calculation period which is undergone by shifting and/or calculating the storage variable information.

In one possible implementation manner, the bit width setting unit is specifically configured to:

In one possible implementation manner, the multiplication resource conversion logic resource device further includes: a first variable processing module and a second variable processing module, wherein,

the first variable processing module is used for shifting the storage variable information based on a shifting rule that the value corresponding to the first preset bit is equal to the value corresponding to the second preset bit if the value corresponding to the first preset bit of the bit width of the storage variable is equal to the value corresponding to the second preset bit in a preset calculation period, so as to determine final storage variable information;

and the second variable processing module is used for carrying out shift and numerical calculation on the storage variable information based on a shift rule and a numerical calculation rule corresponding to a value corresponding to a second preset bit when the value corresponding to a first preset bit of the bit width of the storage variable is not equal to the value corresponding to the second preset bit in a preset calculation period, and determining final storage variable information.

In one possible implementation manner, the final variable information determining module further includes: a first variable information determination unit, wherein,

a first variable information determining unit, configured to determine, in each preset sub-calculation period, a relationship between a value corresponding to a first preset bit of a bit width of the storage variable and a value corresponding to a second preset bit of the bit width of the storage variable, determine a corresponding processing manner of the determined relationship from a shift rule and/or a numerical calculation rule, process the storage variable information, determine sub-storage variable information corresponding to each preset sub-calculation period, and use the preset sub-storage variable information determined in a last preset sub-calculation period as final storage variable information; the sub-stored variable information corresponding to each preset sub-calculation period is used as the stored variable information of the next preset sub-calculation period adjacent to the preset sub-calculation period.

In one possible implementation manner, the second variable processing module further includes: a first bit width new value determining unit, a second variable information determining unit, and a first variable shifting unit, wherein,

a first bit width new value determining unit, configured to, if the value corresponding to the first preset bit is greater than the value corresponding to the second preset bit, subtract the value corresponding to the first bit width of the storage variable information from the multiplicand value based on the numerical calculation rule, and determine a new value corresponding to the first bit width;

A second variable information determining unit configured to determine first intermediate storage variable information based on a new value corresponding to the first bit width, a value corresponding to the second bit width, and a value corresponding to the third bit width;

the first variable displacement unit is used for discarding the third bit width and the value of the third bit width corresponding to the first intermediate storage variable information based on a displacement rule; and supplementing the bit width of the highest bit in the first bit width corresponding to the first intermediate storage variable information and the value corresponding to the bit width of the highest bit to the highest bit corresponding to the first intermediate storage variable information after the discarding process is completed.

In one possible implementation manner, the multiplication resource conversion logic resource device further includes: a second bit width new value determining unit, a third variable information determining unit, and a second variable shifting unit, wherein,

a second bit width new value determining unit, configured to, if the value corresponding to the first preset bit is smaller than the value of the second preset bit, add the value corresponding to the first bit width of the storage variable information to a multiplicand value based on the numerical calculation rule, and determine a new value corresponding to the first bit width;

a third variable information determining unit configured to determine second intermediate storage variable information based on the new value corresponding to the first bit width, the value corresponding to the second bit width, and the value corresponding to the third bit width;

The second variable shifting unit is used for discarding the third bit width and the value of the third bit width corresponding to the first intermediate storage variable information based on the shifting rule; and supplementing the bit width of the highest bit in the first bit width corresponding to the second intermediate storage variable information and the value corresponding to the bit width of the highest bit to the highest bit corresponding to the second intermediate storage variable information after the discarding process is completed.

In one possible implementation manner, the multiplication resource conversion logic resource device further includes: a bit-width value discard module, wherein,

and the bit width value discarding module is used for discarding the value corresponding to the part of the new value exceeding the first bit width if the bit width of the new value corresponding to the first bit width is larger than the first bit width.

In one possible implementation manner, the operation result information determining module further includes: a result information determination unit, wherein,

and the result information determining unit is used for discarding the bit width and the value of the lowest bit corresponding to the final storage variable information, converting the final storage variable information of which the bit width and the value of the lowest bit are discarded, and determining operation result information corresponding to the multiplication operation information.

In a third aspect, the present application provides a multiplier, which adopts the following technical scheme:

a multiplier, the multiplier comprising:

at least one processor;

a memory;

at least one application program, wherein the at least one application program is stored in the memory and configured to be executed by the at least one processor, the at least one application program configured to: and executing the method for converting the logical resources by the multiplication resources.

In a fourth aspect, the present application provides a numerical computer readable medium, which adopts the following technical scheme:

a numerical computer readable medium comprising: a numerical computer program is stored that can be loaded by a processor and that performs the above-described method of converting logical resources by multiplying resources.

In summary, the present application includes the following beneficial technical effects:

obtaining multiplication information, setting storage variable information comprising an initial value of a storage variable and a bit width of the storage variable according to the multiplication information, comparing a value corresponding to a first preset bit of the storage variable with a value corresponding to a second preset bit in a preset calculation period, determining a relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit, judging that the relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit meets the preset relation, determining a processing mode of the initial value of the storage variable from a shift rule and/or a numerical calculation rule corresponding to the preset relation, determining final storage variable information according to the corresponding processing mode, converting the final storage variable information based on a preset conversion rule, and further determining operation result information corresponding to the multiplication information; the shift and/or numerical calculation processing is carried out on the stored variable information to replace the multiplication processing on the multiplication information, so that the utilization of multiplication resources is reduced, and the calculation capability of the calculation processing process with huge calculation amount is improved.

Drawings

FIG. 1 is a flow chart of a method for converting logical resources by multiplication resources according to an embodiment of the present application;

FIG. 2 is a flow diagram of an example of a multiplication resource conversion logic resource according to an embodiment of the present application;

FIG. 3 is a block diagram of a device for converting logical resources by multiplication resources according to an embodiment of the present application;

fig. 4 is a schematic diagram of a multiplier according to an embodiment of the present application.

Detailed Description

The present application is described in further detail below in conjunction with figures 1-4.

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The embodiment of the application provides a method for converting multiplication operation resources into logic resources, which is executed by a multiplier, and referring to fig. 1, the method comprises the following steps: step S101, step S102, and step S103, wherein,

S101, setting storage variable information according to the obtained multiplication information.

For the embodiments of the present application, the multiplication information includes a multiplier value, a multiplier bit width, a multiplicand value, and a multiplicand bit width, and the storage variable information includes an initial value of the storage variable and a bit width of the storage variable.

After the multiplier obtains the multiplication information, the multiplier analyzes the multiplication information to determine a multiplier value, a multiplier bit width, a multiplicand value and a multiplicand bit width contained therein, and then the multiplier sets the function of the multiplier value, the multiplier bit width, the multiplicand value and the multiplicand bit width in the process of setting the storage variable information, for example, sets the bit width corresponding to the storage variable information based on the multiplier bit width and the multiplicand bit width, sets the initial value corresponding to the storage variable information based on the multiplier value, and the like, so as to complete the setting of the storage variable information.

Specifically, since the multiplier generally performs processing in a binary form in the operation processing process, two ways of obtaining multiplication information may be adopted, namely, one way, a technician inputs initial multiplication information including other binary multiplication values, multiplicand values, multiplication bit widths and multiplicand bit widths except binary into the multiplier, and the multiplier performs binary conversion on the other binary multiplication values and the multiplicand values included in the initial multiplication information to obtain the binary multiplication values and the multiplicand values, and obtains corresponding binary bit widths respectively at the same time, that is, obtains the multiplication information; in the second mode, the technician directly inputs multiplication information including binary multiplier value, multiplied value, multiplier bit width and multiplicand bit width into the multiplier, and the multiplier directly obtains the information.

The method for setting the stored variable information by the value description can also be that a technician obtains the stored variable information by manually calculating the setting according to the existing multiplication information, and then the technician inputs the stored variable information into a value multiplier through a terminal device so as to finish the setting of the stored variable information.

S102, if a preset relation is met between a value corresponding to a first preset bit of the bit width of the storage variable and a value corresponding to a second preset bit of the bit width of the storage variable in a preset calculation period, determining a processing mode of the storage variable information from the shift rule and/or the numerical calculation rule based on the shift rule and/or the numerical calculation rule corresponding to the preset relation, and determining final storage variable information according to the processing mode.

For the embodiment of the application, the multiplier presets the first preset bit and the second preset bit, after the storage variable information is set, the first preset bit and the second preset bit corresponding to the storage variable information are determined, and the multiplier takes the value of the first preset bit and the value of the second preset bit corresponding to the storage variable information as a judging condition for determining what processing is performed on the storage variable information.

When the multiplier sets the storage variable information, a preset calculation period of the multiplier starts, that is, a calculation period of processing the storage variable information starts, firstly, the multiplier determines a value corresponding to a first preset bit of a bit width of the storage variable and a value corresponding to a second preset bit, for example, the first preset bit is a next lower bit of the bit width 0000 0000 0 (in the embodiment of the application, a space is added after each 4 bits of bit width of the binary number is exemplified for better understanding), the second preset bit stores the lowest bit of the bit width 0000 0000 0 of the variable, then the value corresponding to the first preset bit is compared with the value corresponding to the second preset bit to determine a size relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit, and the multiplier determines a processing mode corresponding to the size relation from a shift rule and/or a calculation rule preset in advance so as to process the storage variable information, and further determine final storage variable information containing a calculation result after the processing of the storage variable information is completed through the determined processing mode; the shift rule comprises right shift and left shift of the storage variable information, and the calculation rule comprises addition calculation and subtraction calculation of the storage variable information.

S103, based on a preset conversion rule, converting the final stored variable information to determine operation result information corresponding to the multiplication operation information.

For the embodiment of the present application, the preset conversion rule includes a shift rule and a binary conversion rule, that is, shift processing and binary conversion processing are performed on the storage variable information.

Based on a shift rule and/or a calculation rule, after the storage variable information is processed in a preset calculation period, the obtained final storage variable information contains a calculation result obtained by multiplying a multiplier value and a multiplicand value, the form of the calculation result presented in the final storage variable information cannot be directly obtained, and a final presentable result can be obtained after corresponding shift processing and conversion processing is carried out, so that after the final storage variable information is determined, a multiplier invokes the conversion processing of the preset conversion rule on the final storage variable information, and the presentable operation result information is determined from the final storage variable information; therefore, the processing mode of equivalent multiplication effect is realized by taking the stored variable information as an intermediate variable to replace a multiplier value and a multiplicand value, so that operation result information is obtained, the utilization of multiplication operation resources is reduced, and the processing capacity of the multiplier to a processing process with huge operation amount is improved.

The multiplier obtains multiplication information, sets storage variable information comprising an initial value of a storage variable and a bit width of the storage variable according to the multiplication information, then compares a value corresponding to a first preset bit of the storage variable with a value corresponding to a second preset bit in a preset calculation period, determines a relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit, judges that the relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit meets a preset relation, then determines a processing mode of the storage variable information from a shift rule and/or a numerical calculation rule corresponding to the preset relation, determines final storage variable information according to the corresponding processing mode, and further converts the final storage variable information based on a preset conversion rule to further determine operation result information corresponding to the multiplication variable information; the shift and/or numerical calculation processing is carried out on the stored variable information to replace the multiplication processing on the multiplication information, so that the utilization of multiplication resources is reduced, and the calculation capability of the calculation processing process with huge calculation amount is improved.

Specifically, in step S101, storage variable information is set according to the acquired multiplication information, including: setting a bit width of the storage variable information based on the multiplied bit width and the multiplicand bit width; setting an initial value of the stored variable information based on the multiplier value; the storage variable information is set according to the bit width of the storage variable information and the initial value of the storage variable.

For the embodiment of the application, the multiplier processing is performed in binary form, so that the multiplier, the multiplicand and the storage variable information are in binary form, in the process of determining the storage variable information according to the multiplication operation information, the initial value of the storage variable can be determined according to the multiplier value, for example, the multiplier value is 110, the initial value of the storage variable can be obtained by shifting or directly adding the multiplier value, for example, the multiplier value 110 is shifted to the left by one bit, the multiplier value at this time is 1100, or the multiplier value at this time is 110, namely, the value of the multiplication is the initial value of the storage variable, but the bit width of the storage variable cannot be determined only by the multiplier value and the multiplicand value, and because the bit widths of the multiplier value and the multiplicand value can be defined as the bit widths of any size if the multiplier value and the multiplicand value are not changed, namely, the bit widths of the storage variable are required to be zero-added before the most significant digit, so that the bit width of the storage variable is determined, for example, the bit width of the storage variable is set based on the multiplier value and the multiplier bit width is 110, and the bit width is added; the multiplier is also preset with a preset bit width, and the preset bit width participates in the setting of the bit width of the storage variable based on the multiplying digital width and the multiplicand bit width.

Further, the process of setting the bit width of the storage variable information based on the multiplied bit width and the multiplicand bit width specifically includes: setting a first bit width of the storage variable information based on the multiplicand bit width; setting a second bit width corresponding to the storage variable information based on the multiplied bit width; setting a third bit width corresponding to the storage variable based on the preset bit width; the bit width of the storage variable information is set based on the first bit width, the second bit width, and the third bit width.

For the embodiment of the present application, after the multiplier obtains the multiplier digital width and the multiplicand bit width, in the process of setting the bit width of the storage variable, the bit width of the storage variable is set to three areas, the bit width of the storage variable is set based on each area, so as to quickly complete the setting of the bit width of the storage variable, concretely, the multiplier obtains the multiplier digital width, takes the multiplier digital width as the bit width of the first bit width of the storage variable information, takes the multiplier bit width as the bit width of the second bit width of the storage variable information pair, then the multiplier takes the bit width preset in advance as the bit width of the third bit width of the storage variable information, for example, the multiplier digital width and the multiplicand bit width are both 0000, takes the multiplier bit width 0000 as the first bit width of the storage variable information, takes the multiplier bit width 0000 as the second bit width of the storage variable information, and the multiplier bit width is added to obtain the bit width 0000 0000, and the third bit width 0000 0000 of the preset bit 0 is taken as the storage variable information, so as to obtain the bit width 0000 0000 0 corresponding to the storage variable information.

After the multiplier sets the storage variable information, processing the storage variable information in a preset computing period is started, and the multiplier determines the processing mode of the storage variable information from the shifting rule and/or the numerical computing rule based on the shifting rule and/or the numerical computing rule corresponding to the preset relation if the value corresponding to the first preset bit of the storage variable and the value corresponding to the second preset bit of the storage variable meet the preset relation in the preset computing period, wherein the preset relation is equal and different based on the magnitude relation between the value corresponding to the first preset bit and the value corresponding to the second preset bit, and the processing mode comprises the following two conditions:

case one: and if the value corresponding to the first preset bit of the bit width of the storage variable is equal to the value corresponding to the second preset bit in the preset calculation period, shifting the storage variable information based on a shifting rule corresponding to the value corresponding to the first preset bit is equal to the value corresponding to the second preset bit.

Specifically, the processing rules corresponding to the preset relation comprise three processing rules, namely a first rule and a second rule, wherein the first rule only carries out shift processing based on the shift rules; rule two, only carry on the calculation processing based on calculation rule; and rule III, performing processing based on the shift rule and the calculation rule.

The multiplier judges the preset relation that the value corresponding to the first preset bit of the bit width of the storage variable is equal to the value corresponding to the second preset bit in the preset calculation period, at the moment, the multiplier determines that the current preset relation meets a first rule from three processing rules, namely, only shift processing based on the shift rule is carried out, and then the multiplier invokes the shift rule to complete shift processing on the storage variable information.

And a second case: and if the value corresponding to the first preset bit of the bit width of the storage variable is not equal to the value corresponding to the second preset bit in the preset calculation period, carrying out shift and numerical calculation on the storage variable information based on a shift rule and a numerical calculation rule corresponding to the value corresponding to the first preset bit.

Specifically, the multiplier judges a preset relation that a value corresponding to a first preset bit of the bit width of the storage variable is unequal to a value corresponding to a second preset bit in a preset calculation period, at the moment, the multiplier determines that the current preset relation meets a third rule from three processing rules, namely, processing based on a shifting rule and a numerical calculation rule is performed, and then the multiplier invokes the shifting rule and the numerical calculation rule to complete shifting processing of the storage variable information, wherein the multiplier firstly performs calculation processing on the storage variable information based on the numerical calculation rule, and then the multiplier performs shifting processing on the storage variable information after the calculation processing is completed based on the shifting rule.

Further, when the multiplier determines that the value corresponding to the first preset bit of the stored variable information is not equal to the value corresponding to the second preset bit, two situations exist between the value corresponding to the first preset bit and the value corresponding to the second preset bit at this time: case one: the value corresponding to the first preset bit is larger than the value corresponding to the second preset bit; and a second case: the value corresponding to the first preset bit is smaller than the value corresponding to the second preset bit; although the stored variable information is required to be calculated in both cases, there is a difference in the calculation process, so that the stored variable information is shifted and the value calculated in the corresponding shifting rule and the value calculation rule based on the fact that the value corresponding to the first preset bit is not equal to the value corresponding to the second preset bit, including: if the value corresponding to the first preset bit is larger than the value corresponding to the second preset bit, subtracting the value corresponding to the first bit width of the stored variable information from the multiplicand value based on a numerical calculation rule, and determining a new value corresponding to the first bit width; determining first intermediate storage variable information based on the new value corresponding to the first bit width, the value corresponding to the second bit width, and the value corresponding to the third bit width; based on a shift rule, discarding the third bit width and the value of the third bit width corresponding to the first intermediate storage variable information; and supplementing the bit width of the highest bit in the first bit width corresponding to the first intermediate storage variable information and the value corresponding to the bit width of the highest bit to the highest bit corresponding to the first intermediate storage variable information after the discarding process is completed.

Specifically, the multiplier judges that the value corresponding to the stored first preset bit is larger than the value corresponding to the second preset bit, at this moment, the multiplier comprises subtraction calculation based on the determined calculation rule, then the multiplier processes the stored variable information based on the calculation rule and the shift rule, wherein the multiplier firstly determines the value corresponding to the first bit width of the stored variable information, subtracts the value corresponding to the first bit width from the multiplicand value, takes the new value obtained by subtracting the value corresponding to the first bit width from the multiplicand value as the new value of the first bit width, and then the multiplier reorganizes the stored variable information based on the new value of the first bit width, namely the multiplier replaces the original value of the first bit width with the new value, other bit width areas of the stored variable are unchanged, so that new stored variable information, namely first intermediate stored variable information, is obtained, and the calculation processing of the stored variable information is ended up until the moment; and then, the multiplier shifts the first intermediate storage variable information based on a corresponding shifting rule, namely, the first intermediate storage variable information is shifted to the right by one bit, the multiplier discards the third bit width corresponding to the first intermediate storage variable information and the value corresponding to the third bit width, and meanwhile, the bit width of the highest bit contained in the first bit width corresponding to the first intermediate storage variable information and the value complement of the highest bit are added to the highest bit corresponding to the first intermediate storage variable information, the value corresponding to the third bit width of which is discarded, so that the shifting of the first intermediate storage variable information is completed.

For example, the storage variable information is 1100 0011 0, the first bit width is 1100, the second bit width is 0011, the third bit width is 0, and the multiplicand is 0100; firstly, the multiplier subtracts a value 1100 corresponding to the first bit width of the storage variable information from a multiplicand value 0100 to obtain a new value 1000 corresponding to the first bit width, then combines the new value 1000 corresponding to the first bit width, a second bit width 0011 and a third bit width 0 to obtain first intermediate storage variable information 1000 0011 0, then the multiplier discards the third bit width 0 of the first intermediate storage variable information, and simultaneously, complements the value 1 of the highest bit included in the first bit width corresponding to the first intermediate storage variable information to the highest bit corresponding to the first intermediate storage variable information for which the value 0 corresponding to the third bit width is discarded, to obtain 1100 0011 1, thereby completing the shift of the first intermediate storage variable information.

It should be noted that, if the value corresponding to the first bit width of the stored variable information is subtracted from the multiplicand value to be negative, and the highest bit of the new value obtained after subtraction is 0, the highest bit 0 is changed to 1, so as to indicate that the new value corresponding to the first bit width obtained by subtraction is negative.

Further, performing shift and numerical calculation on the storage variable information based on a corresponding shift rule and a numerical calculation rule that a value corresponding to the first preset bit is not equal to a value corresponding to the second preset bit, further including: if the value corresponding to the first preset bit is smaller than the value of the second preset bit, adding the value corresponding to the first bit width of the stored variable information with the multiplicand value based on a numerical calculation rule, and determining a new value corresponding to the first bit width; determining second intermediate storage variable information based on the new value corresponding to the first bit width, the value corresponding to the second bit width, and the value corresponding to the third bit width; based on a shift rule, discarding the third bit width and the value of the third bit width corresponding to the first intermediate storage variable information; and supplementing the bit width of the highest bit in the first bit width corresponding to the second intermediate storage variable information and the value corresponding to the bit width of the highest bit to the highest bit corresponding to the second intermediate storage variable information after the discarding process is completed.

Specifically, the multiplier judges that the value corresponding to the stored first preset bit is smaller than the value corresponding to the second preset bit, at this time, the multiplier carries out addition calculation based on the determined calculation rule, immediately, the multiplier carries out displacement processing on the stored variable information based on the calculation rule and the displacement rule, wherein the multiplier firstly determines the value corresponding to the first bit width of the stored variable information, adds the value corresponding to the first bit width to the multiplicand value, takes the new value obtained by adding the value corresponding to the first bit width as the new value of the first bit width, then, the multiplier rearranges the stored variable information based on the new value of the first bit width, namely, the multiplier replaces the value of the original first bit width with the new value, other bit width areas of the stored variable are unchanged, so that new stored variable information, namely, second intermediate stored variable information is obtained, and finally, the multiplier carries out displacement processing on the second intermediate stored variable information based on the corresponding displacement rule, namely, the multiplier shifts the second intermediate stored variable information to the right by one bit, and meanwhile, the multiplier discards the value corresponding to the second intermediate stored variable information corresponding to the highest bit width of the second intermediate stored variable information, and the maximum value corresponding to the second intermediate stored variable information is completely displaced to the highest bit corresponding to the second intermediate stored variable information.

For example, the storage variable information is 0011 0011 0, the first bit width is 0011, the second bit width is 0011, the third bit width is 0, and the multiplicand is 0100; firstly, a multiplier adds a value 0011 corresponding to a first bit width of storage variable information and a multiplicand value 0100 to obtain a new value 0111 corresponding to the first bit width, then combines the new value 0111 corresponding to the first bit width, a second bit width 0011 and a third bit width 0 to obtain second intermediate storage variable information 0111 0011 0, and then the multiplier discards the third bit width 0 of the second intermediate storage variable information, and meanwhile, complements the value 0 of the highest bit included in the first bit width corresponding to the second intermediate storage variable information to the highest bit corresponding to the second intermediate storage variable information of which the value 0 corresponding to the third bit width is discarded to obtain 0011 1001 1, thereby completing the shift of the second intermediate storage variable information.

Further stated, the multiplier obtains a new value corresponding to a new value after adding the value corresponding to the first bit width and the multiplicand value, where the new value corresponding to the first bit width needs to be processed correspondingly to ensure the correctness of the subsequent processing, and specifically, after determining the new value corresponding to the first bit width, the multiplier further includes: and if the bit width of the new value corresponding to the first bit width is larger than the first bit width, discarding the value corresponding to the part of the new value exceeding the first bit width.

For example, the storage variable information is 1111 1000 1, the first bit width is 1111, the second bit width is 1000, the third bit width is 1, the multiplicand is 0100, the value obtained by adding the first bit width 1111 and the multiplicand 0100 is 10011, and the bit width of the value 10011 is larger than the bit width of the first bit width, so the multiplier discards the highest bit 1 of the value to obtain a value 0011, and the value 0011 is a new value corresponding to the first bit width.

Specifically, when the multiplier sets a preset calculation period, the preset calculation period comprises a plurality of preset sub-calculation periods, each preset sub-calculation period is used as a calculation unit, namely, one multiplication calculation period can be converted into a plurality of sub-periods, the corresponding calculation processing process of the multiplier is ensured to be completed in a single calculation period, and further the situation that the calculation cannot be completed in the calculation period due to huge calculation processing amount in one multiplication calculation period is avoided; therefore, in step 102, if the preset relationship is satisfied between the value corresponding to the first preset bit of the bit width of the storage variable and the value corresponding to the second preset bit of the bit width of the storage variable in the preset calculation period, the processing manner of the storage variable information is determined from the shift rule and/or the numerical calculation rule based on the shift rule and/or the numerical calculation rule corresponding to the preset relationship, and the final storage variable information is determined according to the processing manner, including: in each preset sub-calculation period, judging the relation between the value corresponding to the first preset bit of the bit width of the storage variable and the value corresponding to the second preset bit of the bit width of the storage variable, determining the corresponding processing mode of the judged relation from the shift rule and/or the numerical calculation rule, processing the storage variable information, and determining the corresponding sub-storage variable information in each preset sub-calculation period.

Specifically, each preset sub-calculation period is used as a processing period of the storage variable information, namely, in each preset sub-calculation period, the relation judgment of the value corresponding to the first preset bit of the bit width of the storage variable and the value corresponding to the second preset bit of the bit width of the storage variable is completed, the rule for processing the storage variable information is determined, the processing of the storage variable information is performed based on the corresponding rule, and the process of the sub-storage variable information corresponding to each preset sub-period is determined; taking the preset sub-storage variable information determined in the last preset sub-calculation period as final storage variable information; the sub-stored variable information corresponding to each preset sub-calculation period is used as the stored variable information of the next preset sub-calculation period adjacent to each preset sub-calculation period.

Further, in step S101, the stored variable information is set according to the obtained multiplication information, and then further includes: based on the multiplied digital width, a preset calculation period is set, which is a calculation period that is undergone by shifting and/or calculating the stored variable information. For example, when the multiplier bit width included in the multiplier operation information is 4, the preset calculation period set by the multiplier is a calculation period composed of four sub-preset calculation periods; and outputting final stored variable information after the fourth sub-preset calculation period is finished, namely finishing the processing of the stored variable information.

In step S103, based on a preset conversion rule, conversion processing is performed on the final stored variable information, and operation result information corresponding to the multiplication operation information is determined, which specifically includes: and discarding the bit width and the value of the least significant bit corresponding to the final storage variable information, converting the final storage variable information of which the bit width and the value of the least significant bit are discarded, and determining operation result information corresponding to the multiplication operation information.

For the embodiment of the application, the multiplier determines the final storage variable information, the final storage variable information at this time includes an operation result and other information preset by the multiplier, the final storage variable information is directly subjected to binary conversion, the obtained result is not a required result, corresponding processing is required before the final storage variable information is subjected to binary conversion, so that other information preset by the multiplier is removed, for example, the final storage variable information is 0001 1000 0, the multiplier discards the lowest bit 0 of the final storage variable information, and then decimal conversion is performed on the final storage variable information to obtain 24, namely operation result information, wherein the binary form of the operation result information is not particularly limited in the embodiment of the application, and can be modified correspondingly based on requirements.

Referring to FIG. 2, FIG. 2 provides an example of a multiplication resource conversion logic resource, with a multiplicand of 4 and a binary form of 0100; multiplier 6 and binary form 0110; setting the bit width of the storage variable based on the multiplication bit width and the multiplicand bit width, and simultaneously shifting the binary form multiplier value leftwards by one bit to set the initial value of the storage variable to obtain the storage variable P= 0000 0110 0; in the first calculation period, the lowest bit and the next lower bit of the storage variable P are equal, the whole storage variable P is shifted to one bit to the right, and the highest bit of the storage variable P is complemented to the highest bit of the storage variable P which is shifted to one bit to the right, so that the storage variable P1= 0000 0011 0 is obtained; in the second calculation period, determining that the lowest bit of the storage variable P1 is smaller than the next lowest bit, subtracting the multiplicand 0100 from the value 0000 corresponding to the first bit width of the storage variable P1 to obtain a new value 1100 corresponding to the first bit width, combining the new value 1100 with a part except the new value to obtain a new P1= 1100 0011 0, right-shifting the new P1= 1100 0011 0 by one bit, and compensating the highest bit of the new P1 to the highest bit of the new PI subjected to right-shifting by one bit to obtain a storage variable P2= 1110 0001 1; in the third calculation period, determining that the lowest order of the storage variable P2 is equal to the next lowest order, shifting the whole storage variable P2 by one order, and supplementing the highest order of the storage variable P to the highest order of the storage variable P2 which is shifted by one order to obtain a storage variable P3= 1111 0000 1; in a fourth calculation period, determining that the lowest bit of the storage variable P3 is greater than the next lowest bit, adding a value 1111 corresponding to the first bit width of the storage variable P3 to a multiplicand 0100 to obtain a new value 0011 corresponding to the first bit width, combining the new value 0011 with a part except the new value to obtain a new p3= 0011 0000 1, right-shifting the new p3= 0011 0000 1 by one bit, and compensating the highest bit of the new P3 to the highest bit of the new P3 which has been right-shifted by one bit to obtain a storage variable p4= 0001 1000 0; at this time, the calculation cycle is equivalent to the multiplication bit width, the calculation is completed, the lowest bit of p4= 0001 1000 0 is discarded, and a binary result 0001 1000 is obtained, and the binary result is subjected to binary conversion to obtain an operation result 24.

The above embodiments describe a method for converting logical resources by using multiplication resources from the viewpoint of a method flow, and the following embodiments describe an apparatus for converting logical resources by using multiplication resources from the viewpoint of a virtual module or a virtual unit, which will be described in detail in the following embodiments.

Referring to fig. 3, the multiplication resource conversion logic resource apparatus 30 may specifically include: a variable information setting module 301, a final variable information determining module 302, and an operation result information determining module 303, wherein,

a variable information setting module 301, configured to set storage variable information according to the obtained multiplication information, where the storage variable information includes a bit width of a storage variable;

the final variable information determining module 302 is configured to determine, if a value corresponding to a first preset bit of the bit width of the storage variable and a value corresponding to a second preset bit of the bit width of the storage variable satisfy a preset relationship in a preset calculation period, a processing manner of the storage variable information from the shift rule and/or the numerical calculation rule based on the shift rule and/or the numerical calculation rule corresponding to the preset relationship, and determine the final storage variable information according to the processing manner;

the operation result information determining module 303 is configured to perform conversion processing on the final stored variable information based on a preset conversion rule, and determine operation result information corresponding to the multiplication operation information.

In one possible implementation manner of the embodiment of the present application, the multiplication information includes a multiplier value, a multiplier bit width, and a multiplicand bit width, and storing variable information further includes: storing an initial value of variable information; the variable information setting module 301 further includes:

a bit width setting unit for setting a bit width for storing variable information based on the multiplied bit width and the multiplicand bit width;

an initial value setting unit configured to set an initial value of the stored variable information based on the multiplier value;

and the variable information setting unit is used for setting the stored variable information according to the bit width of the stored variable information and the initial value of the stored variable.

In one possible implementation manner of the embodiment of the present application, the multiplication resource conversion logic resource device 30 further includes: a period setting module, wherein,

the period setting module is used for setting a preset calculation period based on the multiplied digital width, wherein the preset calculation period is a calculation period which is undergone by shifting and/or calculating the stored variable information.

One possible implementation manner of the embodiment of the present application is a bit width setting unit, which is specifically configured to:

setting a second bit width corresponding to the storage variable information based on the multiplied bit width;

Setting a third bit width corresponding to the storage variable based on the preset bit width;

In one possible implementation manner of the embodiment of the present application, the multiplication resource conversion logic resource device 30 further includes: a first variable processing module and a second variable processing module, wherein,

the first variable processing module is used for shifting the storage variable information based on a corresponding shifting rule that the value corresponding to the first preset bit is equal to the value corresponding to the second preset bit if the value corresponding to the first preset bit of the bit width of the storage variable is equal to the value corresponding to the second preset bit in a preset calculation period;

and the second variable processing module is used for shifting and calculating the value of the stored variable information based on a corresponding shifting rule and a value calculation rule that the value corresponding to the first preset bit is not equal to the value corresponding to the second preset bit if the value corresponding to the first preset bit of the bit width of the stored variable is not equal to the value corresponding to the second preset bit in the preset calculation period.

In one possible implementation manner of the embodiment of the present application, the final variable information determining module 302 further includes: a first variable information determination unit, wherein,

The first variable information determining unit is used for determining the relation between the value corresponding to the first preset bit of the bit width of the storage variable and the value corresponding to the second preset bit of the bit width of the storage variable in each preset sub-calculation period, determining the corresponding processing mode of the determined relation from the shift rule and/or the numerical value calculation rule, processing the storage variable information, determining the corresponding sub-storage variable information in each preset sub-calculation period, and taking the preset sub-storage variable information determined in the last preset sub-calculation period as final storage variable information; the sub-stored variable information corresponding to each preset sub-calculation period is used as the stored variable information of the next preset sub-calculation period adjacent to each preset sub-calculation period.

In one possible implementation manner of the embodiment of the present application, the second variable processing module further includes: a first bit width new value determining unit, a second variable information determining unit, and a first variable shifting unit, wherein,

a first bit width new value determining unit, configured to, if a value corresponding to a first preset bit is greater than a value corresponding to a second preset bit, subtract a value corresponding to the first bit width of the stored variable information from a multiplicand value based on a numerical calculation rule, and determine a new value corresponding to the first bit width;

In one possible implementation manner of the embodiment of the present application, the multiplication resource conversion logic resource device 30 further includes: a second bit width new value determining unit, a third variable information determining unit, and a second variable shifting unit, wherein,

a second bit width new value determining unit, configured to, if the value corresponding to the first preset bit is smaller than the value of the second preset bit, add the value corresponding to the first bit width of the stored variable information to the multiplicand value based on a numerical calculation rule, and determine a new value corresponding to the first bit width;

The second variable shifting unit is used for discarding the third bit width and the value of the third bit width corresponding to the first intermediate storage variable information based on a shifting rule; and supplementing the bit width of the highest bit in the first bit width corresponding to the second intermediate storage variable information and the value corresponding to the bit width of the highest bit to the highest bit corresponding to the second intermediate storage variable information after the discarding process is completed.

In one possible implementation manner of the embodiment of the present application, the multiplication resource conversion logic resource device 30 further includes: a bit-width value discard module, wherein,

In one possible implementation manner of this embodiment of the present application, the operation result information determining module 303 further includes: a result information determination unit, wherein,

and the result information determining unit is used for discarding the bit width and the value of the lowest bit corresponding to the final storage variable information, converting the final storage variable information of which the bit width and the value are discarded, and determining the operation result information corresponding to the multiplication operation information.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

The embodiment of the present application also describes a multiplier from the perspective of a physical device, as shown in fig. 4, where the multiplier 40 shown in fig. 4 includes: a processor 401 and a memory 403. Processor 301 and memory 403 are coupled, such as by bus 402. Optionally, multiplier 40 may also include transceiver 304. It should be noted that, in practical applications, the transceiver 404 is not limited to one, and the structure of the multiplier 40 is not limited to the embodiment of the present application.

The processor 401 may be a CPU (Central Processing Unit ), general purpose processor, DSP (Digital Signal Processor, data signal processor), ASIC (Application Specific Integrated Circuit ), FPGA (Field Programmable Gate Array, field programmable gate array) or other programmable logic device, transistor logic device, hardware components, or any combination thereof. Which may implement or perform the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. The processor 401 may also be a combination for implementing a numerical calculation function, for example, including one or more microprocessor combinations, a combination of a DSP and a microprocessor, or the like.

Bus 402 may include a path to transfer information between the components. Bus 402 may be a PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus or EISA (Extended Industry Standard Architecture ) bus, among others. Bus 402 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in fig. 4, but not only one bus or one type of bus.

The Memory 403 may be, but is not limited to, ROM (Read Only Memory) or other type of static storage multiplier that can store static information and instructions, RAM (Random Access Memory ) or other type of dynamic storage multiplier that can store information and instructions, EEPROM (Electrically Erasable Programmable Read Only Memory ), CD-ROM (Compact Disc Read Only Memory, compact disc Read Only Memory) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk media or other magnetic storage multiplier, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a numerical computer.

The memory 403 is used for storing application program codes for executing the present application and is controlled to be executed by the processor 401. The processor 401 is arranged to execute the application code stored in the memory 303 to implement what is shown in the foregoing method embodiments.

The multiplier shown in fig. 4 is only an example and should not impose any limitation on the functionality and scope of use of the embodiments of the present application.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the flowcharts of the figures may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily being sequential, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.

The foregoing is only a partial embodiment of the present application and it should be noted that, for a person skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims

1. A method for converting logical resources by multiplication resources, comprising:

based on a preset conversion rule, converting the final stored variable information to determine operation result information corresponding to the multiplication operation information;

the multiplication information includes a multiplier value, a multiplier bit width, and a multiplicand bit width, the storage variable information further includes an initial value of the storage variable information, and the setting of the storage variable information according to the obtained multiplication information includes:

setting the storage variable information according to the bit width of the storage variable information and the initial value of the storage variable;

the setting of the bit width of the storage variable information based on the multiplier bit width and the multiplicand bit width includes:

setting a bit width of the storage variable information based on the first bit width, the second bit width, and the third bit width;

if a preset relation is satisfied between a value corresponding to a first preset bit of the bit width of the storage variable and a value corresponding to a second preset bit of the bit width of the storage variable in a preset calculation period, determining a processing mode of the storage variable information from a shift rule and/or a numerical calculation rule based on the shift rule and/or the numerical calculation rule corresponding to the preset relation, including:

If the value corresponding to the first preset bit of the bit width of the storage variable is not equal to the value corresponding to the second preset bit in the preset calculation period, carrying out shift and numerical calculation on the storage variable information based on a shift rule and a numerical calculation rule corresponding to the value corresponding to the first preset bit;

the shifting and numerical calculation of the stored variable information based on the shifting rule and the numerical calculation rule corresponding to the value corresponding to the first preset bit being not equal to the value corresponding to the second preset bit includes:

2. The method of claim 1, wherein setting the storage variable information based on the obtained multiplication information, and further comprising:

3. The method according to claim 1, wherein the preset computing period includes a plurality of preset sub-computing periods, and if a preset relationship is satisfied between a value corresponding to a first preset bit of the bit width of the storage variable and a value corresponding to a second preset bit of the bit width of the storage variable in the preset computing period, determining a processing manner of the storage variable information from the shift rule and/or the numerical computing rule based on the shift rule and/or the numerical computing rule corresponding to the preset relationship, and determining final storage variable information according to the processing manner, including:

4. The method of claim 1, wherein shifting and numerical computing the storage variable information based on a shift rule and a numerical computation rule corresponding to a value corresponding to the first preset bit being unequal to a value corresponding to the second preset bit, comprises:

5. The method of claim 4, wherein the determining the new value for the first bit width further comprises:

6. The method according to claim 1, wherein the converting the final stored variable information based on a preset conversion rule to determine operation result information corresponding to the multiplication operation information includes:

7. A multiplication resource conversion logic resource apparatus, comprising:

the operation result information determining module is used for converting the final stored variable information based on a preset conversion rule to determine operation result information corresponding to the multiplication operation information;

the multiplication information includes a multiplier value, a multiplier bit width, and a multiplicand bit width, and the storage variable information further includes: storing an initial value of variable information; the variable information setting module further includes:

a variable information setting unit configured to set the storage variable information according to a bit width of the storage variable information and an initial value of the storage variable;

the bit width setting unit is specifically configured to:

setting a bit width of the storage variable information based on the first bit width, the second bit width, and the third bit width

The multiplication resource conversion logic resource device further comprises: a first variable processing module and a second variable processing module, wherein,

The second variable processing module is used for carrying out shift and numerical calculation on the storage variable information based on a shift rule and a numerical calculation rule corresponding to a value corresponding to a second preset bit, wherein the value corresponding to a first preset bit of the bit width of the storage variable is not equal to the value corresponding to the second preset bit in a preset calculation period, and determining final storage variable information;

the second variable processing module further includes: a first bit width new value determining unit, a second variable information determining unit, and a first variable shifting unit, wherein,

8. A multiplier, the multiplier comprising:

at least one processor;

a memory;

at least one application program, wherein the at least one application program is stored in the memory and configured to be executed by the at least one processor, the at least one application program configured to: a method of performing the multiplication resource conversion logic resource of any one of claims 1 to 6.

9. A numerical computer readable medium having stored thereon a numerical computer program, characterized in that the numerical computer is caused to perform the multiplication resource conversion logical resource method according to any one of claims 1 to 6 when the numerical computer program is executed in a numerical computer.