CN115933861A - Clock frequency compensation method and system, electronic equipment and chip thereof - Google Patents
Clock frequency compensation method and system, electronic equipment and chip thereof Download PDFInfo
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- CN115933861A CN115933861A CN202211731195.8A CN202211731195A CN115933861A CN 115933861 A CN115933861 A CN 115933861A CN 202211731195 A CN202211731195 A CN 202211731195A CN 115933861 A CN115933861 A CN 115933861A
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Abstract
The invention provides a clock frequency compensation method and a system, electronic equipment and a chip thereof, wherein the clock frequency compensation method comprises the following steps: acquiring a time deviation value; calculating an error compensation value according to the time deviation value, the sampling rate of the terminal in the current mode and the dormancy duration of the terminal in the previous mode, wherein the current mode is a normal working mode, and the previous mode is a mode in which the terminal is converted into the dormancy mode; determining a clock frequency compensation value of the terminal entering a next mode according to the error compensation value and an automatic frequency control tracking value of the terminal in the current mode, wherein the next mode is a sleep mode; and compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value. The invention can reduce the complexity and power consumption of the system of the terminal.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a clock frequency compensation method and system, an electronic device, and a chip.
Background
The terminal typically enters a sleep mode for power saving. In the sleep mode, the terminal is in a low-voltage working state. And after the terminal is converted from the sleep mode to the normal working mode, the terminal can be in the working state of normal temperature and normal pressure. And the clock used by the terminal in the sleep mode is different from that used in the normal operation mode.
Typically, the terminal uses a 26MHz or 52MHz clock to synchronize and time with the base station in the normal operating mode, while the terminal maintains such synchronization and timing in the sleep mode using a 32KHz clock to save power.
However, when the terminal is switched from the sleep mode to the normal operation mode, the terminal may encounter a temporary meeting and a frequency deviation. In the existing way of compensating time and frequency deviation, only the fixed calibration relation of the fast and slow clocks in the working state of normal temperature and normal pressure is generally considered, but the error influence of the low-pressure working state generated in the sleep mode on the 32kHz clock in the chip is not considered. Therefore, the problem that the accumulated error is gradually increased along with the increase of the sleep time is caused, and further, the accumulated error of the terminal when the sleep wakes up to recover to the 26MHz clock is also increased, so that the time deviation of the whole system of the terminal is also increased, and the system is forced to need to increase frequent calibration or other means to maintain the accuracy of the system clock and the timing. In order to recover the receiver time, the wake-up time needs to be advanced, so that the time of the terminal in the sleep mode is reduced, the time synchronization complexity of the system of the terminal is increased, the working time in the normal working mode is increased, and the power consumption of the whole system of the terminal is increased.
Therefore, how to reduce the complexity of time synchronization when the terminal is switched from the sleep mode to the normal operating mode, and further reduce the complexity and power consumption of the system of the terminal becomes a problem that needs to be solved at present.
Disclosure of Invention
In order to solve the above problems, the clock frequency compensation method, the system, the electronic device, and the chip provided by the present invention determine the clock frequency compensation value of the terminal entering the next mode through the error compensation value and the automatic frequency control tracking value of the terminal in the current mode, and can compensate the clock frequency of the next mode, so that the time synchronization complexity can be reduced when the terminal is switched from the sleep mode to the normal operation mode in the next mode, and the complexity and the power consumption of the system of the terminal can be further reduced.
In a first aspect, the present invention provides a method for clock frequency compensation, comprising:
acquiring a time deviation value;
calculating an error compensation value according to the time deviation value, the sampling rate of the terminal in the current mode and the dormancy duration of the terminal in the last mode, wherein the current mode is a normal working mode, and the last mode is a mode in which the terminal is converted into the dormancy mode;
determining a clock frequency compensation value of the terminal entering a next mode according to the error compensation value and an automatic frequency control tracking value of the terminal in the current mode, wherein the next mode is a sleep mode;
and compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value.
Optionally, the step of calculating the error compensation value according to the time offset value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode includes:
calculating a scale factor through the product of the sampling rate of the terminal in the current mode and the sleep duration of the terminal in the last mode;
and calculating an error compensation value according to the reciprocal of the scale factor and the time deviation value.
Optionally, the step of obtaining the time deviation value includes:
determining a pre-synchronization strategy according to the dormancy duration of the terminal in the last mode;
and calculating a time deviation value according to a pre-synchronization strategy.
Optionally, the pre-synchronization policy includes: a cell search strategy and an observed time difference of arrival strategy;
the step of determining the pre-synchronization strategy according to the dormancy duration of the terminal in the last mode comprises the following steps:
when the sleeping time length in the last mode is greater than a time threshold value, selecting a cell search strategy as a pre-synchronization strategy;
and when the sleeping time length in the last mode is less than or equal to the time threshold, selecting a cell search strategy as an observed time difference of arrival strategy.
Optionally, the step of determining the clock frequency compensation value for the terminal to enter the next mode by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode includes:
converting the clock frequency compensation value into a first increasing and decreasing value corresponding to the clock frequency in the sleep mode;
converting the automatic frequency control tracking value into a second increment and decrement value corresponding to the clock frequency in the sleep mode;
and determining a clock frequency compensation value through the first increment and decrement values and the second increment and decrement values.
Optionally, after the step of determining the clock frequency compensation value for the terminal to enter the next mode through the error compensation value and the automatic frequency control tracking value of the terminal in the current mode, the method further includes: the error compensation value is recorded.
Optionally, the step of compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value includes:
and before the terminal enters the next mode, compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value.
In a second aspect, the present invention provides a system for clock frequency compensation, comprising:
an obtaining module configured to obtain a time offset value;
the calculation module is configured to calculate an error compensation value according to the time deviation value, the sampling rate of the terminal in the current mode and the sleep duration of the terminal in the last mode, wherein the current mode is a normal working mode, and the last mode is a mode in which the terminal is converted into the sleep mode;
the terminal comprises a determining module, a judging module and a judging module, wherein the determining module is configured to determine a clock frequency compensation value of the terminal entering a next mode through an error compensation value and an automatic frequency control tracking value of the terminal in a current mode, and the next mode is a sleep mode;
and the compensation module is configured to compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value.
Optionally, the calculation module comprises:
the first calculation submodule is configured to calculate a scale factor through the product of the sampling rate of the terminal in the current mode and the sleep duration of the terminal in the last mode;
and the second calculation submodule is configured to calculate an error compensation value through the reciprocal of the scale factor and the time deviation value.
Optionally, the obtaining module includes:
the determining submodule is configured to determine a pre-synchronization strategy according to the sleep duration of the terminal in the last mode;
a third calculation submodule configured to calculate a time offset value according to a pre-synchronization policy.
Optionally, the pre-synchronization policy includes: a cell search strategy and an observed time difference of arrival strategy;
the determining submodule is further configured to select the cell search strategy as a pre-synchronization strategy when the sleep duration in the last mode is greater than a time threshold, and select the cell search strategy as an observed arrival time difference strategy when the sleep duration in the last mode is less than or equal to the time threshold.
Optionally, the determining module includes:
a first scaling submodule configured to scale the clock frequency compensation value to a first increment or decrement value corresponding to the clock frequency in the sleep mode;
a second scaling submodule configured to scale the automatic frequency control tracking value to a second incremental or decremental value corresponding to the clock frequency in the sleep mode;
a determination submodule configured to determine a clock frequency compensation value by the first increment-decrement value and the second increment-decrement value.
Optionally, the system further comprises:
a recording module configured to record the error compensation value.
Optionally, the compensation module is further configured to compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value before the terminal enters the next mode.
In a third aspect, the present invention provides an electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the first and the second end of the pipe are connected with each other,
the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method of any one of the above.
In a fourth aspect, the present invention provides a chip, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method of any one of the above.
In a fifth aspect, the present invention provides a chip module, which includes the above chip.
In a sixth aspect, the invention provides a computer readable storage medium having stored thereon computer instructions which, when executed by a processor, implement a method as in any one of the above.
The clock frequency compensation method, the system, the electronic device and the chip provided by the embodiment of the invention determine the clock frequency compensation value of the terminal entering the next mode through the error compensation value and the automatic frequency control tracking value of the terminal in the current mode, and can compensate the clock frequency of the next mode, so that the time of frame interruption generated when the terminal is converted from the sleep mode to the normal working mode in the next mode is closer to the time which is synchronized once, the time synchronization complexity of the terminal is further reduced when the terminal is converted from the sleep mode to the normal working mode in the next mode, and the system complexity and the power consumption of the terminal are further reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the description below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic flow chart diagram of a method of clock frequency compensation according to an embodiment of the present application;
fig. 2 is a schematic block diagram of a system for clock frequency compensation according to an embodiment of the present application.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may comprise additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
It will be understood that when an element is referred to as being "fixedly attached" to another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for purposes of illustration only.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.
In a first aspect, the present embodiment provides a method for clock frequency compensation, referring to fig. 1, the method includes steps S101 to S101:
step S101: and acquiring a time deviation value.
The Time offset value (Time _ offset value) can be estimated by a modem (modem) or dynamically selected by a presynchronization (Presync) strategy.
In this embodiment, the step of obtaining the time deviation value includes: determining a pre-synchronization strategy according to the dormancy duration of the terminal in the last mode; and calculating a time deviation value according to a pre-synchronization strategy. The pre-synchronization policy includes at least one calculation policy for calculating the time offset value, and specifically, different calculation policies are used according to different application systems.
Further, the pre-synchronization policy includes: a Cell Search (CS) strategy and an observed time difference of arrival (OTDOA) strategy, but is not limited thereto.
The step of determining the pre-synchronization strategy according to the sleep duration of the terminal in the last mode comprises the following steps: when the dormancy duration in the last mode is greater than a time threshold, selecting a cell search strategy as a pre-synchronization strategy; and when the sleeping time length in the last mode is less than or equal to the time threshold, selecting a cell search strategy as an observed time difference of arrival strategy.
In the present embodiment, the time threshold is 128 seconds, but is not limited thereto; meanwhile, the embodiment does not further limit the way of specifically calculating the time deviation value through the cell search strategy or the observed arrival time difference strategy.
In an alternative embodiment, the pre-synchronization policy may also include: a Cell Search (CS) strategy, and a DMRS (Demodulation Reference Signal) strategy.
The step of determining the pre-synchronization strategy according to the sleep duration of the terminal in the last mode comprises the following steps: when the dormancy duration in the last mode is greater than a time threshold, selecting a cell search strategy as a pre-synchronization strategy; and when the sleeping time length in the last mode is less than or equal to the time threshold, selecting a cell search strategy as an observed time difference of arrival strategy.
Step S102: and calculating an error compensation value according to the time deviation value, the sampling rate of the terminal in the current mode and the dormancy duration of the terminal in the previous mode.
The current mode is a normal working mode, and the previous mode is a terminal converted into a sleep mode.
Specifically, the terminal uses a clock frequency of 26MHz in the normal operation mode, but the terminal is not limited to the clock frequency of 26MHz, and a clock frequency of 52MHz and the like may also be used in practical applications; the terminal uses a 32KHz clock frequency in the sleep mode, and a clock frequency of 32768Hz is specifically used in practical application, but the terminal is not limited to the 32KHz clock frequency.
In this embodiment, the terminal uses a 26MHz clock to synchronize and time with the base station in the normal operation mode. The terminal maintains this synchronization and timing in sleep mode using a 32KHz clock to save power. While the principle of maintaining synchronization and timing by a 32KHz clock is: the count value of the 32KHz clock is converted into a counter value for the 26MHz timing clock by a coefficient, which is specific to the implementation method and is not described in detail in this embodiment.
In an optional embodiment, the step of calculating the error compensation value according to the time offset value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode includes: calculating a scale factor according to the product of the sampling rate of the terminal in the current mode and the sleep duration of the terminal in the last mode; and calculating an error compensation value through the reciprocal of the scale factor and the time deviation value. Specifically, see formula one:
ppm = (time _ offset)/(fs sleeptime) formula one
Wherein ppm is an error compensation value, fs is a sampling rate, and sleeptime is a sleep duration causing time _ offset, that is, a sleep duration of the terminal in the last mode.
In an optional embodiment, after the step of calculating the error compensation value according to the time offset value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode, the method further includes: the error compensation value is recorded.
The error compensation value is recorded, so that the clock frequency of the next mode can be compensated subsequently, and meanwhile, the error compensation value can be applied to sleep modes in other application scene similar stages. And can facilitate the user to optimally adjust the error compensation value through the operating system according to the compensation effect of the next mode,
step S103: and determining the clock frequency compensation value of the terminal entering the next mode through the error compensation value and the automatic frequency control tracking value of the terminal in the current mode.
Wherein the next mode is a sleep mode.
In an alternative embodiment, the step of determining the clock frequency compensation value for the terminal to enter the next mode by the error compensation value and the afc tracking value of the terminal in the current mode includes: converting the clock frequency compensation value into a first increment and decrement value corresponding to the clock frequency in the sleep mode; converting the automatic frequency control tracking value into a second increment and decrement value corresponding to the clock frequency in the sleep mode; an error compensation value is determined by the first increment and decrement values and the second increment and decrement values.
Step S104: and compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value.
In an alternative embodiment, the step of compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value comprises: and before the terminal enters the next mode, compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value.
For example, the crystal in the terminal has a clock frequency of 32KHz (rate) in the sleep mode, and the rate is 0x752f8bc, and ppm with a value of-3374 is converted into an increment-decrement value of the rate, i.e., a first increment-decrement value, which is +0x19; meanwhile, the afc (automatic frequency control) tracking value which is-28 in the current normal mode is also converted into the increment and decrement value of the clock frequency of 32KHz, namely, the second increment and decrement value is-0 x3. Then, it is determined that the clock frequency actually adopted by the terminal in the next mode, that is, the clock frequency rate actually adopted by the sleep of the next stage is 0x752f8d2, uniformly at the time of entering the next mode, that is, before the 32k clock timing of the next mode is enabled. Wherein, 0x752f8d2=0x752f8bc +0x19-0x3.
The clock frequency compensation method determines the clock frequency compensation value of the terminal entering the next mode through the error compensation value and the automatic frequency control tracking value of the terminal in the current mode, and can compensate the clock frequency of the terminal before the terminal enters the next mode, namely, the 32k crystal is compensated in advance, so that the time of frame interruption generated when the terminal is switched from the sleep mode to the normal working mode in the next mode is closer to the time once synchronized, the time synchronization complexity can be further reduced when the terminal is switched from the sleep mode to the normal working mode in the next mode, the complexity and the power consumption of a system of the terminal can be further reduced, and meanwhile, the power consumption of a corresponding chip, a chip module and the system can be reduced.
In a second aspect, based on the method for clock frequency compensation in the first aspect, the present embodiment provides a system 200 for clock frequency compensation, and referring to fig. 2, the system 200 for clock frequency compensation includes:
an obtaining module 201 configured to obtain a time deviation value;
the calculating module 202 is configured to calculate an error compensation value according to the time offset value, a sampling rate of the terminal in a current mode and a sleep duration of the terminal in a previous mode, wherein the current mode is a normal working mode, and the previous mode is a mode in which the terminal is switched to the sleep mode;
a determining module 203 configured to determine a clock frequency compensation value of the terminal entering a next mode through the error compensation value and an automatic frequency control tracking value of the terminal in a current mode, wherein the next mode is a sleep mode;
and the compensation module 204 is configured to compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value.
In an alternative embodiment, the calculation module 202 includes:
the first calculation submodule is configured to calculate a scale factor through the product of the sampling rate of the terminal in the current mode and the sleep duration of the terminal in the last mode;
and the second calculation submodule is configured to calculate an error compensation value through the reciprocal of the scale factor and the time deviation value.
In an alternative embodiment, the obtaining module 201 includes:
the determining submodule is configured to determine a pre-synchronization strategy according to the dormancy duration of the terminal in the last mode;
a third calculation submodule configured to calculate a time offset value according to a pre-synchronization policy.
In an alternative embodiment, the pre-synchronization policy comprises: a cell search strategy and an observed time difference of arrival strategy;
the determining submodule is further configured to select the cell search strategy as a pre-synchronization strategy when the sleep duration in the last mode is greater than a time threshold, and select the cell search strategy as an observed time difference of arrival strategy when the sleep duration in the last mode is less than or equal to the time threshold.
In an alternative embodiment, the determining module 203 comprises:
a first scaling submodule configured to scale the clock frequency compensation value to a first increase-decrease value corresponding to the clock frequency in the sleep mode;
a second scaling submodule configured to scale the automatic frequency control tracking value to a second incremental or decremental value corresponding to the clock frequency in the sleep mode;
a determination submodule configured to determine a clock frequency compensation value by the first and second increase and decrease values.
In an alternative embodiment, the system 200 for clock frequency compensation further comprises:
a recording module configured to record the error compensation value.
In an alternative embodiment, the compensation module 204 is further configured to compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value before the terminal enters the next mode.
In a third aspect, the present embodiment provides an electronic device, including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the first and the second end of the pipe are connected with each other,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of the above.
In a fourth aspect, the present embodiment provides a chip, including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of the above.
In a fifth aspect, the present embodiment provides a chip module, which includes the chip described above.
In a sixth aspect, the present embodiments provide a computer readable storage medium storing computer instructions that, when executed by a processor, implement a method as in any one of the above.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (18)
1. A method of clock frequency compensation, comprising:
acquiring a time deviation value;
calculating an error compensation value according to the time deviation value, the sampling rate of the terminal in the current mode and the dormancy duration of the terminal in the last mode, wherein the current mode is a normal working mode, and the last mode is a mode in which the terminal is converted into the dormancy mode;
determining a clock frequency compensation value of the terminal entering a next mode according to the error compensation value and an automatic frequency control tracking value of the terminal in the current mode, wherein the next mode is a sleep mode;
and compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value.
2. The method of claim 1, wherein the step of calculating the error compensation value according to the time offset value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode comprises:
calculating a scale factor through the product of the sampling rate of the terminal in the current mode and the sleep duration of the terminal in the last mode;
and calculating the error compensation value according to the reciprocal of the scale factor and the time deviation value.
3. The method of claim 1, wherein the step of obtaining the time offset value comprises:
determining a pre-synchronization strategy according to the dormancy duration of the terminal in the last mode;
and calculating the time deviation value according to the pre-synchronization strategy.
4. The method of claim 3, wherein the pre-synchronization policy comprises: a cell search strategy and an observed time difference of arrival strategy;
the step of determining the pre-synchronization strategy according to the sleep duration of the terminal in the last mode comprises the following steps:
when the sleeping time length in the last mode is larger than a time threshold, selecting the cell search strategy as the pre-synchronization strategy;
and when the sleeping time length in the last mode is less than or equal to the time threshold, selecting the cell search strategy as the observed time difference of arrival strategy.
5. The method of claim 1, wherein the step of determining the clock frequency compensation value for the terminal to enter the next mode through the error compensation value and the afc tracking value of the terminal in the current mode comprises:
converting the clock frequency compensation value into a first increment and decrement value corresponding to the clock frequency in the sleep mode;
converting the automatic frequency control tracking value to a second incremental or decremental value corresponding to the clock frequency in the sleep mode;
determining the clock frequency compensation value through the first increasing and decreasing value and the second increasing and decreasing value.
6. The method according to any one of claims 1 to 5, wherein after the step of determining the clock frequency compensation value for the terminal to enter the next mode through the error compensation value and the automatic frequency control tracking value of the terminal in the current mode, the method further comprises: and recording the error compensation value.
7. The method according to any one of claims 1 to 5, wherein the step of compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value comprises:
and before the terminal enters the next mode, compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value.
8. A system for clock frequency compensation, comprising:
an obtaining module configured to obtain a time offset value;
the calculation module is configured to calculate an error compensation value according to the time deviation value, the sampling rate of the terminal in the current mode and the sleep duration of the terminal in the last mode, wherein the current mode is a normal working mode, and the last mode is a mode in which the terminal is converted into the sleep mode;
the determining module is configured to determine a clock frequency compensation value of the terminal entering a next mode through the error compensation value and an automatic frequency control tracking value of the terminal in a current mode, wherein the next mode is a sleep mode;
a compensation module configured to compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value.
9. The system of claim 8, wherein the computing module comprises:
the first calculation submodule is configured to calculate a scale factor through the product of the sampling rate of the terminal in the current mode and the sleep duration of the terminal in the last mode;
a second calculation submodule configured to calculate the error compensation value from the inverse of the scaling factor and the time offset value.
10. The system of claim 8, wherein the acquisition module comprises:
the determining submodule is configured to determine a pre-synchronization strategy according to the sleep duration of the terminal in the last mode;
a third calculation submodule configured to calculate the time offset value according to the pre-synchronization policy.
11. The system of claim 10, wherein the pre-synchronization policy comprises: a cell search strategy and an observed time difference of arrival strategy;
the determining sub-module is further configured to select the cell search strategy as the pre-synchronization strategy when the sleep duration in the previous mode is greater than a time threshold, and select the cell search strategy as the observed time difference of arrival strategy when the sleep duration in the previous mode is less than or equal to the time threshold.
12. The system of claim 8, wherein the determination module comprises:
a first scaling submodule configured to scale the clock frequency compensation value to a first increase-decrease value corresponding to a clock frequency in the sleep mode;
a second scaling submodule configured to scale the automatic frequency control tracking value to a second incremental or decremental value corresponding to the clock frequency in the sleep mode;
a determination submodule configured to determine the clock frequency compensation value from the first and second increase and decrease values.
13. The system of any one of claims 8 to 12, further comprising:
a recording module configured to record the error compensation value.
14. The system according to any one of claims 8 to 12, wherein the compensation module is further configured to compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value before the terminal enters the next mode.
15. An electronic device, characterized in that the electronic device comprises:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 7.
16. A chip, wherein the chip comprises:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the first and the second end of the pipe are connected with each other,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 7.
17. A chip module, characterized in that it comprises a chip according to claim 16.
18. A computer-readable storage medium, characterized in that it stores computer instructions which, when executed by a processor, implement the method of any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211731195.8A CN115933861A (en) | 2022-12-30 | 2022-12-30 | Clock frequency compensation method and system, electronic equipment and chip thereof |
Applications Claiming Priority (1)
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|---|---|---|---|
| CN202211731195.8A CN115933861A (en) | 2022-12-30 | 2022-12-30 | Clock frequency compensation method and system, electronic equipment and chip thereof |
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