CN115883689A - Code block transmission method, device and storage medium - Google Patents
Code block transmission method, device and storage medium Download PDFInfo
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- CN115883689A CN115883689A CN202111113008.5A CN202111113008A CN115883689A CN 115883689 A CN115883689 A CN 115883689A CN 202111113008 A CN202111113008 A CN 202111113008A CN 115883689 A CN115883689 A CN 115883689A
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Abstract
The application discloses a code block transmission method, a device and a storage medium, wherein the code block transmission method comprises the following steps: determining a counting threshold value of a counter for counting the clock pulse according to the period of the clock pulse, the bandwidth of the client and the code block interval of the transmission code block of the client with different bandwidths, wherein the counters corresponding to the clients with different bandwidths are different; when the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of a count mark corresponding to the nth counter in a register as a preset value, wherein the value of N is less than or equal to N, and N is the number of clients; scanning the register; and when the counting flag bit corresponding to the mth counter in the register is scanned to be a preset value, receiving a code block sent by a client corresponding to the mth counter or sending the code block to the client corresponding to the mth counter, wherein the value of m is less than or equal to N. The method and the device can give consideration to chip resource saving and feasibility and meet the time interval requirement required by the code block transmission standard.
Description
Technical Field
The present application relates to the field of network communication technologies, and in particular, to a code block transmission method, apparatus, and storage medium.
Background
The flexible Ethernet (FlexE) technology is developed to meet the requirements of high-speed transmission, flexible bandwidth configuration, and the like based on the Ethernet technology.
In the flexible ethernet, according to the relevant standard requirements of OAM (Operation, administration and Maintenance), the code block intervals are different for different types of OAM code blocks according to the relevant standard requirements of the flexible ethernet OAM. For example, the code block interval requirement for transmitting the BAS code block is to transmit and receive (K is 1024) at intervals of 16K frames, or 32K, 64K, 128K, 256K,512k frames, under the bandwidth of the FlexE Client (K is 1024), and other types of OAM frames are also transmitted and received based on this interval unit, or in time units of 1 second.
Due to the flexibility of 5G granularity, which can support bandwidth, the bandwidth of each FlexE Client may be different, even if the code blocks are transmitted at the same code block interval, the time interval for the FlexE clients of different bandwidths to transmit the code blocks is different. If a plurality of timers are used to respectively realize the time interval required by the clients with different bandwidths to reach the code block transmission standard, waste of chip resources is caused, and if one timer is used to realize the time interval required by the clients with different bandwidths to reach the code block transmission standard, the time interval can be difficult to realize.
Disclosure of Invention
The embodiment of the application provides a code block transmission method, a code block transmission device and a storage medium.
The technical scheme of the application is realized as follows:
in a first aspect, a method for code block transmission is provided, and the method includes:
determining a counting threshold value of a counter for counting the clock pulses according to the period of the clock pulses, the bandwidth of a client and the code block interval of the client transmission code blocks with different bandwidths; the counters corresponding to the clients with different bandwidths are different;
when the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of a count mark corresponding to the nth counter in a register as a preset value; the value of N is less than or equal to N, wherein N is the number of the clients;
scanning the register;
and when the counting flag bit corresponding to the mth counter in the register is scanned to be the preset value, receiving a code block sent by a client corresponding to the mth counter or sending the code block to the client corresponding to the mth counter, wherein the value of m is less than or equal to N.
In the above technical solution, the scanning the register includes:
scanning the register for a timing period of a timer, wherein the timing period of the timer is less than or equal to the period of the clock pulse.
In the above technical solution, the determining a count threshold for a counter to count the clock pulse according to a period of the clock pulse, a bandwidth of a client, and a code block interval of a code block transmitted by the client with different bandwidths includes:
determining a time interval for transmitting the code block according to the bandwidth of the nth client, the code block interval and the bit number contained in each frame in the code block interval;
determining a quotient between the time interval and a period of the clock pulse;
determining an integer portion of the quotient as a count threshold of the nth counter.
In the above technical solution, the method further includes:
when the quotient has a decimal part, recording the decimal part of the quotient;
and when the product of the fractional part and the s is greater than or equal to 1, determining that the maximum value of the current counting of the nth counter is the count threshold plus 1, wherein s is the counting turn of the current counting of the nth counter from 0 to the count threshold continuously.
In the above technical solution, the code block includes: the code block spacing of the second type code block is P times of the code block spacing of the first type code block, and P is a positive integer greater than or equal to 2;
the count threshold of the nth counter is as follows: determined according to a code block interval of the first type of code block;
when the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of a count mark corresponding to the nth counter in a register as a preset value, including:
every time the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of a count mark corresponding to the first code block of the nth counter in the register as the preset value; and/or the presence of a gas in the atmosphere,
and when the count value of the nth counter reaches the count threshold value of the nth counter for P times continuously, setting the position of a count mark corresponding to the second code block of the nth counter in the register as the preset value.
In the above technical solution, the code blocks further include a third type code block, where an nth time interval for the client to transmit the third type code block is q times of a time interval for the nth client to transmit the first type code block, an interval unit of the time interval is different from an interval unit of the code block interval, and q is a positive integer greater than or equal to 2;
when the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of the count mark corresponding to the nth counter in the register to a preset value further comprises:
and when the count value of the nth counter reaches the count threshold value of the nth counter for q times continuously, setting the position of a count mark corresponding to the third code block of the nth counter in the register as the preset value.
In the above technical solution, the method further includes:
if the code block sent by the client corresponding to the mth counter is not received within the preset continuous times, generating an overtime alarm; wherein the preset continuous times are as follows: the number of times that the count value of the mth counter reaches the count threshold value of the mth counter continuously.
In a second aspect, an apparatus for code block transmission is provided, the apparatus comprising:
the determining module is used for determining a counting threshold value of a counter for counting the clock pulses according to the period of the clock pulses, the bandwidth of a client and the code block interval of the client transmission code blocks with different bandwidths; the counters corresponding to the clients with different bandwidths are different;
the setting module is used for setting the counting mark position corresponding to the nth counter in the register as a preset value when the counting value of the nth counter reaches the counting threshold value of the nth counter; the value of N is less than or equal to N, and N is the number of the clients;
the scanning module is used for scanning the register;
and the transmission module is used for receiving a code block sent by a client corresponding to the mth counter or sending the code block to the client corresponding to the mth counter when the counting flag bit corresponding to the mth counter in the register is scanned to be the preset value, wherein the value of m is less than or equal to N.
In a third aspect, an electronic apparatus is provided, comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the code block transmission method of any of the first aspects.
In a fourth aspect, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is arranged to, when executed, perform the code block transmission method of any of the first aspects.
In the technical scheme provided by the application, the counting threshold value of the counter for counting the clock pulse is determined according to the period of the clock pulse, the bandwidth of the client and the code block interval of the transmission code block of the client with different bandwidths, and the counters corresponding to the clients with different bandwidths are different, so that compared with the time interval required by the client with different bandwidths to reach the code block transmission standard by using a plurality of timers, the counters corresponding to the clients with different bandwidths share the same clock pulse for counting, namely the pulse counting is realized by using only one timer for the clients with different bandwidths, so that the chip resource can be greatly saved; in addition, the same main frequency/frequency division pulse signal is not required to be used as the minimum common divisor of different time intervals, so that the method is not limited by the size of the pulse signal, and only the counting threshold value for counting the clock pulse by the counter degrees corresponding to the clients with different bandwidths is determined, so that the method is more feasible; in addition, when the count value of the nth counter reaches the count threshold value of the nth counter, the position of the count flag corresponding to the nth counter in the register is set as a preset value, the register is scanned, and when the count flag corresponding to the mth counter in the register is scanned as the preset value, the code block sent by the client corresponding to the mth counter is received or the code block is sent to the client corresponding to the mth counter, wherein the value of m is less than or equal to N, so that the time precision of code block transmission can be ensured while the chip resource saving and feasibility are fully considered, and the time interval requirement required by the code block transmission standard is met.
Drawings
FIG. 1a is a schematic flow diagram of a design scheme using multiple timers;
FIG. 1b is a schematic flow chart of a design scheme using one timer;
fig. 2 is a schematic flowchart of a code block transmission method according to an embodiment of the present application;
fig. 3 is another schematic flow chart of a code block transmission method according to an embodiment of the present application;
fig. 4 is a schematic flowchart of a code block transmission method according to an embodiment of the present application;
fig. 5a is a schematic diagram of a framework of a two-stage timer in a code block transmission method according to an embodiment of the present application;
FIG. 5b is a pseudo code logic of a method for using a timer counter register according to an embodiment of the present application;
fig. 5c is a flowchart of a code block transmission method based on a two-stage timer according to an embodiment of the present application;
fig. 5d is a flowchart of a BAS timeout handling mechanism triggered by a timer according to an embodiment of the present application;
fig. 5e is a flowchart of a timeout count update handling mechanism in the receiving direction according to the embodiment of the present application;
fig. 6 is a schematic structural diagram of a code block transmission apparatus according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application. In the present application, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict. The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
It is to be understood that, unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
Furthermore, in the description of the present application, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present application, the meaning of "a plurality" is two or more unless otherwise specified.
The time interval is different for different types of OAM code blocks, as required by the relevant standards for flexible ethernet OAM. For a BAS code block (Basic code block), the function of the code block is to regularly monitor the Basic code block of a Flexe Client (flexible Ethernet Client), the code block interval requirement for transmitting the code block is 16K/32K/64K/128K/256K/512K block (data frame), and the data frame adopts 66bit/64bit coding, namely the actual effective data of each frame is 8Byte. For APS code blocks (code blocks for protection switching), when a link failure is detected, three APS code blocks need to be transmitted consecutively at the same code block interval as the BAS code blocks. For other code blocks, such as CV code blocks (connectivity verification code blocks), 1DM code blocks (one-way delay code blocks), 2DMM code blocks (two-way delay measurement code blocks), 2DMR (two-way delay response code blocks), CS code blocks (customer signal indication code blocks), all are in time units of 1 second, 10 seconds, or 1 minute.
Due to the flexibility of the FlexE Client bandwidth of the flexible ethernet, the flexible ethernet defines that the FlexE Client bandwidth thereof takes 5G as the minimum unit, and can be combined according to the chip supported capacity, such as 400G or 800G. For example, a bandwidth combination of 25G, 50G, 105G, 195G, and the like in 5G may be supported, so that the code block interval of the transmission code block of the FlexE Client with different bandwidths is the same, and the time interval of the transmission code block is different, for example, the code block interval of the transmission BAS code block is 16k frames, and the time interval of the transmission BAS code block of the FlexE Client with 25G bandwidth is different from that of the transmission BAS code block of the FlexE Client with 50G bandwidth.
The general timer implementation method comprises the following steps: frequency division configuration is carried out according to the main frequency of the chip, the counter is updated by taking the main frequency as a minimum unit, and a certain operation flow is triggered by configuring a threshold value reached by the counter, so that the timing function is realized. For example, assuming that the main frequency of the chip is 500M, if a 1ms timer is configured, a counter needs to be designed, the counter performs an operation of adding 1 every time the main frequency is refreshed, and when the counter reaches 500M/1000/1, i.e. 500000, it indicates that the time reaches 1ms, and a certain operation is executed at this time.
In the face of the flexibility of 5G granularity capable of supporting bandwidth and OAM related standard requirements, two schemes are generally available from the design point of view for realizing code block transmission of Flexe clients with different bandwidths.
The first scheme comprises the following steps: as shown in fig. 1a, fig. 1a is a schematic flow chart of a design scheme using multiple timers, and since bandwidths of each FlexE Client may be different, threshold configuration of a counter has no certain calculation relationship, a timer needs to be designed for each FlexE Client, and timer time can be set according to different bandwidths. Thus, although the problem of the timer is solved, a large number of timers are needed to be used, and chip resources are greatly wasted.
Scheme II: as shown in fig. 1b, fig. 1b is a flow chart of a design scheme using a timer, from which all time units with different bandwidths are generated, and at the same time, functions of different time intervals are achieved by configuring accumulator registers of different timer counters and different thresholds. However, due to the diversity of the FlexE Client bandwidths, if a certain FlexE Client needs to support 55G bandwidth, the time interval of 16K frames is calculated as: 64bit 16K/55G =19065.018ns, and another Flexe Client needs to support 105G, the time interval of 16K frames is calculated as 64bit 16K/105G =9986.438ns, and the same main frequency/frequency division pulse signal is used, namely the minimum common divisor of the two time intervals needs to be found, so that the method can be used for configuring different timer counters to achieve the purpose of using one timer. Moreover, with the bandwidth granularity of 5G as a unit, the minimum common divisor of the time intervals of 16K frames considering all bandwidths may need to reach the level of 1ns or be less than 1ns, and even if the chip main frequency can meet the pulse granularity of 1ns, the chip cannot complete the operation that needs to be performed after the timer reaches the threshold value within 1ns, such as sending a FlexE OAM code block. Therefore, this solution is not feasible.
In view of this, the embodiments of the present application provide a code block transmission method, which can guarantee the time precision of code block transmission and meet the time interval requirement required by the code block transmission standard while fully considering chip resource saving and feasibility. The method can be executed by a code block transmission device, the device can be implemented in a software and/or hardware manner, and can be deployed in a switch chip supporting FlexE OAM, the chip can be an Application Specific Integrated Circuit (ASIC) chip, or a Field Programmable Gate Array (FPGA) chip, or NP, and the like, and can be adjusted accordingly according to actual conditions.
Referring to fig. 2, an embodiment of the present application provides a code block transmission method, which may include:
s11, determining a counting threshold value of a counter for counting clock pulses according to the period of the clock pulses, the bandwidth of a client and the code block interval of code block transmission of the client with different bandwidths; and the counters corresponding to the clients with different bandwidths are different.
The clock pulse may be a time pulse signal divided by the main frequency generated by the switching chip, and the count of the started counter is increased by one every time a clock pulse is generated. Here, the period of the clock pulse may be set according to actual needs, and preferably, the period of the clock pulse is set to 32ns. Here, the started counter may be a counter corresponding to a client that needs to perform code block transmission between current devices.
The Client can be a flexible Ethernet Client Flexe Client, and sends or receives OAM code blocks according to code block intervals required by an OAM standard under the bandwidth to which the Client belongs, wherein the number of the clients is multiple, and the bandwidths of the multiple clients can be partially the same or different.
Where the code block interval may be a specified number of data frames as required by the code block transmission standard. For example, when the code block interval for transmitting the code block is 16k data frames, that is, one code block is transmitted every 16k data frames, wherein the data frames are encoded by 66 bits/64 bits, and the actual valid data of each frame is 8 bytes.
The counter for counting clock pulses is a count register, and the counter is configured to record a count threshold of the counter for the clock pulses as a configuration register, and more specifically, a first count field of the count register is configured to record a current count value for the clock pulses, and a first configuration field of the configuration register is configured to record the count threshold for the clock pulses.
It can be understood that, under the same code block interval, the counter corresponding to the different bandwidth clients has different count thresholds for counting the clock pulses.
S12, when the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of a count mark corresponding to the nth counter in the register as a preset value; and the value of N is less than or equal to N, and N is the number of the clients.
When the count value of the nth counter corresponding to the nth client reaches the count threshold value of the nth counter, the count value of the nth counter is cleared, and the position of a count mark corresponding to the nth counter in the register is triggered to be a preset value. The counter adopts different values to indicate whether the count value of the counter reaches a count threshold value or not at the corresponding count flag bit in the register.
In particular implementations, the register may use a binary bit in the bitmap data structure as a count flag bit corresponding to the counter. Here, the bitmap data structure refers to a data structure that uses a bitmap (bitmap) type field, where each bit (bit) in the field represents a counter (or a client corresponding to the counter), and each bit uses 0 to indicate that the count value of the counter does not reach a count threshold, and uses 1 to indicate that the count value of the counter reaches the count threshold; alternatively, 0 indicates that the count value of the counter reaches the count threshold value, and 1 indicates that the count value of the counter does not reach the count threshold value.
When the counting value of one counter reaches the counting threshold value of the counter, the bit representing the counter is set to be a preset value indicating that the counting threshold value is reached in the register.
And S13, scanning the register.
In one embodiment, the scan register may be cycled through repeatedly;
in another embodiment, specifically, the counting flag bits corresponding to different counters in the register may be scanned according to a timing period of the timer, and each time a counting flag bit is scanned, it is determined whether a value of the counting flag bit is a preset value.
And S14, when the counting flag bit corresponding to the mth counter in the register is scanned to be a preset value, receiving a code block sent by a client corresponding to the mth counter or sending the code block to the client corresponding to the mth counter, wherein the value of m is less than or equal to N.
In one example, the code block transmission apparatus is located in a switch chip as a receiving end, and when the count flag bit corresponding to the m-th counter in the register is scanned to be a preset value, the code block transmission apparatus indicates that: the time interval of receiving the code block sent by the client corresponding to the mth counter is reached, and at the moment, the code block transmission device receives the code block sent by the client corresponding to the mth counter;
in another example, the code block transmission apparatus is located in a switch chip as a sending end, and when the count flag bit corresponding to the m-th counter in the register is scanned to be a preset value, the code block transmission apparatus indicates that: when the time interval for transmitting the code block to the client corresponding to the mth counter is reached, the code block transmission device transmits the code block to the client corresponding to the mth counter.
In the embodiment of the application, when the code block is transmitted, because the counting threshold value of the counter for counting the clock pulse is determined according to the period of the clock pulse, the bandwidth of the client and the code block interval of the code block transmitted by the client with different bandwidths, the counters corresponding to the clients with different bandwidths are different, so that compared with the time interval required by the client with different bandwidths to reach the code block transmission standard by using a plurality of timers, the counters corresponding to the clients with different bandwidths share the same clock pulse for counting, namely the pulse counting is realized by using only one timer for the clients with different bandwidths, and the chip resource can be greatly saved; in addition, the same main frequency/frequency division pulse signal is not required to be used as the minimum common divisor of different time intervals, so that the size of the pulse signal is not limited, and only the counting threshold value for counting the clock pulse by the counter degree corresponding to the client sides with different bandwidths is determined, so that the feasibility is realized; in addition, when the count value of the nth counter reaches the count threshold value of the nth counter, the position of the count flag corresponding to the nth counter in the register is set as a preset value, the register is scanned, and when the count flag corresponding to the mth counter in the register is scanned as the preset value, the code block sent by the client corresponding to the mth counter is received or the code block is sent to the client corresponding to the mth counter, wherein the value of m is less than or equal to N, so that the time precision of code block transmission can be ensured while the chip resource saving and feasibility are fully considered, and the time interval requirement required by the code block transmission standard is met.
In an embodiment, as shown in fig. 3, in the step S11, determining a count threshold of the counter for counting the clock pulses according to the period of the clock pulses, the bandwidth of the client, and the code block interval of the transmission code blocks of the clients with different bandwidths may include:
and S111, determining the time interval for transmitting the code block according to the bandwidth of the nth client, the code block interval and the bit number contained in each frame in the code block interval.
Wherein the bandwidth of the client is inversely related to the time interval of the client transmitting the code block.
Specifically, the product of the code block interval and the number of bits contained by the code block is determined, and the quotient between the product and the bandwidth of the nth client is taken as the time interval for the nth client to transmit the code block.
For example, taking the code block as a BAS code block as an example, assuming that the bandwidth of the nth client is 55G, the code block interval for transmitting the BAS code block is 16K frames, and each frame includes 64 bits, the time interval for the nth client to transmit the code block is calculated as: 64bit 16k/55g=19065.018ns.
And S112, determining the quotient between the time interval and the period of the clock pulse.
Here, the quotient between the time interval and the period of the clock pulse may be understood as the number of pulses of the clock pulse within the time interval, which may be a non-integer value.
And S113, determining the integer part of the quotient as the counting threshold value of the nth counter.
Specifically, the configuration register of the nth counter holds a first configuration field and a second configuration field. The first configuration field is used for configuring the counting threshold of the nth counter, namely the integer part of the quotient between the time interval of the nth client transmitting the code block and the period of the clock pulse; the second configuration field is used to configure the configuration value of the fractional count portion of the nth counter.
In one embodiment, as shown in fig. 4, based on fig. 3, the method may further include:
and S114, recording the decimal part of the quotient when the decimal part of the quotient exists.
Specifically, for a time interval in which the nth client transmits a code block, the fractional part of the quotient between the time interval and the period of the clock pulse may be configured into a second configuration field within the configuration register as a configuration value of the fractional count portion of the nth counter.
Exemplarily, assuming that the bandwidth of the nth client is 55G, the codeblocks are transmitted at a codeblock interval of 16K data frames, the transmission time interval is 19065.018ns, and for a time pulse with a pulse period of 32ns, the required number of pulses is: 19065.018/32=595.782, to achieve a more precise time interval, in addition to the integer part 595 of the number of pulses as a configuration value for the count threshold of the nth counter in the first configuration field in the configuration register, it is also possible to take the fractional part 0.782 of the number of pulses as a configuration value for the fractional count part of the nth counter in the second configuration field in the configuration register.
And S115, when the product of the fractional part and S is greater than or equal to 1, determining that the maximum value of the current counting of the nth counter is the counting threshold value plus 1, wherein S is the counting turn of the current counting of the nth counter from 0 to the counting threshold value continuously.
Specifically, when the product of the fractional part and s is greater than or equal to 1, the value of the product is recorded into the second count field of the count register in the nth counter, and the first count field of the count register in the nth counter is used for recording the current count value of the nth counter to the clock pulse.
In this embodiment, the current counting round of the nth counter continuously counting from 0 to the counting threshold is multiplied by the fractional part of the number of pulses of the clock pulse in the time interval of the nth client transmitting the code block, and when the multiplication result is greater than or equal to 1, the maximum value of the current counting of the nth counter is determined as the counting threshold plus 1, so that not only can the counting processing of the fractional part be approximately averaged in a plurality of pulse periods, but also the time precision of code block transmission is further improved.
In one embodiment, a code block includes: the code block spacing of the second code block is P times of the code block spacing of the first code block, and P is a positive integer greater than or equal to 2; the count threshold of the nth counter is: determined according to the code block spacing of the code blocks of the first type.
Here, for convenience of description, the code block interval of the first-type code block may be referred to as a first code block interval, and the code block interval of the second-type code block may be referred to as a second code block interval. Here, the first code block interval may be a 16K data frame, and the second code block interval may be a 32K data frame, a 64K data frame, a 128K data frame, a 256K data frame, or a 512K data frame, but the embodiment of the present application is not limited thereto.
The first code block interval may be a minimum code block interval supported by the corresponding client, and the second code block interval is P times the minimum code block interval.
Wherein, the determining the counting threshold of the nth counter according to the code block interval of the first code block comprises:
and determining a counting threshold value of the nth counter for counting the clock pulses according to the period of the clock pulses, the bandwidth of the nth client and the code block interval of the first code block.
Specifically, the step implementation process may refer to step S111 to step S113 in the above embodiment, and details are not repeated here.
In the step S12, when the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of the count flag corresponding to the nth counter in the register as the preset value may include at least one of the steps S121 and S122:
and S121, setting the counting mark position corresponding to the first code block of the nth counter in the register as a preset value every time the counting value of the nth counter reaches the counting threshold value of the nth counter.
In this embodiment, since the count threshold of the nth counter is determined according to the code block interval of the first type of code block, when the count value of the nth counter reaches the count threshold of the nth counter, it indicates that the nth client corresponding to the nth counter reaches the code block interval for transmitting the first type of code block, and the count flag position corresponding to the first type of code block of the nth counter in the register is a preset value, in this way, in the process of scanning the register, the count flag position corresponding to the first type of code block of the nth counter in the register is scanned as the preset value, so as to receive the first type of code block sent by the nth client or send the first type of code block to the nth client, thereby implementing that clients with different bandwidths can transmit the first type of code block according to the code block transmission standard, and ensuring the time precision of code block transmission.
And S122, when the count value of the nth counter reaches the count threshold value of the nth counter for P times continuously, setting the position of a count mark corresponding to the second code block of the nth counter in the register as a preset value.
In this embodiment, because the code block interval of the second code block is P times of the code block interval of the first code block, and meanwhile, because the count threshold of the nth counter is determined according to the code block interval of the first code block, when the count value of the nth counter reaches the count threshold of the nth counter for P consecutive times, it indicates that the nth client corresponding to the nth counter reaches the code block interval for transmitting the second code block, and the count flag position corresponding to the second code block of the nth counter in the register is a preset value, in this way, in the process of scanning the register, the count flag position corresponding to the second code block of the nth counter in the register is scanned as a preset value to receive the second code block sent by the nth client or send the second code block to the nth client, thereby implementing that clients with different bandwidths can transmit the second code block according to the transmission standard, and ensuring the time precision of code block transmission. In one embodiment, the code blocks further include a third type of code block, wherein the nth client transmits the third type of code block at a time interval q times the time interval at which the nth client transmits the first type of code block, the interval unit of the time interval being different from the interval unit of the code block interval, and q is a positive integer greater than or equal to 2.
Here, the time interval may be in units of intervals of time of the order of seconds, and the code block interval is in units of intervals of the number of data frames. As an example, the third type code block may be CV code blocks transmitted in time of the order of seconds or minutes, and the first type code block may be BAS code blocks, APS code blocks, or the like transmitted at intervals of 16k data frames, but the embodiment of the present application is not limited thereto.
The time interval for the nth client to transmit the first code block may be determined as follows:
and determining the time interval of the nth client for transmitting the first code block according to the bandwidth of the nth client, the code block interval of the first code block transmitted by the nth client and the number of bits contained in each frame of code block in the code block interval.
In the step S12, when the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of the count flag corresponding to the nth counter in the register as the preset value, the method may further include:
and S123, when the count value of the nth counter reaches the count threshold value of the nth counter for q times continuously, setting the position of a count mark corresponding to the third code block of the nth counter in the register as a preset value.
In this embodiment, since the time interval for the nth client to transmit the third code block is q times as long as the time interval for the nth client to transmit the first code block, when the count value of the nth counter reaches the count threshold of the nth counter for q consecutive times, it indicates that the nth client has reached the time interval for transmitting the third code block, and the count flag position corresponding to the third code block of the nth counter in the register is a preset value, so that, in the process of scanning the register, the count flag position corresponding to the third code block of the nth counter in the register is scanned as the preset value to receive the third code block sent by the nth client or send the third code block to the nth client, thereby realizing that clients with different bandwidths can transmit the third code block according to the code block transmission standard, and ensuring the time precision of code block transmission.
In an embodiment, in the step S13, the scanning the register may include:
the register is scanned for a timing period of a timer, wherein the timing period of the timer is less than or equal to a period of the clock pulse.
The timer may be a timer to which the register belongs, i.e., a second-stage timer.
The timing period of the timer is an adjustable value, which can be adjusted within a chip design allowable range, and the register is scanned with a timing period as small as possible, it can be understood that the smaller the timing period of the timer is, the more the code block transmission time accuracy can be improved, and preferably, the timing period of the timer is set to 8ns.
In one embodiment, the method may further comprise:
if the code blocks sent by the client corresponding to the mth counter are not received within the preset continuous times, generating an overtime alarm; wherein, the preset continuous times are as follows: the number of times the count value of the mth counter reaches the count threshold value of the mth counter in succession.
The preset continuous times can be set according to practical application, for example, set to 3, that is: and continuously receiving the code block sent by the client corresponding to the mth counter for 3 times, and generating an overtime alarm.
It should be noted that when the number of consecutive times of code blocks sent by the client corresponding to the mth counter is not received is lower than the preset number of consecutive times, no timeout alarm is generated.
Next, a code block transmission method provided in the embodiment of the present application is described with reference to fig. 5a to 5 e.
Taking a FlexE Client supporting 800G in total as an example, when the bandwidth 5G is the minimum bandwidth granularity, 800/5 (G) =160 FlexE clients at most, the period of the clock pulse signal divided by the chip main frequency is set to be 32ns, and a 16K data frame is used as the code block interval of each FlexE Client transmission code block.
As shown in fig. 5a, in the first-stage timer, a counter is respectively set for each FlexE Client, each counter includes a count register and a configuration register, the count register is DsFlexEOamTxScanCounter, and the count register holds two fields: a counter for holding an integer portion of the current timer count, and a countfrac for holding a fractional portion of the current timer count. The configuration register is DsFlexeoAMTxScanCfg, which holds two fields: the method comprises the steps of calculating the counting threshold value of each pulse, and calculating FracCfg, wherein the calculating threshold value is used for configuring the counting threshold value of the corresponding FlexE Client 16K data frame, and the calculating FracCfg is used for configuring the configuration value of the decimal part of each pulse updating.
In the second stage timer, the trigger register is set to FlexeoAmTxScanBitmap, which holds a field, updateEnBitmap. This field may be of the bitmap type, i.e., each bit therein represents a Flexe Client, and when 1, indicates that the 16K frame interval of the current Flexe Client has been reached.
FIG. 5b is a pseudo code logic for a method of using a timer counter register. Considering that 32ns time pulse is a fixed pulse, and generally cannot be divided into integer bandwidths, taking 55G bandwidth as an example, the time interval of transmission of a code block by using a 16K data frame as a code block interval is 19065.018ns according to the calculation in the foregoing embodiment, 19065.018/32=595.782 is needed for 32ns time pulse, and dsflexeoamctxcscancfg.countrtthrd is 595 and dsflexeoamctxcscancfg.counterfrccfg.counterfrccfg is about 0.ch can be configured to achieve the precise time interval. The required time interval can be reached according to the pseudo-code logic of fig. 5 b. In particular, considering that the private switch chip does not generally support decimal operations, using the pseudo code logic herein, the decimal count part performs an increment operation each time the countthrd is reached, and when the decimal part carries, the threshold value satisfying the condition needs to be increased by 1 next time, i.e., dsflexeoamtxscancounter. Countfrac [8] is 1, so as to approximately average the counting process of the decimal in multiple cycles.
When the count value of the nth counter reaches the count threshold value of the nth counter, setting the bit of the FlexeeEOamTxScanBitmap corresponding to the nth counter in the n-th counter to be 1, indicating that the Flexe Client corresponding to the nth counter reaches the time trigger condition of 16K frames, and performing timing processing of a second-stage timer to trigger subsequent operation.
It should be noted that, both DsFlexEOamTxScanCounter and DsFlexEOamTxScanCfg registers need to store the relevant counter and configuration for each FlexE Client, so that FlexE clients reaching different bandwidth rates can have different time interval configurations.
The second-stage timer can adopt an 8ns fixed polling timer, and the subsequent processing of the FlexeE Client with one bit of 1 in FlexeeAmTxScanBitmap is processed every 8ns. Here 8ns is an adjustable value that can be adjusted within the chip design to allow for subsequent processing with as little polling time as possible.
As shown in fig. 5c, based on the timing process of the first-level timer and the second-level timer, when the processing logic proceeds to the functional processing module, it means the time interval of the 16K data frame of the bandwidth corresponding to the current FlexE Client is reached. Other code block intervals can be obtained by multiplying the code block interval of the 16K data frame. For example, the BAS code block needs to support the code block interval of 16K/32K/64K/128K/256K/512K.
Further, a Counter register called basperio Counter may be added to the BAS Period Counter module of the functional processing module, and is used to configure a multiple of 16K, for example, if the current FlexE Client needs to configure a code block interval of 64K frames, the Counter value is configured to be 4. When the BasPeriodCounter is not 0, not processing, and waiting for the code block interval trigger of the next 16K frame; when the baseperiodcounter is decreased to 0, the transmission of the BAS frame is triggered, and the baseperiodcounter is set to an initial value of 4, waiting for the code block interval trigger of the next 16K frame round.
Further, if other frames need to be transmitted at the rate of second, the multiple value of 1 second is calculated according to the previously calculated 16K frame time interval corresponding to the current FlexE Client bandwidth, for example, the time interval corresponding to the 16K frame is 19065.018ns with 55G bandwidth as an example, the multiple value of 1 second can be configured as 52452, and the decimal processing can be omitted on the premise of allowing a certain error. Here, onespecperiodcounter may be configured to be 52452, the process flow is similar to baseperiodcounter, and when onespecperiodcounter is decremented to 0, it indicates that a 1 second interval is triggered.
Still further, similar processing is performed for different OAM frames that require time intervals of the order of seconds, here exemplified by CV code blocks. If the CV code block generation rate needs to be set to 1 second, the CVPeriodCounter initial value is configured to be 1, and by analogy, if the CV code block generation rate needs to be set to 10 seconds, the CVPeriodCounter initial value is configured to be 10.1 minute, set to 60. Subsequently using similar logic, when CVPeriodCounter is 0, then sending the CV frame is triggered and CVPeriodCounter is restored to the initial value. Other second-level OAM frames are processed using similar logic.
Fig. 5d is a schematic diagram of a BAS timeout processing mechanism triggered by a timer according to an embodiment of the present application, and fig. 5e is a flowchart of a timeout count update processing mechanism in a receiving direction. As shown in fig. 5d, at 16K frame intervals, a baserapidcount decrease of 1 operation is triggered, the baserapidcount is used to configure a preset number of consecutive times for a timeout alarm, and when the baserapidcount decreases to 0, a timeout is considered to occur, triggering an alarm. Meanwhile, as shown in fig. 5e, in the receiving direction, when the BAS is received, the baseexpered count is updated to be the preconfigured preset continuous number, for example, if it needs to be considered that the BAS is not received for 3 consecutive frame interval periods as time out, the preconfigured preset continuous number is configured to be 3. The overtime alarm mechanism can be realized by the timer timing decrement and the receiving direction refreshing processing.
In summary, the present application uses two stages of timers, and only two timers are needed, and by cascading the two stages of timers, resource saving and feasibility of chip design are fully considered while ensuring time accuracy of sending the FlexE OAM frame, so as to meet a time interval requirement required by a standard. Meanwhile, based on two stages of timers, the method can use one set of processing flow aiming at the time interval processing of different Flexe OAM frame types, can support various time intervals required by standards, and has strong expansibility.
It should be noted that the present application is directed to a code block transmission method based on a two-stage timer, which is brought about by the flexible bandwidth of FlexE OAM. However, the idea can be applied to chip-level processing similar code block transmission requirements based on two-level timers, and is not limited to the application in the single scene of Flexe OAM.
As shown in fig. 6, an embodiment of the present application provides a code block transmission apparatus, which may include:
a determining module 601, configured to determine a count threshold for counting clock pulses by a counter according to a period of the clock pulses, a bandwidth of a client, and a code block interval of a code block transmitted by a client with different bandwidths; the counters corresponding to the clients with different bandwidths are different;
a setting module 602, configured to set, when a count value of an nth counter reaches a count threshold of the nth counter, a count flag position corresponding to the nth counter in the register as a preset value; wherein the value of N is less than or equal to N, and N is the number of the clients;
a scanning module 603 for scanning the register;
the transmission module 604 is configured to receive a code block sent by a client corresponding to the mth counter or send the code block to the client corresponding to the mth counter when the count flag bit corresponding to the mth counter scanned in the register is a preset value, where a value of m is less than or equal to N.
In one embodiment, the scanning module is specifically configured to:
the register is scanned for a timing period of a timer, wherein the timing period of the timer is less than or equal to a period of the clock pulse.
In one embodiment, the determining module is specifically configured to:
determining the time interval for transmitting the code block according to the bandwidth of the nth client, the code block interval and the bit number contained in each frame in the code block interval;
determining a quotient between the time interval and the period of the clock pulse;
the integer part of the quotient is determined as the count threshold of the nth counter.
In one embodiment, the determining module is further specifically configured to:
when the quotient has a decimal part, recording the decimal part of the quotient;
and when the product of the fractional part and s is greater than or equal to 1, determining the maximum value of the current counting of the nth counter as the counting threshold value plus 1, wherein s is the counting turn of the current counting of the nth counter from 0 to the counting threshold value continuously.
In one embodiment, a code block includes: the code block spacing of the second code block is P times of the code block spacing of the first code block, and P is a positive integer greater than or equal to 2; the count threshold of the nth counter is: determined according to a code block interval of the first type of code block;
the setting module includes:
the first setting unit is used for setting the counting mark position corresponding to the first code block of the nth counter in the register as a preset value every time the counting value of the nth counter reaches the counting threshold value of the nth counter;
and the second setting unit is used for setting the counting mark position corresponding to the second class code block of the nth counter in the register as a preset value when the counting value of the nth counter reaches the counting threshold value of the nth counter for P times continuously.
In one embodiment, the code blocks further include a third type of code block, wherein the nth client transmits the third type of code block at a time interval q times the time interval at which the nth client transmits the first type of code block, the interval unit of the time interval is different from the interval unit of the code block interval, and q is a positive integer greater than or equal to 2;
the setting module further includes:
and the third setting unit is used for setting the counting mark position corresponding to the third code block of the nth counter in the register as a preset value when the count value of the nth counter reaches the counting threshold value of the nth counter for q times continuously.
In one embodiment, the apparatus further comprises:
the warning module is used for generating an overtime warning if the code block sent by the client corresponding to the mth counter is not received for the preset continuous times; wherein the preset continuous times are as follows: the number of times the count value of the mth counter reaches the count threshold value of the mth counter continuously.
It should be noted that: in the code block transmission apparatus provided in the above embodiment, when executing the code block transmission method, only the division of the above program modules is taken as an example, and in practical applications, the above processing distribution may be completed by different program modules according to needs, that is, the internal structure of the apparatus is divided into different program modules to complete all or part of the above-described processing. In addition, the code block transmission apparatus and the code block transmission method provided by the above embodiments belong to the same concept, and specific implementation processes thereof are detailed in the method embodiments and are not described herein again.
An embodiment of the present application further provides an electronic device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein: the processor, when executing the computer program, implements the steps of the code block transmission method according to any of the embodiments of the present application.
Fig. 7 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application, where the electronic device 700 shown in fig. 7 includes: at least one processor 701, a memory 702, at least one network interface 703. The various components in the electronic device 700 are coupled together by a bus system 704. It is understood that the bus system 704 is used to enable communications among the components. The bus system 704 includes a power bus, a control bus, and a status signal bus in addition to a data bus. For clarity of illustration, however, the various buses are labeled in fig. 7 as the bus system 704.
It will be appreciated that the memory 702 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory.
The memory 702 in the present embodiment is used to store various types of data to support the operation of the electronic device 700. Examples of such data include: any computer program, such as an executable program, for operating on the electronic device 700, where the program implementing the method of the embodiments of the present application may be embodied in the executable program.
The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored on the storage medium, and when the computer program is executed by a processor, the steps in the code block transmission method according to any one of the embodiments of the present application are implemented.
It should be noted that the storage medium of the embodiments of the present application may be implemented by any type of volatile or non-volatile storage device, or a combination thereof. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic Random Access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical Disc, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), synchronous Static Random Access Memory (SSRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), enhanced Synchronous Dynamic Random Access Memory (ESDRAM), enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), synchronous Dynamic Random Access Memory (SLDRAM), direct Memory (DRmb Access), and Random Access Memory (DRAM). The storage media described in the embodiments of the present application are intended to comprise, without being limited to, these and any other suitable types of memory.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described device embodiments are merely illustrative, for example, the division of the unit is only one logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps of implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer-readable storage medium, and when executed, executes the steps including the method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application or portions thereof that contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling an electronic apparatus (which may be a personal computer, a server, or a network device) to execute all or part of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media capable of storing program code.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of code block transmission, the method comprising:
determining a counting threshold value of a counter for counting the clock pulses according to the period of the clock pulses, the bandwidth of a client and the code block interval of the client transmission code block with different bandwidths; the counters corresponding to the clients with different bandwidths are different;
when the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of a count mark corresponding to the nth counter in a register as a preset value; the value of N is less than or equal to N, and N is the number of the clients;
scanning the register;
and when the counting flag bit corresponding to the mth counter in the register is scanned to be the preset value, receiving a code block sent by a client corresponding to the mth counter or sending the code block to the client corresponding to the mth counter, wherein the value of m is less than or equal to N.
2. The method of claim 1, wherein scanning the register comprises:
scanning the register for a timing period of a timer, wherein the timing period of the timer is less than or equal to the period of the clock pulse.
3. The method of claim 1, wherein determining a count threshold for a counter to count clock pulses according to a period of the clock pulses, a bandwidth of a client, and a code block interval of a code block transmitted by the client with different bandwidths comprises:
determining a time interval for transmitting the code block according to the bandwidth of the nth client, the code block interval and the bit number contained in each frame in the code block interval;
determining a quotient between the time interval and a period of the clock pulse;
determining an integer portion of the quotient as a count threshold of the nth counter.
4. The method of claim 3, further comprising:
when the quotient has a decimal part, recording the decimal part of the quotient;
and when the product of the fractional part and s is greater than or equal to 1, determining that the maximum value of the current counting of the nth counter is the counting threshold value plus 1, wherein s is the counting turn of the current counting of the nth counter from 0 to the counting threshold value continuously.
5. The method according to any one of claims 1 to 4,
the code block includes: the code block spacing of the second type code block is P times of the code block spacing of the first type code block, and P is a positive integer greater than or equal to 2;
the count threshold of the nth counter is: determined according to the code block interval of the first type code block;
when the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of a count mark corresponding to the nth counter in a register as a preset value, including:
every time the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of a count mark corresponding to the first code block of the nth counter in the register as the preset value; and/or the presence of a gas in the gas,
and when the count value of the nth counter reaches the count threshold value of the nth counter for P times continuously, setting the position of a count mark corresponding to the second code block of the nth counter in the register as the preset value.
6. The method of claim 5, wherein the code blocks further comprise a third type of code block, wherein the nth client transmits the third type of code block at a time interval q times the time interval at which the nth client transmits the first type of code block, the time interval having a unit of spacing different from the unit of spacing of the code block interval, and q is a positive integer greater than or equal to 2;
when the count value of the nth counter reaches the count threshold value of the nth counter, setting the position of a count mark corresponding to the nth counter in a register as a preset value, and further comprising:
and when the count value of the nth counter reaches the count threshold value of the nth counter for q times continuously, setting the position of a count mark corresponding to the third code block of the nth counter in the register as the preset value.
7. The method of claim 1, further comprising:
if the code block sent by the client corresponding to the mth counter is not received within the preset continuous times, generating an overtime alarm; wherein the preset continuous times are as follows: the number of times the count value of the mth counter reaches the count threshold value of the mth counter in succession.
8. An apparatus for code block transmission, the apparatus comprising:
the determining module is used for determining a counting threshold value of a counter for counting the clock pulses according to the period of the clock pulses, the bandwidth of a client and the code block interval of the code block transmitted by the client with different bandwidths; the counters corresponding to the clients with different bandwidths are different;
the setting module is used for setting the counting mark position corresponding to the nth counter in the register as a preset value when the counting value of the nth counter reaches the counting threshold value of the nth counter; the value of N is less than or equal to N, wherein N is the number of the clients;
a scanning module for scanning the register;
and the transmission module is used for receiving a code block sent by a client corresponding to the mth counter or sending the code block to the client corresponding to the mth counter when the counting flag bit corresponding to the mth counter in the register is scanned to be the preset value, wherein the value of m is less than or equal to N.
9. An electronic apparatus comprising a memory and a processor, wherein the memory has stored therein a computer program, and the processor is configured to execute the computer program to perform the code block transmission method of any of claims 1 to 7.
10. A computer-readable storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the code block transmission method of any of claims 1 to 7 when executed.
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| CN202111113008.5A CN115883689A (en) | 2021-09-23 | 2021-09-23 | Code block transmission method, device and storage medium |
| PCT/CN2022/112712 WO2023045625A1 (en) | 2021-09-23 | 2022-08-16 | Code block transmission method and apparatus, and storage medium |
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| US11018792B2 (en) * | 2017-12-22 | 2021-05-25 | Telefonaktiebolaget Lm Ericsson (Publ) | Methods and apparatus for configuring a flex ethernet node |
| CN110224775B (en) * | 2018-03-01 | 2021-10-29 | 中兴通讯股份有限公司 | Method, device and equipment for determining time information |
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