CN115883012A - Coding method and device - Google Patents
Coding method and device Download PDFInfo
- Publication number
- CN115883012A CN115883012A CN202210108120.8A CN202210108120A CN115883012A CN 115883012 A CN115883012 A CN 115883012A CN 202210108120 A CN202210108120 A CN 202210108120A CN 115883012 A CN115883012 A CN 115883012A
- Authority
- CN
- China
- Prior art keywords
- sequence
- data
- information sequence
- cache
- check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0014—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the source coding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Quality & Reliability (AREA)
- Error Detection And Correction (AREA)
Abstract
The application discloses a coding device includes: a step code error code decorrelation interleaver (SEDI), a step code encoder, a step code error code decorrelation deinterleaver (SEDD) and an output unit; the SEDI is used for receiving the first information sequence and carrying out SEDI processing on the first information sequence to obtain a second information sequence; the ladder code encoder is used for carrying out ladder coding on the second information sequence to obtain a first check sequence; the SEDD is used for carrying out SEDD processing on the first check sequence to obtain a second check sequence; the output unit is used for receiving the first information sequence, and merging and outputting the second check sequence and the first information sequence; or receiving the first information sequence at the next moment, and combining and outputting the second check sequence and the first information sequence at the next moment. The coding device disclosed by the application can play a role in reducing noise correlation, and the SEDD does not need to interleave an information sequence, so that the coding complexity is low.
Description
The application is a divisional application, the application number of the original application is 201810032298.2, the date of the original application is 2018, 01, 12 and the whole content of the original application is incorporated into the application by reference.
Technical Field
The present application relates to the field of coding, and in particular, to a coding method and apparatus for solving noise correlation.
Background
At present, the high-speed optical transmission network is developing towards large capacity, packetization and intellectualization. High-speed optical transmission networks need to use efficient Forward Error Correction (FEC) codes to combat optical impairments (such as uncompensated chromatic dispersion, polarization mode dispersion, and nonlinear effects) during optical transmission and maintain a sufficiently low bit Error rate over long distances. Most of these FEC codes are designed under Additive White Gaussian Noise (AWGN).
However, in an actual communication system, noise has a correlation, and the correlation of the noise may cause performance degradation of the FEC code. The coding method and the coding device can reduce the influence of noise correlation on a coding system, and have low coding complexity.
Disclosure of Invention
The present application aims to provide an encoding method and an encoding device, which solve the problem of performance degradation of an encoding system caused by noise correlation.
In a first aspect, an encoding apparatus is provided, including: a step code error code decorrelation interleaver (SEDI), a step code encoder, a step code error code decorrelation deinterleaver (SEDD) and an output unit; the SEDI is used for carrying out SEDI processing on the received first information sequence to obtain a second information sequence; the ladder code encoder is used for carrying out ladder coding on the second information sequence to obtain a first check sequence; the SEDD is used for performing SEDD processing on the first check sequence to obtain a second check sequence; the output unit is used for receiving the first information sequence, and merging and outputting the second check sequence and the first information sequence; or the second check sequence and the first information sequence at the next moment are merged and output.
The information sequence and the check sequence contained in the sequence finally output by the encoding device provided by the embodiment of the application are disordered (namely, interleaved) relative to the information sequence and the check sequence generated by the step code encoder, so that the effect of reducing noise correlation can be achieved, the SEDD does not need to interleave the information sequence, and the encoding complexity and the power consumption are not high.
In one possible implementation, the operations of the SEDI and the SEDD are reciprocal, and the SEDI and the SEDD interleave received data in units of bits. The embodiment can ensure the systematicness of the output sequence and improve the code performance.
In a possible implementation manner, the ladder code encoder includes a first cache and a second cache, where the first cache stores a second information sequence at a current time, and the second cache stores data stored in the first cache at a previous time; the ladder code encoder is used for encoding the mth row of data in the first cache and the nth row of data in the second cache to obtain mth check data, and writing the mth check data into the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n; and the ladder code encoder reads out the check data in the first cache to obtain the first check sequence.
In a possible implementation manner, when the number M of rows of the data in the first cache is greater than the number N of columns of the data in the second cache, the data in the second cache includes additional M-N columns of all-0 data, where M and N are both positive integers.
In one possible implementation manner, the length of the first information sequence and the second information sequence is 512 × 478 bits, and the length of the first check sequence and the length of the second check sequence are 512 × 32 bits.
In a second aspect, an encoding method is provided, including: receiving a first information sequence, and performing step code error code decorrelation interleaving (SEDI) processing on the first information sequence to obtain a second information sequence; carrying out ladder coding on the second information sequence to obtain a first check sequence; performing step code error code decorrelation de-interleaving (SEDD) processing on the first check sequence to obtain a second check sequence; and merging and outputting the second check sequence and the first information sequence, or merging and outputting the second check sequence and the first information sequence at the next moment.
In one possible implementation, the interleaving operation performed on the first information sequence and the interleaving operation performed on the first check sequence are reciprocal and are interleaved in units of bits. The embodiment can ensure the systematicness of the output sequence and improve the code performance.
In a possible implementation manner, the step coding is performed on the second information sequence to obtain a first check sequence, which specifically includes: encoding the mth row of data in the first cache and the nth row of data in the second cache to obtain mth check data, and writing the mth check data into the mth row of the first cache, wherein the first cache stores a second information sequence at the current moment, and the second cache stores data stored in the first cache at the previous moment; m and n are integers, and the value of m corresponds to the unique value of n; and reading the check data in the first cache to obtain the first check sequence.
In a possible implementation manner, when the number M of rows of the data in the first cache is greater than the number N of columns of the data in the second cache, the data in the second cache includes additional M-N columns of all-0 data, where M and N are both positive integers.
In one possible implementation manner, the length of the first information sequence and the second information sequence is 512 × 478 bits, and the length of the first check sequence and the length of the second check sequence are 512 × 32 bits.
In a third aspect, an encoding apparatus is provided, including: the system comprises an input interface, a processor and an output interface, wherein the processor is used for receiving a first information sequence through the input interface and sending a combined sequence through the output interface; the device is also used for performing step code error code decorrelation interleaving (SEDI) processing on the first information sequence to obtain a second information sequence; carrying out ladder coding on the second information sequence to obtain a first check sequence; performing step code error code decorrelation de-interleaving (SEDD) processing on the first check sequence to obtain a second check sequence; and merging the second check sequence and the first information sequence, or merging the second check sequence and the first information sequence at the next moment.
In one possible implementation, the interleaving operation performed on the first information sequence and the interleaving operation performed on the first check sequence are reciprocal and are interleaved in units of bits. The embodiment can ensure the systematicness of the output sequence and improve the code performance.
In a possible implementation manner, the step coding is performed on the second information sequence by the processor to obtain a first check sequence, which specifically includes: the processor encodes the mth row of data in the first cache and the nth row of data in the second cache to obtain mth check data, and writes the mth check data into the mth row of the first cache, wherein the first cache stores a second information sequence at the current moment, and the second cache stores data stored in the first cache at the previous moment; m and n are integers, and the value of m corresponds to the unique value of n; and reading the check data in the first cache to obtain the first check sequence.
In a possible implementation manner, when the number M of rows of the data in the first cache is greater than the number N of columns of the data in the second cache, the data in the second cache includes additional M-N columns of all-0 data, where M and N are both positive integers.
In one possible implementation manner, the lengths of the first information sequence and the second information sequence are 512 × 478 bits, and the lengths of the first check sequence and the second check sequence are 512 × 32 bits.
The information sequence and the check sequence contained in the sequence finally output by the encoding device provided by the embodiment of the application are disordered (namely, interleaved) relative to the information sequence and the check sequence generated by the step code encoder, so that the effect of reducing noise correlation can be achieved, the SEDD does not need to interleave the information sequence, and the encoding complexity and the power consumption are not high.
Drawings
Fig. 1 is a block diagram of a communication system;
fig. 2 is a block diagram of an encoding apparatus according to an embodiment of the present disclosure;
fig. 3 is a block diagram of a sed according to another embodiment of the present application;
fig. 4 is an interleaving table in the SEDD according to another embodiment of the present application;
fig. 5 (a) is a block diagram of an encoding apparatus according to another embodiment of the present application;
fig. 5 (b) is a block diagram of an encoding apparatus according to another embodiment of the present application;
fig. 6 (a) is a block diagram of an encoding apparatus according to another embodiment of the present application;
fig. 6 (b) is a block diagram of an encoding apparatus according to another embodiment of the present application;
FIG. 7 is a flowchart of an encoding method according to another embodiment of the present application;
fig. 8 is a block diagram of a coding apparatus according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
Fig. 1 shows a block diagram of a communication system, where at a transmitting end, a source provides a data stream to be transmitted; the encoder receives the data stream, encodes the data stream, sends the encoded data stream to the transmitter, and the transmitter sends the encoded data stream to the transmitter through a channel. At the receiving end, the receiver receives the coded data stream, decodes the coded data stream through a decoder, restores original data and sends the original data to an information sink. The encoding method provided by the present application is used in the encoder shown in fig. 1, and is a very important ring in a communication system.
An embodiment of the present application provides an encoding apparatus, as shown in fig. 2, including: (Staircase Error De-correlator Interleaver, SEDI) ladder code Error code decorrelation De-Interleaver 210, ladder code encoder 220, (Staircase Error De-correlator DE-Interleaver, SEDD) ladder code Error code decorrelation De-Interleaver 230 and output unit 240,
the SEDI 210 is used for receiving the first information sequence and performing SEDI processing on the first information sequence to obtain a second information sequence;
and the ladder code encoder 220 is configured to perform ladder encoding on the second information sequence to obtain a first check sequence.
Specifically, the ladder code encoder 220 includes a first cache and a second cache, where the first cache stores a second information sequence at a current time, and the second cache stores data stored in the first cache at a previous time; the step code encoder encodes the mth row of data in the first cache and the nth row of data in the second cache to obtain mth check data, and writes the mth check data into the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n; and reading the check data in the first cache to obtain a first check sequence.
Assuming that the second information sequence is 512 rows × 478 columns and m =3, n =1, the data of the 3 rd row in the first buffer and the data of the 1 st column in the second buffer together form data of 478+512=990 bits, and the data of the 990 bits are subjected to (Bose-Chaudhuri-Hocquenghem, BCH) encoding to obtain a BCH codeword with a length of 1022 bits, where the extra 32 bits of information are the 3 rd parity data, and the 3 rd parity data is stored in the 3 rd row of the first buffer; by analogy, 512 32-bit check data are obtained and are respectively stored in 512 lines of the first cache, wherein the value of m corresponds to the unique value of n, and the corresponding relation is written in advance.
It should be noted that the second cache stores all the data stored in the first cache at the previous time, that is, the second cache includes the information data and the check data stored in the first cache at the previous time, that is, the data in the second cache is 512 rows × 510 columns. At this time, the row number 512 of the data in the first cache is greater than the column number 510 of the data in the second cache, and the number of the data columns in the second cache is two columns less, then 2 additional columns of all-0 data are added to the data in the second cache, and the columns in the second cache are filled up, so that 512 32-bit check data can be obtained at the current time.
And the SEDD 230 is used for performing SEDD processing on the first check sequence to obtain a second check sequence. Specifically, the sed 230 performs dd processing on the first check sequence in units of bits; therein, SEDD 230 includes a first 12-stage interleaver 301, a packet interleaver 302, a second 12-stage interleaver 303, and a controller 304, as shown in FIG. 3. The first 12-stage interleaver 301 includes 12 serially connected interleavers, which together form an interleaving table as shown in fig. 4, where each 64-bit first check sequence is interleaved, and after passing through the interleaving table as shown in fig. 3, a 64-bit first information sequence that disturbs the position order is obtained; it is noted that fig. 4 shows 64 bits in the first check sequence as 1 to 64, and the positions of the bits after interleaving as 0 to 63. Wherein the controller 304 can generate twelve bits of binary control data p1_ cnt (with a value ranging from 1 to 4095) to control which one or more of the 12 serial interleavers included in the first 12-stage interleaver function; for example, when p1_ cnt =1 (0000 0000 0001), the first 11 interleavers are not functional, and only the 12 th interleaver is functional, which is reflected in the interleaving table shown in fig. 4, i.e., columns 1 to 11 are not functional, and only column 12 is needed. At this time, after the 1 st bit of the first check sequence is interleaved, the value of the 1 st row and 12 th column is 4, which indicates the position of the 5 th bit; after the 2 nd bit of the first check sequence is interleaved, the value of the 12 nd column in the 2 nd row is 11, which indicates the position of the 12 th bit; and by analogy, interleaving the first check sequence of every 64 bits to obtain the first check sequence in a disordered sequence. When p1_ cnt =3 (0000 0000 0011), the first 10 interleavers are not functional, and only the 11 th interleaver and the 12 th interleaver operate, at this time, only 11-12 columns in fig. 4 may be seen, where the 1 st bit of the first check sequence is first interleaved by the 11 th interleaver, the value of the 11 st column in the 1 st row is 14, which indicates the position of the 15 th bit, and then the 15 th bit passes by the 12 th interleaver, the value of the 12 th column in the 15 th row is 47, which indicates the position of the 48 th bit, that is, the 1 st bit of the first check sequence is changed to the position of the 48 th bit after passing through the first 12-stage interleaver, and so on, the first check sequence of every 64 bits is interleaved, so as to obtain the first check sequence in a scrambled order.
It should be noted that the first 12-stage interleaver 301 is time-varying with a time-varying period of 5, that is, the interleaving table shown in fig. 4 is only one of five interleaving tables included in the first 12-stage interleaver 301, and after the interleaving of a group of 64-bit first check sequences is completed, the next interleaving table is switched to, and the process is repeated.
A packet interleaver 302 for performing a "run list" interleaving operation on the first check sequence after passing through the first 12-stage interleaver 301; still taking the first information sequence as 512 rows × 478 as an example, after the ladder code encoder 220, the length of the first check sequence should be 512 rows × 32 columns, i.e. 16384 bits. The first check sequence may be divided into 256 groups of 64-bit sequences, each group of 64-bit sequences is interleaved by the first 12-stage interleaver 301, and the interleaved data is sent to the packet interleaver 302; the packet interleaver 302 divides the interleaved data into 8 groups of 2048 bits each, sequentially performs row-column interleaving on the 8 groups of data, and sends the row-column interleaved data to the second 12-level interleaver 303, wherein the row-column interleaving mode of each group of data is as follows: firstly, writing into a packet interleaver 302 by rows, wherein each row has 64 bits and has 32 rows; when reading, it is read in columns, with the first 32 bits of the output sequence coming from the first column, the 33-64 bits from the second column, and so on.
And a second 12-stage interleaver 303, configured to perform interleaving processing on the sequence output by the packet interleaver 302 again to obtain a second check sequence. Among them, the second 12-stage interleaver 303 is the same in structure as the first 12-stage interleaver 301 except that the interleaving table in the second 12-stage interleaver 303 is different from the interleaving table in the first 12-stage interleaver 301. Further, when controlling the second 12-stage interleaver 303 to operate, the value range of the twelve-bit binary control signal p2_ cnt generated by the controller 304 is: 1 to (4095-41).
It should be noted that the interleaving function of the SEDI and the interleaving function of the SEDD are reversible, and the data entering the SEDI sequentially enters a third 12-stage interleaver, a packet interleaver and a fourth 12-stage interleaver for interleaving and outputting, wherein the third 12-stage interleaver performs the inverse operation of the second 12-stage interleaver, the fourth 12-stage interleaver performs the inverse operation of the first 12-stage interleaver, and the packet interleaver of the SEDI performs the inverse operation of the packet interleaver of the SEDD.
Specifically, the implementation of the packet interleaver in the SEDI is described below. Since the length of data entering the packet interleaver in the SEDI is 512 × 478=244736 bits, the 244736 bits are divided into 8 groups of 30592 bits each, and the following operations are performed on the 30592-bit data: dividing the 30592-bit data into 12 groups, wherein the first 11 groups comprise 40 multiplied by 64 bits, writing the data into a packet interleaver by columns, and each column comprises 40 bits and 64 columns; group 12 consists of 38 x 64 bits, again written into the block interleaver in columns, 38 bits per column, for 64 columns; when reading, the reading is carried out according to rows, the 64 bits of the first row are read first, then the second row is read, and so on. The packet interleaver of the SEDI sequentially performs interleaving of "column out" on 8 sets of 30592-bit data, and then sends the interleaved data to the fourth 12-stage interleaver.
An output unit 240, configured to receive the first information sequence, and output the second check sequence and the first information sequence in a merged manner; or receiving the first information sequence at the next moment, and combining and outputting the second check sequence and the first information sequence at the next moment.
Specifically, for the case that the output unit 240 outputs the second parity sequence and the first information sequence in a merged manner, the output unit 240 includes a buffer unit 541 and a merging unit 542, as shown in fig. 5 (a), the buffer unit is configured to store the first information sequence, and after the second parity sequence is output by the SEDD 230, the second parity sequence and the first information sequence are output in a merged manner by the merging unit, or the output unit 240 includes a delay unit 543 and a merging unit 542, as shown in fig. 5 (b), the delay unit 543 delays the first information sequence, and the merging unit 542 outputs the second parity sequence and the first information sequence in a merged manner, where a specific delay time is: the difference between the time when the first information sequence enters the encoding device and the time when the second check sequence occurs is subtracted by the time required for outputting the first information sequence. At this time, after the first information sequence is output, the second check sequence is output next, and no additional buffer is needed.
Further, for the case that the output unit 240 outputs the second parity sequence and the first information sequence at the next time in a merged manner, the output unit 240 may include a buffer unit 641 and a merge unit 642, as shown in fig. 6 (a), the buffer unit 641 is configured to store the second parity sequence, and wait until the output unit 240 receives the first information sequence at the next time, and then merge and output the second parity sequence and the first information sequence at the next time by using the merge unit 642, or the output unit 240 includes a delay unit 643 and a merge unit 642, as shown in fig. 6 (b), the delay unit 643 delays the second parity sequence, and then merges and output the second parity sequence and the first information sequence at the next time by using the merge unit 642, where the specific delay time is: the difference between the time of generation of the second check sequence and the time at which the first information sequence is output from the encoding device at the next time. At this time, after the first information sequence at the next moment is output, the second check sequence at the current moment is output, and no additional buffer is needed.
The information sequence and the check sequence included in the sequence finally output by the encoding device provided by this embodiment are scrambled (i.e., interleaved) with respect to both the information sequence and the check sequence generated by the ladder code encoder, so that the effect of reducing noise correlation can be achieved, and the SEDD does not need to interleave the information sequence, and the complexity of encoding and power consumption are not high.
Another embodiment of the present application provides an encoding method, as shown in fig. 7, including:
701. and receiving the first information sequence, and carrying out SEDI processing on the first information sequence to obtain a second information sequence.
702. And carrying out step coding on the second information sequence to obtain a first check sequence.
703. And performing SEDD processing on the first check sequence to obtain a second check sequence.
704. Combining and outputting the second check sequence and the first information sequence; or receiving the first information sequence at the next moment, and combining and outputting the second check sequence and the first information sequence at the next moment.
The interleaving manner of the SEDI and the SEDD has been described in detail in the foregoing embodiment of the apparatus, and the embodiment is not described herein again.
Optionally, the first information sequence at the current moment is stored in a first cache, and the data stored in the first cache at the previous moment is stored in a second cache; step 702 specifically includes: encoding the mth row of data in the first cache and the nth row of data in the second cache to obtain mth check data, and writing the mth check data into the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n; and reading the check data in the first cache to obtain a first check sequence.
Further, when the number M of rows of data in the first buffer is greater than the number N of columns of data in the second buffer, the data in the second buffer includes additional M-N columns of all-0 data, where M and N are both positive integers.
Optionally, the merging and outputting the second check sequence and the first information sequence specifically includes: storing the first information sequence, combining and outputting the second check sequence and the first information sequence after the second check sequence is obtained, or delaying the first information sequence, and combining and outputting the second check sequence and the first information sequence, wherein the specific delay time is as follows: the difference between the time when the first information sequence enters the encoding device and the time when the second check sequence occurs is subtracted by the time required for outputting the first information sequence. At this time, after the first information sequence is output, the second check sequence is output next, and no additional buffer is needed.
Optionally, the merging and outputting the second check sequence and the first information sequence at the next time includes: storing the second check sequence, merging and outputting the second check sequence and the first information sequence at the next moment after receiving the first information sequence at the next moment, or delaying the second check sequence, merging and outputting the second check sequence and the first information sequence at the next moment, wherein the specific delay time is as follows: the difference between the time of generation of the second check sequence and the time at which the first information sequence is output from the encoding device at the next time. At this time, after the first information sequence at the next moment is output, the second check sequence at the current moment is output, and no additional buffer is needed.
In the encoding method provided in this embodiment, the information sequence and the check sequence included in the finally output sequence are scrambled (that is, interleaved) with respect to both the information sequence and the check sequence generated by encoding, so that the effect of reducing noise correlation can be achieved, and in step 703, interleaving of the information sequence is not required, and the complexity and power consumption of encoding are not high.
Another embodiment of the present application provides an encoding apparatus 800, as shown in fig. 8, including: an input interface 801, a processor 802, and an output interface 803; the processor 802 is configured to receive the first information sequence through the input interface 801, send the merged sequence through the output interface 803, and implement the steps and functions implemented by the concatenated coding apparatus 800 in the foregoing embodiments, which are not described herein again.
The present application provides a computer-readable storage medium or a computer program product for storing a computer program for executing the encoding method involved in the above method embodiments.
It will be appreciated that fig. 8 only shows a simplified design of the encoding device. In practical applications, the encoding apparatus may include any number of interfaces, processors, and the like, and all terminals that can implement the embodiments of the present application are within the scope of the embodiments of the present application.
It is further understood that the processor referred to in the embodiments of the present application may be a Central Processing Unit (CPU), and may also be other general purpose processors, digital Signal Processors (DSP), application Specific Integrated Circuits (ASIC), field Programmable Gate Arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and so on. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In various embodiments of the present invention, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
In short, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (15)
1. An encoding apparatus, comprising: a ladder code error decorrelation interleaver (SEDI), a ladder code decoder, a ladder code error decorrelation deinterleaver (SEDD),
the SEDI is used for carrying out SEDI processing on the received first received information sequence to obtain a second received information sequence;
the SEDI is used for carrying out SEDI processing on the received second receiving check sequence to obtain a first receiving check sequence;
the ladder code decoder is used for carrying out ladder decoding on the second received information sequence and the first received check sequence to obtain a second information sequence;
the SEDD is used for performing SEDD processing on the second information sequence to obtain a first information sequence and outputting the first information sequence;
the first received information sequence is obtained after the first information sequence is transmitted through a channel, and the second received check sequence is obtained after the second check sequence is transmitted through the channel.
2. The encoding device of claim 1, wherein the operations of the SEDI and the SEDD are reciprocal, the SEDI and the SEDD interleaving the received data in units of bits.
3. The encoding apparatus according to claim 1 or 2, wherein the ladder decoder includes a first buffer and a second buffer, wherein the first buffer stores a second received information sequence and a first received check sequence at a current time, and the second buffer stores information data and check data stored in the first buffer at least one time before the current time;
the ladder code decoder is used for merging the mth row of data in the first cache and the nth row of data in the second cache, decoding to obtain decoded mth row of data and nth row of data, and writing the decoded mth row of data and the decoded nth row of data into the mth row of the first cache and the nth row of the second cache respectively, wherein m and n are integers, and the value of m corresponds to the unique value of n;
and the ladder code decoder reads out second information sequence data of a first moment in the second cache to obtain a second information sequence, wherein the first moment is one of at least one moment before the current moment.
4. The encoding apparatus according to claim 3, wherein when the number of rows M of data in the first buffer is greater than the number of columns N of data in the second buffer, the data in the second buffer comprises additional M-N columns of all-0 data, where M and N are both positive integers.
5. The encoding device according to claim 1 or 2, wherein the first information sequence and the second information sequence have a length of 512 x 478 bits, and the first check sequence and the second check sequence have a length of 512 x 32 bits.
6. An encoding method, comprising:
receiving an information sequence, wherein the information sequence comprises a first received information sequence and a second received check sequence, and respectively performing step code error code de-correlation interleaving (SEDI) processing on the first received information sequence and the second received check sequence to obtain a second received information sequence and a first received check sequence;
carrying out step decoding on the second received information sequence and the first received check sequence to obtain a second information sequence;
performing step code error code decorrelation de-interleaving (SEDD) processing on the second information sequence to obtain a first information sequence;
receiving the first information sequence and outputting the first information sequence,
the first received information sequence is obtained after the first information sequence is transmitted through a channel, and the second received check sequence is obtained after the second check sequence is transmitted through the channel.
7. The encoding method according to claim 6, wherein the interleaving operation performed on the first information sequence and the interleaving operation performed on the first check sequence are reciprocal and are interleaved in units of bits.
8. The encoding method according to claim 6 or 7, wherein the step decoding is performed on the second received information sequence and the first received check sequence to obtain a second information sequence, and specifically comprises:
merging the mth row of data in a first cache and the nth row of data in a second cache, decoding to obtain the decoded mth row of data and the decoded nth row of data, and writing the mth row of data and the nth row of data into the mth row of the first cache and the nth row of data in the second cache respectively, wherein the first cache stores a second received information sequence and a first received check sequence at the current moment, and the second cache stores information data and check data stored in the first cache at least one moment before the current moment; m and n are integers, and the value of m corresponds to the unique value of n;
and reading out second information sequence data of a first time in the second cache to obtain a second information sequence, wherein the first time is one of at least one time before the current time.
9. The encoding method of claim 8, wherein when the number of rows M of data in the first buffer is greater than the number of columns N of data in the second buffer, the data in the second buffer comprises additional M-N columns of all 0 data, where M and N are both positive integers.
10. The encoding method according to claim 6 or 7, wherein the first information sequence and the second information sequence have a length of 512 x 478 bits, and the first check sequence and the second check sequence have a length of 512 x 32 bits.
11. An encoding apparatus, comprising: an input interface, a processor and an output interface; wherein the content of the first and second substances,
the processor is used for receiving the combined sequence through the input interface and sending a first information sequence through the output interface; the device is also used for performing step code error code decorrelation interleaving (SEDI) processing on the first received information sequence to obtain a second received information sequence, and performing SEDI processing on the second received check sequence to obtain a first received check sequence; carrying out step decoding on the second received information sequence and the first received check sequence to obtain a second information sequence; and performing step code error code decorrelation de-interleaving (SEDD) processing on the second information sequence to obtain a first information sequence.
12. The encoding apparatus according to claim 11, wherein the interleaving operation performed on the first information sequence and the interleaving operation performed on the first check sequence are reciprocal and are interleaved in units of bits.
13. The encoding device as claimed in claim 11 or 12, wherein the processor performs step decoding on the second received information sequence and the first received check sequence to obtain the second information sequence, and specifically comprises:
the processor merges the mth row of data in the first cache and the nth row of data in the second cache, decodes the mth row of data and the nth row of data to obtain the decoded mth row of data and the decoded nth row of data, and writes the decoded mth row of data and the decoded nth row of data into the mth row of the first cache and the nth row of the second cache respectively, wherein the first cache stores a second received information sequence and a first received check sequence at the current moment, and the second cache stores information data and check data stored in the first cache at least one moment before the current moment; m and n are integers, and the value of m corresponds to the unique value of n;
and reading out second information data of a first moment in the second cache to obtain a second information sequence, wherein the first moment is one of at least one moment before the current moment.
14. The encoding apparatus of claim 13, wherein when the number of rows M of data in the first buffer is greater than the number of columns N of data in the second buffer, the data in the second buffer comprises additional M-N columns of all 0 data, where M and N are both positive integers.
15. The encoding apparatus according to claim 11 or 12, wherein the first information sequence and the second information sequence have a length of 512 x 478 bits, and the first check sequence and the second check sequence have a length of 512 x 32 bits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210108120.8A CN115883012A (en) | 2018-01-12 | 2018-01-12 | Coding method and device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810032298.2A CN110034846B (en) | 2018-01-12 | 2018-01-12 | Coding method and device |
| CN202210108120.8A CN115883012A (en) | 2018-01-12 | 2018-01-12 | Coding method and device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810032298.2A Division CN110034846B (en) | 2018-01-12 | 2018-01-12 | Coding method and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115883012A true CN115883012A (en) | 2023-03-31 |
Family
ID=67234508
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810032298.2A Active CN110034846B (en) | 2018-01-12 | 2018-01-12 | Coding method and device |
| CN202210106599.1A Active CN114598420B (en) | 2018-01-12 | 2018-01-12 | Coding method and device |
| CN202210108120.8A Pending CN115883012A (en) | 2018-01-12 | 2018-01-12 | Coding method and device |
Family Applications Before (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810032298.2A Active CN110034846B (en) | 2018-01-12 | 2018-01-12 | Coding method and device |
| CN202210106599.1A Active CN114598420B (en) | 2018-01-12 | 2018-01-12 | Coding method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (3) | CN110034846B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115276796A (en) * | 2022-06-23 | 2022-11-01 | 兰州理工大学 | Ladder code based atmospheric optical transmission method with super-Nyquist rate |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100379380B1 (en) * | 1999-09-15 | 2003-04-10 | 엘지전자 주식회사 | Method for removing interference signal in communication system |
| US8019020B1 (en) * | 2006-11-01 | 2011-09-13 | Marvell International Ltd. | Binary decoding for correlated input information |
| US8254502B2 (en) * | 2008-12-22 | 2012-08-28 | Qualcomm Incorporated | Post decoding soft interference cancellation |
| CN102064917B (en) * | 2011-01-11 | 2013-01-02 | 河海大学 | Demodulation decoding method for LDPC (Low Density Parity Code) modulation system |
| US8751910B2 (en) * | 2011-04-13 | 2014-06-10 | Cortina Systems, Inc. | Staircase forward error correction coding |
| US8601340B2 (en) * | 2011-07-25 | 2013-12-03 | Cortina Systems, Inc. | Time varying data permutation apparatus and methods |
| CN104901770B (en) * | 2014-03-06 | 2019-12-13 | 中兴通讯股份有限公司 | Error code decorrelation method and device, data processing method, device and system |
| CN106059596B (en) * | 2016-06-24 | 2019-05-14 | 中山大学 | Using binary BCH code as the grouping markov supercomposed coding method and its interpretation method of composition code |
-
2018
- 2018-01-12 CN CN201810032298.2A patent/CN110034846B/en active Active
- 2018-01-12 CN CN202210106599.1A patent/CN114598420B/en active Active
- 2018-01-12 CN CN202210108120.8A patent/CN115883012A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN114598420B (en) | 2024-07-05 |
| CN114598420A (en) | 2022-06-07 |
| CN110034846B (en) | 2021-12-10 |
| CN110034846A (en) | 2019-07-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10944430B2 (en) | Time varying data permutation apparatus and methods | |
| US8543884B2 (en) | Communications channel parallel interleaver and de-interleaver | |
| US6854077B2 (en) | Apparatus and method for providing turbo code interleaving in a communications system | |
| WO2020228126A1 (en) | Data transmission, encoding and decoding method, apparatus and device, and storage medium | |
| KR20020067382A (en) | Code generating and decoding apparatus and method in communication system | |
| KR102281107B1 (en) | Method for encoding data, encoder, decoder, and communication system | |
| JP4420924B2 (en) | Method and encoder for encoding an information bit sequence | |
| US8166373B2 (en) | Method and apparatus for turbo encoding and decoding | |
| KR100628201B1 (en) | Method for Turbo Decoding | |
| CN110034846B (en) | Coding method and device | |
| KR100504988B1 (en) | Hybrid interleaver for turbo codes | |
| CN111130572A (en) | Turbo code quick realizing method | |
| KR20060121312A (en) | Convolutional turbo code interleaver | |
| CN113472362A (en) | Coding method and device for data communication | |
| JP4420925B2 (en) | Method and encoder for encoding an information bit sequence | |
| CN110034847B (en) | Cascade coding method and device | |
| KR20000001483A (en) | Turbo code having multiple tail and encoding/decoding method thereof and encoder/decoder using that | |
| KR20030047100A (en) | Apparatus for sharing memory between interleaver and deinterleaver in turbo decoder and method thereof | |
| KR100218680B1 (en) | Convolution encoding method | |
| CN114337689A (en) | Method and device for coding and decoding duobinary Turbo code | |
| KR100332805B1 (en) | Serially concatenated convolutional encoding apparatus and encoding/decoding method | |
| KR100651473B1 (en) | A high speed turbo decoder using pipe-line processing | |
| KR20140144055A (en) | Turbo code system | |
| JP2006060859A (en) | Turbo decoding equipment and receiving mobile communications systems provided with turbo decoding equipment using memory and decoder |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |