CN115881727A

CN115881727A - Semiconductor structure and forming method thereof

Info

Publication number: CN115881727A
Application number: CN202111144545.6A
Authority: CN
Inventors: 陈建
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2021-09-28
Filing date: 2021-09-28
Publication date: 2023-03-31

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the method comprises the following steps: providing a first substrate comprising opposing first and second sides; forming a first epitaxial layer on the first surface; forming a plurality of mutually-separated fin part structures on the top surface of the first epitaxial layer; forming a first device layer on the surfaces of the first epitaxial layer and the fin structure; providing a second substrate having circuitry therein; bonding the first substrate and the second substrate after forming the first device layer, the first side facing the second substrate, and the circuit being electrically interconnected with the first device layer; removing the first substrate after bonding the first substrate and the second substrate; and after the first substrate is removed, a plurality of first conductive plugs are formed, the first conductive plugs are electrically interconnected with the first device layer, and the surfaces of the first conductive plugs are exposed out of the bottom surface of the first epitaxial layer. Therefore, the integration level of the semiconductor structure is improved, and meanwhile, the performance of the semiconductor structure can be improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the development of semiconductor technology, the feature size of integrated circuits is continuously reduced, and the interconnection density of devices is continuously improved. 3D System on Chip (3D-SOC) technology is capable of providing very high density interconnects and, thus, is one of the important directions in integrated circuit design.

In most 3D-SOC solutions, wafer to Wafer (Wafer) bonding is required, and circuit connection is further realized Through Silicon Via (TSV) technology. In the prior art, after a wafer is bonded to a wafer, the thickness of the wafer is usually reduced by a back thinning technique, for example, grinding, dry etching or wet etching is performed on the back of the wafer. However, the thinned wafer thickness still reaches the micron level. Accordingly, the depth of the through-silicon via needs to reach the micron level because of the need to penetrate the wafer. The aspect ratio (TSV aspect ratio) of the through silicon via is generally required to be below 10 due to the limitation of the etching process in the prior art, and therefore, the area occupied by the through silicon via on the surface of the wafer is large due to the limitation of the micron-scale depth of the through silicon via, which results in poor integration level of the semiconductor structure. Meanwhile, in the prior art, silicon is generally used as a material of a wafer, and compared with some strained materials, such as silicon germanium and the like, the carrier mobility of silicon is small, so that the driving current of a semiconductor device such as a MOS transistor is small, and the performance of a semiconductor structure is poor.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which aims to improve the integration level of the semiconductor structure and simultaneously improve the performance of the semiconductor structure.

To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: a first epitaxial layer having opposing top and bottom surfaces; the fin structures are positioned on the top surface of the first epitaxial layer and are separated from each other; the first device layer is positioned on the surfaces of the first epitaxial layer and the fin structures and comprises a plurality of device structures, a plurality of interconnection structures and an isolation medium structure, and the fin structures, the interconnection structures and the device structures are surrounded by the isolation medium structure; a second substrate bonded to the first device layer, the second substrate having circuitry therein, the circuitry being electrically interconnected with the first device layer; the first conductive plugs are positioned in the first epitaxial layer and the first device layer and electrically interconnected with the first device layer, and the surfaces of the first conductive plugs are exposed out of the bottom surface of the first epitaxial layer.

Optionally, the height of the first conductive plug ranges from 240 nm to 800 nm.

Optionally, the thickness of the first epitaxial layer ranges from 200 nm to 500 nm.

Optionally, the material of the first epitaxial layer includes silicon germanium.

Optionally, the content of germanium in the material of the first epitaxial layer is 10% to 30%.

Optionally, the first epitaxial layer includes a first region and a second region, and the plurality of fin structures includes: a number of first fins located on the first region, a number of second fins located on the second region, the first fins and the second fins being of different materials.

Optionally, the first fin further extends into the first epitaxial layer, the first fin includes a first relaxed buffer layer and a first top layer on the first relaxed buffer layer, the first relaxed buffer layer refers to a portion of the first fin that extends into the first epitaxial layer, a material of the first top layer includes silicon, and a material of the first relaxed buffer layer includes silicon germanium.

Optionally, the second fin further extends into the first epitaxial layer, the second fin includes a second strain relaxation buffer layer and a second top layer located on the second strain relaxation buffer layer, the second strain relaxation buffer layer refers to a portion of the second fin extending into the first epitaxial layer, a material of the second top layer includes silicon germanium, a material of the second strain relaxation buffer layer includes silicon germanium, and a content of germanium in the material of the second top layer is greater than a content of germanium in the material of the second strain relaxation buffer layer.

Optionally, the content of germanium in the material of the second top layer is 40% to 100%, and the content of germanium in the material of the second strain relaxation buffer layer is 10% to 30%.

Optionally, the method further includes: and a metal wiring layer on the exposed surface of the first conductive plug.

Optionally, the first device layer includes a plurality of device structures, a plurality of interconnect structures, and an isolation dielectric structure, and the isolation dielectric structure surrounds the fin structure, the interconnect structures, and the device structures.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a first substrate comprising opposing first and second sides; forming a first epitaxial layer on the first surface, wherein the first epitaxial layer is provided with a top surface and a bottom surface which are opposite, the bottom surface of the first epitaxial layer is in contact with the first surface, and the material of the first epitaxial layer is different from that of the first substrate; forming a plurality of mutually-separated fin part structures on the top surface of the first epitaxial layer; forming a first device layer on the surfaces of the first epitaxial layer and the fin structure; providing a second substrate having circuitry therein; bonding the first substrate and the second substrate after forming the first device layer, the first side facing the second substrate, and the circuit being electrically interconnected with the first device layer; removing the first substrate after bonding the first substrate and the second substrate; and after the first substrate is removed, a plurality of first conductive plugs are formed in the first epitaxial layer and the first device layer, the first conductive plugs are electrically interconnected with the first device layer, and the surfaces of the first conductive plugs are exposed from the bottom surface of the first epitaxial layer.

Optionally, the forming process of the first epitaxial layer includes an epitaxial growth process, and the parameters of the epitaxial growth process include: the reaction gas comprises GeH ₄ And SiH ₄ Or SiH ₂ Cl ₂ The deposition temperature is 600-900 ℃, and GeH ₄ The percentage concentration of the gas is 10-35%.

Optionally, the method for removing the first substrate includes: thinning the first substrate from the second surface until the thickness of the first substrate is within a second preset thickness range; and after thinning the first substrate, etching or flattening the first substrate from the second surface until the surface of the first epitaxial layer is exposed.

Optionally, the second predetermined thickness range is 8 to 12 micrometers.

Optionally, the first substrate is thinned from the second surface at a first etching rate, and after the first substrate is thinned, the first substrate is etched or planarized from the second surface at a second etching rate, which is lower than the first etching rate.

Optionally, the process for thinning the first substrate from the second side includes: a dry etching process or a chemical mechanical polishing process.

Optionally, the dry etching process includes a plasma etching process, and the gas used in the plasma etching process includes Cl ₂ 、HBr、SF ₆ And CF ₄ One or more of (a).

Optionally, after thinning the first substrate, the first substrate is etched from the second surface by using a dry etching process, and parameters of the dry etching process include: the gas used comprises H ₂ 、CF ₄ And Ar, or the gas used comprises H ₂ 、NF ₃ And Ar, and H ₂ 、CF ₄ And Ar at a gas flow ratio of 10 ₂ 、NF ₃ And Ar gas flow ratio of 10.

Optionally, the first fin and the second fin further extend into the first epitaxial layer, the first fin includes a first relaxed strain buffer layer and a first top layer on the first relaxed strain buffer layer, the second fin includes a second relaxed strain buffer layer and a second top layer on the second relaxed strain buffer layer, the first relaxed strain buffer layer refers to a portion of the first fin that extends into the first epitaxial layer, and the second relaxed strain buffer layer refers to a portion of the second fin that extends into the first epitaxial layer.

Optionally, the method for forming the plurality of fin structures includes: forming a second epitaxial layer on the top surface of the first epitaxial layer on the first region and the second region; forming a first opening in the second epitaxial layer, wherein the first opening exposes the surface of the first epitaxial layer on the second region; forming a third epitaxial layer in the first opening, wherein the first opening is filled with the third epitaxial layer; forming a plurality of fin mask structures which are mutually separated on the second epitaxial layer and the third epitaxial layer; and etching the second epitaxial layer on the first region and the third epitaxial layer on the second region by taking the fin mask structure as a mask until part of the first epitaxial layer is etched.

Optionally, the material of the first epitaxial layer and the material of the third epitaxial layer include silicon germanium, the material of the second epitaxial layer includes silicon, and the content of germanium in the material of the third epitaxial layer is greater than the content of germanium in the material of the first epitaxial layer.

Optionally, the process for forming the third epitaxial layer includes an epitaxial growth process, and parameters of the epitaxial growth process include: the reaction gas comprises GeH ₄ And SiH ₄ Or SiH ₂ Cl ₂ The deposition temperature is 600-900 ℃, and GeH ₄ The percentage concentration of the gas is 40% -65%.

Optionally, the thickness of the second epitaxial layer ranges from 40 nm to 100 nm.

Optionally, the method further includes: and forming a metal wiring layer on the exposed surface of the first conductive plug.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, the first epitaxial layer is formed on the first surface, and the materials of the first epitaxial layer and the first substrate are different, so that the first substrate can be removed after the first substrate and the second substrate are bonded, the height of the first conductive plug which needs to penetrate through the first epitaxial layer and a part of the first device layer is smaller, the occupied area of the first conductive plug on the surface parallel to the first surface can be reduced, and the integration level of the semiconductor structure is further improved. Furthermore, because the first epitaxial layer is formed on the first surface, and the plurality of fin structures which are separated from each other are formed on the top surface of the first epitaxial layer, compared with the material of the first substrate, by selecting a material with higher carrier mobility as the material of the first epitaxial layer, higher driving current can be provided for the MOS transistor formed by the fin structures, and thus, the performance of the semiconductor structure is improved.

In the semiconductor structure provided by the technical scheme of the invention, the first conductive plug is used for leading out the circuit of the first device layer and the circuit of the second substrate from the bottom surface of the first epitaxial layer. On the basis, the first conductive plug is positioned in the first epitaxial layer and the first device layer, so that the first conductive plug does not need to penetrate through the first substrate, and the height of the first conductive plug is reduced. By reducing the height of the first conductive plug, the area of the first conductive plug that needs to be occupied on the surface parallel to the first face can be reduced, thereby improving the integration of the semiconductor structure. In addition, compared with the material of the first substrate, the material with higher carrier mobility is selected as the material of the first epitaxial layer, so that higher driving current can be provided for the MOS device formed by the fin portion structure, and the performance of the semiconductor structure is improved.

Further, the first fin is used to form an NMOS device. Since the material of the first top layer comprises silicon and the material of the first strain relaxation layer comprises silicon germanium, on one hand, through the first strain relaxation layer, tensile stress can be caused on the first top layer, and therefore the driving current of the NMOS device is further increased. On the other hand, because the germanium content in the first strain relaxation layer is higher than that of the material of the first top layer, the first fin is internally provided with the ultra-steep degeneration well region, so that the carrier mobility of the NMOS device is further increased, and the driving current of the NMOS device is further increased. In conclusion, the performance of the semiconductor structure is further improved. Furthermore, since the first fin further extends into the first epitaxial layer, and the first strain relaxation buffer layer refers to a portion of the first fin extending into the first epitaxial layer, the first epitaxial layer also provides a material for the first strain relaxation buffer layer, so that the formation of the first strain relaxation buffer layer can be achieved in a simple process.

Further, the second fin is used to form a PMOS device. Since the second fin includes the second strain relaxation buffer layer and the second top layer, the material of the second top layer includes silicon germanium, the material of the second strain relaxation buffer layer includes silicon germanium, and the content of germanium in the material of the second top layer is greater than the content of germanium in the material of the second strain relaxation buffer layer, on one hand, through the second strain relaxation buffer layer, a compressive stress can be induced in the second top layer, thereby further increasing the driving current of the PMOS device. On the other hand, because the germanium content in the second strain relaxation buffer layer is higher than that of the material of the second top layer, the second fin is internally provided with the super-steep degeneration well region, so that the carrier mobility of the PMOS device is further increased, and the driving current of the PMOS device is further increased. In conclusion, the performance of the semiconductor structure is further improved. Furthermore, since the second fin also extends into the first epitaxial layer, and the second strain relaxation buffer layer refers to a portion of the second fin extending into the first epitaxial layer, the first epitaxial layer also provides a material for the second strain relaxation buffer layer, so that formation of the second strain relaxation buffer layer can be achieved in a simple step.

Drawings

Fig. 1 to fig. 11 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Detailed Description

As described in the background art, in the prior art, the depth of the through silicon via is limited to the micron level, and the area occupied by the through silicon via on the surface of the wafer is large, which results in poor integration of the semiconductor structure. Meanwhile, in the prior art, silicon is generally used as a material of a wafer, and compared with some strained materials such as silicon germanium and the like, the carrier mobility of silicon is small, so that the driving current of a semiconductor device such as a MOS transistor is small, and the performance of a semiconductor structure is poor.

In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, in which a first epitaxial layer is formed on a first surface of a first substrate, and the first substrate is removed, so that the integration level of the semiconductor structure is improved, and the performance of the semiconductor structure is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 to 11 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Referring to fig. 1, a first substrate 100 is provided, and the first substrate 100 includes a first side 101 and a second side 102 opposite to each other.

In the present embodiment, the first substrate 100 is a silicon substrate.

In other embodiments, the first substrate may also be a germanium, silicon germanium, gallium arsenide substrate, or the like. The type of substrate may be selected by a person skilled in the art as desired, and the type of first substrate should therefore not be a feature limiting the scope of the invention.

With reference to fig. 1, a first epitaxial layer 110 is formed on the first surface 101, the first epitaxial layer 110 has a top surface 110a and a bottom surface 110b opposite to each other, the bottom surface 110b of the first epitaxial layer 110 is in contact with the first surface 101, and a material of the first epitaxial layer 110 is different from a material of the first substrate 100.

The purpose of the material of the first epitaxial layer 110 being different from the material of the first substrate 100 is that, in the subsequent process of removing the first substrate, the material of the first epitaxial layer 110 and the material of the first substrate 100 can have different etching rates, so that the process of removing the first substrate 100 can be stopped at the bottom surface 110b of the first epitaxial layer 110, and the removal of the first substrate 100 is realized.

In this embodiment, the material of the first epitaxial layer 110 includes silicon germanium.

The carrier mobility of the germanium-silicon is higher than that of silicon, and since the material of the first epitaxial layer 110 includes germanium-silicon, compared with the first substrate 100, the first epitaxial layer 110 in this embodiment can provide a higher driving current for a MOS transistor formed by a subsequently formed fin structure, so as to improve the performance of the semiconductor structure.

Preferably, the forming process of the first epitaxial layer 110 includes an epitaxial growth process. The first epitaxial layer 110 formed using the epitaxial growth process has a small thickness, which can be only several hundred nanometers.

Specifically, the thickness H1 of the first epitaxial layer 110 ranges from 200 nm to 500 nm.

The thickness H1 of the first epitaxial layer 110 is too small, the first epitaxial layer 110 cannot well replace the first substrate 100 to provide sufficient driving current for the subsequently formed MOS transistor, and the thickness H1 of the first epitaxial layer 110 is too large, which increases the height of the subsequently formed first conductive plug, and is not favorable for improving the integration level of the semiconductor structure. Therefore, by making the thickness H1 of the first epitaxial layer 110 in the range of 200 nm to 500 nm, on one hand, the first epitaxial layer 110 better replaces the first substrate 100 to provide sufficient driving current for the subsequently formed MOS transistor, and the performance of the semiconductor structure is better improved; on the other hand, it is more favorable to reduce the height of the first conductive plug, so as to better improve the integration level of the semiconductor structure.

Specifically, the parameters of the epitaxial growth process for forming the first epitaxial layer 110 include: the reaction gas comprises GeH ₄ And SiH ₄ Or SiH ₂ Cl ₂ The deposition temperature is 600-900 ℃, and GeH ₄ The percentage concentration of the gas is 10-35%.

In the present embodiment, the content of germanium in the material of the first epitaxial layer 110 is 10% to 30%.

In this embodiment, the first epitaxial layer 110 includes a first region I and a second region II, which are used to form devices of different conductivity types.

Specifically, the first region I in this embodiment is used to form an NMOS device, and the second region II is used to form a PMOS device.

In other embodiments, the first epitaxial layer may not distinguish between the first and second regions, or the first region may be used to form PMOS devices and the second region may be used to form NMOS devices.

Next, a plurality of fin structures separated from each other are formed on the top surface 110a of the first epitaxial layer 110. Please refer to fig. 2 to 5 for steps of forming a plurality of fin structures.

Referring to fig. 2, a second epitaxial layer 120 is formed on the top surface 110a of the first epitaxial layer 110 over the first region I and the second region II.

In this embodiment, the second epitaxial layer 120 provides materials for fin structures to be formed in the first region I.

In this embodiment, the material of the second epitaxial layer 120 includes silicon. Thereby, NMOS devices can be subsequently formed in the first region I.

In the present embodiment, the thickness H2 of the second epitaxial layer 120 ranges from 40 nm to 100 nm.

The thickness H2 of the second epitaxial layer 120 is 40 nm to 100 nm for controlling the total height of the first epitaxial layer 110 and the fin structure formed subsequently. Therefore, the height of the first conductive plug formed subsequently can be ensured to reach only a few hundred nanometers better.

In this embodiment, the forming process of the second epitaxial layer 120 includes an epitaxial growth process.

With continued reference to fig. 2, a first opening 121 is formed in the second epitaxial layer 120, and the first opening 121 exposes the surface of the first epitaxial layer 110 on the second region II.

The first opening 121 provides a space for the subsequent formation of a third epitaxial layer.

In this embodiment, the method of forming the first opening 121 includes: forming a first opening mask layer (not shown) on the surface of the second epitaxial layer 120, wherein the first opening mask layer exposes the surface of the second epitaxial layer 120 in the second region II; and etching the second epitaxial layer 120 by taking the first opening mask layer as a mask until the surface of the first epitaxial layer 110 is exposed.

In the present embodiment, the process of etching the second epitaxial layer 120 to form the first opening 121 includes at least one of a dry etching process and a wet etching process.

In this embodiment, after the first opening 121 is formed, the first opening mask layer is removed.

Referring to fig. 3, a third epitaxial layer 130 is formed in the first opening 121 (as shown in fig. 2), and the third epitaxial layer 130 fills the first opening 121.

The third epitaxial layer 130 provides material for a fin structure to be formed in the second region II.

The material of the third epitaxial layer 130 is different from the material of the second epitaxial layer 120, so that the first region I and the second region II enable the formation of devices of different conductivity types.

In this embodiment, the material of the third epitaxial layer 130 is silicon germanium. Thereby, P-type devices can be subsequently formed in the second region II.

In this embodiment, the content of germanium in the material of the third epitaxial layer 130 is greater than the content of germanium in the material of the first epitaxial layer 110.

By making the content of germanium in the material of the third epitaxial layer 130 greater than the content of germanium in the material of the first epitaxial layer 110, the content of germanium in the material of the subsequently formed second top layer can be made greater than the content of germanium in the material of the second strain-relaxed buffer layer.

Specifically, the content of germanium in the material of the third epitaxial layer 130 is 40% to 100%. Therefore, by matching the material of the second epitaxial layer 120 and the content of germanium in the material of the first epitaxial layer 110, the content of germanium in the subsequently formed material of the first top layer is higher than that of the first strain relaxation buffer layer, and the content of germanium in the subsequently formed material of the second top layer is higher than that of the second strain relaxation buffer layer.

In addition, in the case of forming devices (NMOS device and PMOS device) of different conductivity types in the first region I and the second region II in this embodiment, when the material of the first top layer formed subsequently includes silicon and the content of germanium in the material of the second top layer is 40% to 100%, by making the content of germanium in the material of the first epitaxial layer 110 be 10% to 30%, it is possible to achieve a higher driving current for both the NMOS device and the PMOS device.

In this embodiment, the method for forming the third epitaxial layer 130 includes: forming a third layer of epitaxial material (not shown) within the first opening 121 and the surface of the second epitaxial layer 120, the third layer of epitaxial material having a higher surface than the surface of the second epitaxial layer 120; the third layer of epitaxial material is planarized until the surface of the second epitaxial layer 120 is exposed.

Preferably, the process for forming the third epitaxial material layer includes an epitaxial growth process. The parameters of the epitaxial growth process comprise: the reaction gas comprises GeH ₄ And SiH ₄ Or SiH ₂ Cl ₂ The deposition temperature is 600-900 ℃, and, geH ₄ The percentage concentration of the gas is 40-65%.

The parameters of the epitaxial growth process are selected because the content of germanium in the third epitaxial layer 130 is controlled, thereby forming the third epitaxial layer 130 having a germanium content of 40% to 100%.

Referring to fig. 4 and 5, fig. 4 is a schematic cross-sectional structure along a direction X1-X2 in fig. 5, and fig. 5 is a schematic perspective structure of fig. 4, the second epitaxial layer 120 on the first region I and the third epitaxial layer 130 on the second region II are etched, and a plurality of fin structures (not shown) separated from each other are formed on the top surface 110a of the first epitaxial layer 110.

The method of etching the second epitaxial layer 120 on the first region I and the third epitaxial layer 130 on the second region II includes: forming a plurality of fin mask structures (not shown) separated from each other on the second epitaxial layer 120 and the third epitaxial layer 130; and etching the second epitaxial layer 120 on the first region I and the third epitaxial layer 130 on the second region II by taking the fin mask structure as a mask until part of the first epitaxial layer 110 is etched.

In this embodiment, the fin structures include: a number of first fins 140 located on the first region I, a number of second fins 150 located on the second region II, the first fins 140 and the second fins 150 being of different materials.

Since the materials of the first fin 140 and the second fin 150 are different, the first region I and the second region II can form devices of different conductivity types.

In this embodiment, the first fin is used to form an NMOS device and the second fin 150 is used to form a PMOS device.

In this embodiment, the purpose of etching part of the first epitaxial layer 110 is to: the formed fin structure comprises a Strain Relaxed Buffer (SRB) so as to better improve the performance of the semiconductor structure.

In other embodiments, the fin mask structure is used as a mask to etch the second epitaxial layer on the first region and the third epitaxial layer on the second region until the surface of the first epitaxial layer is exposed. That is, the fin structure may not include a strain-relaxed buffer layer.

Specifically, in the present embodiment, the first fin 140 further extends into the first epitaxial layer 110, and the first fin 140 includes a first relaxed buffer layer 141 and a first top layer 142 on the first relaxed buffer layer 141, where the first relaxed buffer layer 141 refers to a portion of the first fin 140 extending into the first epitaxial layer 110.

In particular, the material of the first strain-relaxation layer 141 is provided by the first epitaxial layer 110 and the material of the first top layer 142 is provided by the second epitaxial layer 120. Thus, the material of the first strain relaxation layer 141 in this embodiment comprises silicon germanium, while the material of the first top layer 142 comprises silicon.

Since the material of the first top layer 142 includes silicon and the material of the first relaxed buffer layer 141 includes silicon germanium, on one hand, a tensile stress can be induced in the first top layer 142 by the first relaxed buffer layer 141, thereby further increasing the driving current of the NMOS device. On the other hand, since the germanium content in the first strain relaxation buffer layer 141 is higher than that of the material of the first top layer 142, the first fin 140 has a Super-Steep Retrograde Well (SSRW) therein, so that the carrier mobility of the NMOS device is further increased, and thus, the driving current of the NMOS device is further increased. In conclusion, the performance of the semiconductor structure is further improved.

In the present embodiment, the second fin 150 further extends into the first epitaxial layer 110, and the second fin 150 includes a second strain relaxation buffer layer 151 and a second top layer 152 on the second strain relaxation buffer layer 151, wherein the second strain relaxation buffer layer 151 refers to a portion of the second fin 150 extending into the first epitaxial layer 110.

In particular, the material of the second strain-relaxed buffer layer 151 is provided by the first epitaxial layer 110 and the material of the second top layer 152 is provided by the third epitaxial layer 130. Therefore, the material of the second strain relaxed buffer layer 151 in this embodiment includes silicon germanium, the material of the second top layer 152 includes silicon germanium, and the content of germanium in the material of the second top layer 152 is higher than the content of germanium in the material of the second strain relaxed buffer layer 151.

Since the second fin 150 includes the second strain relaxation buffer layer 151 and the second top layer 152, the material of the second top layer 152 includes silicon germanium, the material of the second strain relaxation buffer layer 151 includes silicon germanium, and the content of germanium in the material of the second top layer 152 is greater than the content of germanium in the material of the second strain relaxation buffer layer 151, on one hand, a compressive stress can be induced in the second top layer 152 by the second strain relaxation buffer layer 151, thereby further increasing the driving current of the PMOS device. On the other hand, since the content of germanium in the material of the second top layer 152 is higher than that of the second strain relaxation buffer layer 151, the second fin 150 has a super-steep retrograde well region therein, so that the carrier mobility of the PMOS device is further increased, and thus, the driving current of the PMOS device is further increased. In conclusion, the performance of the semiconductor structure is further improved.

Furthermore, since the first epitaxial layer 110 also provides a material for the first and second strain relaxation buffer layers 141 and 151, the formation of the first and second strain relaxation buffer layers 141 and 151 can be achieved in simple steps.

In this embodiment, the fin mask structure is used as a mask to etch the second epitaxial layer 120 on the first region I and the third epitaxial layer 130 on the second region II until a portion of the first epitaxial layer 110 is etched, where the etching process includes at least one of a dry etching process and a wet etching process.

Referring to fig. 6, a first device layer 160 is formed on the first epitaxial layer 110 and the surface of the fin structure (not shown).

Specifically, the first device layer 160 is formed based on a front end of line (FEOL), a middle end of line (MEOL), and a back end of line (BEOL) in a semiconductor process.

The first device layer 160 includes a plurality of device structures (not shown), a plurality of interconnect structures (not shown), and an isolation dielectric structure (not shown) surrounding the fin structure, the interconnect structures, and the device structures.

The device structure comprises a plurality of grid structures so as to form devices such as transistors, diodes, triodes and the like. The device structure may also include capacitive, inductive, etc. devices. The isolation dielectric structure may be comprised of multiple layers of dielectric materials.

The device structure, interconnect structure, and isolation dielectric structure in the first device layer 160 may be selected as desired by those skilled in the art. Accordingly, the specific device structure, interconnect structure and isolation dielectric structure in the first device layer 160 should not be features that limit the scope of the present invention.

Referring to fig. 7, a second substrate 200 is provided, the second substrate 200 having a circuit (not shown) therein.

It is to be understood that the circuit may be formed in the second substrate 200 as needed by those skilled in the art. Therefore, the specific structure of the second substrate 200 should not be a feature that limits the scope of the present invention.

Preferably, the second substrate 200 includes: a substrate 201, a fourth epitaxial layer 202 on the surface of the substrate 201, and a second device layer 203 on the fourth epitaxial layer 202.

When the subsequent first substrate 100 and the second substrate 200 are bonded, the fourth epitaxial layer 202 in the second substrate 200 is symmetrical to the first epitaxial layer 110 in the structure above and below the bonding surface, so that the stress of the bonding surface can be more uniform, and the performance and the reliability of the semiconductor structure can be improved.

The method for forming the fourth epitaxial layer 202 and the second device layer 203 in this embodiment may refer to the method for forming the first epitaxial layer 110, the fin structures, and the first device layer 160 in fig. 1 to 5. Likewise, the second device layer 203 may be formed as desired by those skilled in the art, and the specific structure of the second device layer 203 should not be a feature that limits the scope of the present invention.

With continued reference to fig. 7, after the first device layer 160 is formed, the first substrate 100 and the second substrate 200 are bonded, the first side 101 faces the second substrate 200, and the circuit is electrically interconnected with the first device layer 160.

In the present embodiment, the manner of bonding the first substrate 100 and the second substrate 200 may be eutectic bonding, or may be any other bonding process feasible in a semiconductor process.

Next, after the first substrate 100 and the second substrate 200 are bonded, the first substrate 100 is removed. Please refer to fig. 8 and 9 for the specific steps of removing the first substrate 100.

Referring to fig. 8, the first substrate 100 is thinned from the second surface 102 until the thickness W1 of the first substrate 100 is within a second predetermined thickness range.

By thinning the first substrate 100 from the second side 102 before subsequently removing the first substrate 100 having a thickness W1 within a second predetermined thickness range, processes of different etch rates can be employed throughout the process of removing the first substrate 100. Therefore, on one hand, when the first substrate 100 is thinned, a part of the first substrate 100 can be removed quickly to improve the efficiency of removing the first substrate 100, and on the other hand, when the part of the first substrate 100 with the thickness W1 within the second preset thickness range is subsequently removed, the etching process can be stopped at the second surface 102 better by a process with higher etching rate and higher precision, so as to improve the performance and reliability of the semiconductor structure.

In this embodiment, the second predetermined thickness is in a range of 8 to 12 micrometers.

If the thickness W1 is too large, more time is required to remove the first substrate 100, which is not favorable for improving the efficiency of removing the first substrate 100. If the thickness W1 is too small, the first substrate 100 may be directly removed under the condition of relatively quickly thinning the first substrate 100, and the etching process may not be stopped on the surface of the first epitaxial layer 110, which may cause damage to the first epitaxial layer 110. Therefore, when the appropriate thickness W1, i.e., the thickness W1 is within the second predetermined thickness range (8 micrometers to 12 micrometers), it can be better compatible with improving the efficiency of removing the first substrate 100 and reducing the risk of damage to the first epitaxial layer 110.

In this embodiment, the process of thinning the first substrate 100 from the second side 102 includes: a dry etching process or a chemical mechanical polishing process.

Preferably, a dry etching process is used to thin the first substrate 100.

The dry etching process comprises a plasma etching process, wherein the gas adopted by the plasma etching process comprises Cl ₂ 、HBr、SF ₆ And CF ₄ One or more of (a).

Specifically, in the process of thinning the first substrate 100 from the second side 102, the first substrate 100 has a first etching rate. Referring to fig. 9, after the first substrate 100 is thinned, the first substrate 100 with the thickness W1 is removed.

In this embodiment, the first substrate 100 is etched from the second surface 102 until the surface of the first epitaxial layer 110 is exposed, so as to remove the first substrate 100 with the thickness W1.

In this embodiment, after the first substrate 100 is thinned, in the process of etching the first substrate 100 from the second surface 102, the first epitaxial layer 110 and the first substrate 100 have a second etching rate, and the second etching rate is less than the first etching rate. Thereby, a better compromise is obtained for improving the efficiency of removing the first substrate 100 and reducing the risk of damage to the first epitaxial layer 110.

Specifically, in the etching process for thinning the first substrate 100, there may be a smaller etching selectivity or no etching selectivity for the first substrate 100 and the first epitaxial layer 110, and a larger etching rate (first etching rate) for the first substrate 100.

In the process of etching the first substrate 100 from the second surface 102 after thinning the first substrate 100, the first substrate 100 and the first epitaxial layer 110 have a larger etching selectivity, and the etching rate (second etching rate) to the first substrate 100 is correspondingly reduced.

Therefore, the efficiency of removing the first substrate 100 is improved, and the risk of damage to the first epitaxial layer 110 is reduced.

Preferably, the first substrate 100 is etched from the second side 102 using a dry etching process. Since the dry etching process is an anisotropic etching process, the process accuracy in the dimension direction of the thickness W1 is improved, which is advantageous for stopping the etching process on the surface of the first epitaxial layer 110 better.

In this embodiment, the parameters of the dry etching process include: the gas used comprises H ₂ 、CF ₄ And Ar, and H ₂ 、CF ₄ And Ar at a gas flow ratio of 10, from 30 to 10, at a temperature in the range of 10 ℃ to 60 ℃, at a power in the range of 30W to 200W, and at a pressure in the range of 50 mtorr to 300 mtorr.

Preferably, H ₂ 、CF ₄ And Ar at a gas flow ratio of 10.

In other embodiments, the parameters of the dry etching process include: the gas used comprises H ₂ 、NF ₃ And Ar, and H ₂ 、NF ₃ And Ar at a gas flow ratio of 10, from 30 to 10, at a temperature in the range of 10 ℃ to 60 ℃, at a power in the range of 30W to 200W, and at a pressure in the range of 50 mtorr to 300 mtorr. Preferably, H ₂ 、NF ₃ And Ar at a gas flow ratio of 10.

In another embodiment, the first substrate 100 is planarized from the second side 102 until the surface of the first epitaxial layer 110 is exposed, so as to remove the first substrate 100 with the thickness W1.

Referring to fig. 10, after removing the first substrate 100, a plurality of first conductive plugs 170 are formed in the first epitaxial layer 110 and the first device layer 160, the first conductive plugs 170 are electrically interconnected with the first device layer 160, and the bottom surface 110b of the first epitaxial layer 110 exposes a plurality of surfaces of the first conductive plugs 170.

Since the first epitaxial layer 110 is formed on the first surface 101 (as shown in fig. 8), and the materials of the first epitaxial layer 110 and the first substrate 100 are different, after the first substrate 100 and the second substrate 200 are bonded, the first substrate 100 can be removed, so that the height H3 of the first conductive plug 170 required to pass through the first epitaxial layer 110 and a part of the first device layer 160 is smaller, and therefore, the occupied area of the first conductive plug 170 on the surface parallel to the first surface 101 can be reduced, and further, the integration level of the semiconductor structure is improved. Furthermore, since the first epitaxial layer 110 is formed on the first surface 101 and the plurality of fin structures separated from each other are formed on the top surface 110a of the first epitaxial layer 110, a higher driving current can be supplied to the MOS transistor formed by the fin structures by selecting a material having a higher carrier mobility as the material of the first epitaxial layer 110 as compared with the material of the first substrate 100, thereby improving the performance of the semiconductor structure.

Specifically, limited by the limit of the etching process in the prior art, the aspect ratio (TSV aspect ratio) of the through silicon via for providing space for the first conductive plug 170 needs to be below a preset ratio (typically below 10), so that, when the height H3 of the first conductive plug 170 is reduced, the area of the first conductive plug 170 on the surface parallel to the first face 101 needs to be reduced accordingly.

Meanwhile, since the first epitaxial layer 110 is formed on the first surface 101, after the first substrate 100 and the second substrate 200 are bonded, the process of removing the first substrate 100 can have different etching rates for the first epitaxial layer 110 and the first substrate 100, so that the process of removing the first substrate 100 can be stopped at the bottom surface 110b of the first epitaxial layer 110 to achieve the removal of the first substrate 100, and thus, the height of the first conductive plug 170 is determined by the total thickness of the first epitaxial layer 110 and the portion of the first device layer 160 through which the first conductive plug 170 needs to pass. Compared with the first substrate 100 with the thickness still at the micron level after being thinned by the back-of-wafer thinning technology, the first epitaxial layer 110 formed by the epitaxial growth technology has smaller thickness and can reach hundreds of nanometers, and therefore the height H3 of the first conductive plug 170 which does not need to penetrate through the first substrate 100 is smaller, so that the area of the first conductive plug 170 which needs to be occupied on the surface parallel to the first surface 101 can be smaller, and further, the integration level of the semiconductor structure is improved.

In the present embodiment, the height H3 of the first conductive plug 170 ranges from 240 nm to 800 nm. Thus, it is possible to achieve a reduction in the diameter of the first conductive plug 170 to the range of 50 nm to 200 nm.

Specifically, the first conductive plug 170 is formed using a through silicon via (tsv) technique. The method of forming the first conductive plug 170 includes: etching the first epitaxial layer 110 and the first device layer 160 to form a Through Silicon Via (TSV); the first conductive plug 170 is formed within the through-silicon via.

The first conductive plug 170 includes: a barrier layer (not shown) on the inner wall surface of the through-silicon via, and a conductive layer (not shown) on the surface of the barrier layer.

Referring to fig. 11, a metal wiring layer 180 is formed on the exposed surface of the first conductive plug 170.

Accordingly, an embodiment of the present invention provides a semiconductor structure formed by the above-mentioned forming method, with reference to fig. 11, including: a first epitaxial layer 110, the first epitaxial layer 110 having opposing top 110a and bottom 110b surfaces; a plurality of fin structures (not shown) located on the top surface 110a of the first epitaxial layer 110 and separated from each other; a first device layer 160 on the first epitaxial layer 110 and the surfaces of the plurality of fin structures; a second substrate 200 bonded to the first device layer 160, the second substrate 200 having circuitry therein that is electrically interconnected to the first device layer 160; a plurality of first conductive plugs 170 located in the first epitaxial layer 110 and the first device layer 160, wherein the first conductive plugs 170 are electrically interconnected with the first device layer 160, and the bottom surface 110b of the first epitaxial layer 110 exposes the surfaces of the plurality of first conductive plugs 170.

The first conductive plugs 170 serve to draw the circuits of the first device layer 160 and the circuits of the second substrate 200 at the bottom surface 110b of the first epitaxial layer 110. On this basis, since the first conductive plug 170 is located within the first epitaxial layer 110 and the first device layer 160, the first conductive plug 170 does not need to pass through the first substrate 100, and thus, the height H3 of the first conductive plug 170 is reduced. By reducing the height H3 of the first conductive plug 170, the area of the first conductive plug 170 that needs to be occupied on the surface parallel to the first face 101 can be reduced, thereby improving the integration of the semiconductor structure. In addition, by selecting a material with higher carrier mobility as the material of the first epitaxial layer 110 compared to the material of the first substrate 100, a higher driving current can be provided for the MOS device composed of the fin structure, thereby improving the performance of the semiconductor structure.

Specifically, the thickness H1 (shown in fig. 1) of the first epitaxial layer 110 ranges from 200 nm to 500 nm.

In this embodiment, the height H3 of the first conductive plug 170 ranges from 240 nm to 800 nm.

In this embodiment, the first fin 140 further extends into the first epitaxial layer 110, and the first fin 140 includes a first relaxed buffer layer 141 and a first top layer 142 on the first relaxed buffer layer 141, where the first relaxed buffer layer 141 refers to a portion of the first fin 140 extending into the first epitaxial layer 110.

In the present embodiment, the material of the first strain relaxation buffer layer 141 comprises silicon germanium.

In the present embodiment, the content of germanium in the material of the first strain relaxation buffer layer 141 is 10% to 30%.

In the present embodiment, the material of the first top layer 142 includes silicon.

In this embodiment, the material of the second top layer 152 includes silicon germanium, the material of the second strain relaxed buffer layer 151 includes silicon germanium, and the content of germanium in the material of the second top layer 152 is greater than the content of germanium in the material of the second strain relaxed buffer layer 151,

in this embodiment, the content of germanium in the material of the second top layer 152 is 40% to 100%, and the content of germanium in the material of the second strain-relaxed buffer layer 151 is 10% to 30%.

In this embodiment, the first device layer 160 includes a plurality of device structures (not shown), a plurality of interconnect structures (not shown), and an isolation dielectric structure (not shown), which surrounds the fin structure, the interconnect structures, and the device structures.

The device structure comprises a plurality of grid structures so as to form devices such as transistors, diodes, triodes and the like. The device structure may also include capacitive, inductive, etc. devices. The isolating dielectric structure may be comprised of multiple layers of dielectric materials.

In this embodiment, the first conductive plug 170 includes: the barrier layer (not shown) is positioned on the inner wall surface of the silicon through hole, and the conductive layer (not shown) is positioned on the surface of the barrier layer, and the barrier layer is used for blocking outward diffusion of materials of the conductive layer.

In this embodiment, the semiconductor structure further includes: a metal wiring layer 180 on the exposed surface of the first conductive plug 170.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

a first epitaxial layer having opposing top and bottom surfaces;

the fin structures are positioned on the top surface of the first epitaxial layer and are separated from each other;

the first device layer is positioned on the surfaces of the first epitaxial layer and the fin structures and comprises a plurality of device structures, a plurality of interconnection structures and an isolation medium structure, and the fin structures, the interconnection structures and the device structures are surrounded by the isolation medium structure;

a second substrate bonded to the first device layer, the second substrate having circuitry therein, the circuitry being electrically interconnected with the first device layer;

the first conductive plugs are positioned in the first epitaxial layer and the first device layer and electrically interconnected with the first device layer, and the surfaces of the first conductive plugs are exposed out of the bottom surface of the first epitaxial layer.

2. The semiconductor structure of claim 1, wherein a height of the first conductive plug ranges from 240 nm to 800 nm.

3. The semiconductor structure of claim 1, wherein a thickness of the first epitaxial layer ranges from 200 nm to 500 nm.

4. The semiconductor structure of claim 1, wherein the material of the first epitaxial layer comprises silicon germanium.

5. The semiconductor structure of claim 4, wherein a germanium content in the material of the first epitaxial layer is 10% to 30%.

6. The semiconductor structure of claim 1, wherein the first epitaxial layer comprises a first region and a second region, and wherein the number of fin structures comprises: a number of first fins located on the first region, a number of second fins located on the second region, the first fins and the second fins being of different materials.

7. The semiconductor structure of claim 6, wherein the first fin further extends into the first epitaxial layer, the first fin comprising a first strain relaxation buffer layer and a first top layer on the first strain relaxation buffer layer, the first strain relaxation buffer layer referring to a portion of the first fin extending into the first epitaxial layer, a material of the first top layer comprising silicon, the material of the first strain relaxation buffer layer comprising silicon germanium.

8. The semiconductor structure of claim 6, wherein the second fin further extends into the first epitaxial layer, the second fin includes a second strain relaxed buffer layer and a second top layer on the second strain relaxed buffer layer, the second strain relaxed buffer layer refers to a portion of the second fin extending into the first epitaxial layer, the second top layer includes silicon germanium, the second strain relaxed buffer layer includes silicon germanium, and a content of germanium in the material of the second top layer is greater than a content of germanium in the material of the second strain relaxed buffer layer.

9. The semiconductor structure of claim 8, wherein a germanium content of the material of the second top layer is 40-100%, and a germanium content of the material of the second strain relaxed buffer layer is 10-30%.

10. The semiconductor structure of claim 1, further comprising: and a metal wiring layer on the exposed surface of the first conductive plug.

11. The semiconductor structure of claim 1, wherein the first device layer comprises a number of device structures, a number of interconnect structures, and an isolation dielectric structure surrounding the fin structure, interconnect structures, and device structures.

12. A method of forming a semiconductor structure, comprising:

providing a first substrate comprising opposing first and second sides;

forming a first epitaxial layer on the first surface, wherein the first epitaxial layer is provided with a top surface and a bottom surface which are opposite, the bottom surface of the first epitaxial layer is in contact with the first surface, and the material of the first epitaxial layer is different from that of the first substrate;

forming a plurality of mutually-separated fin part structures on the top surface of the first epitaxial layer;

forming a first device layer on the surfaces of the first epitaxial layer and the fin structure;

providing a second substrate having circuitry therein;

bonding the first substrate and the second substrate after forming the first device layer, the first side facing the second substrate, and the circuit being electrically interconnected with the first device layer;

removing the first substrate after bonding the first substrate and the second substrate;

and after the first substrate is removed, a plurality of first conductive plugs are formed in the first epitaxial layer and the first device layer, the first conductive plugs are electrically interconnected with the first device layer, and the surfaces of the first conductive plugs are exposed from the bottom surface of the first epitaxial layer.

13. The method of forming a semiconductor structure of claim 12, wherein a thickness of the first epitaxial layer ranges from 200 nanometers to 500 nanometers.

14. The method of forming a semiconductor structure of claim 12, wherein the process of forming the first epitaxial layer comprises an epitaxial growth process, and the parameters of the epitaxial growth process comprise: the reaction gas comprises GeH ₄ And SiH ₄ Or SiH ₂ Cl ₂ The deposition temperature is 600-900 ℃, and GeH ₄ The percentage concentration of the gas is 10-35%.

15. The method of forming a semiconductor structure of claim 12, wherein removing the first substrate comprises: thinning the first substrate from the second surface until the thickness of the first substrate is within a second preset thickness range; and after thinning the first substrate, etching or flattening the first substrate from the second surface until the surface of the first epitaxial layer is exposed.

16. The method of claim 15, wherein the second predetermined thickness is in a range from 8 microns to 12 microns.

17. The method of claim 15, wherein the first substrate has a first etch rate during the process of thinning the first substrate from the second side, wherein the first substrate has a second etch rate after thinning the first substrate and during the process of etching or planarizing the first substrate from the second side, and wherein the second etch rate is less than the first etch rate.

18. The method of forming a semiconductor structure of claim 15, wherein the process of thinning the first substrate from the second side comprises: a dry etching process or a chemical mechanical polishing process.

19. The method of claim 18, wherein the dry etching process comprises a plasma etching process using a gas comprising Cl ₂ 、HBr、SF ₆ And CF ₄ One or more of (a).

20. The method for forming a semiconductor structure according to claim 15, wherein after thinning the first substrate, the first substrate is etched from the second side using a dry etching process, and parameters of the dry etching process include: the gas used comprises H ₂ 、CF ₄ And Ar, or the gas used comprises H ₂ 、NF ₃ And Ar, and H ₂ 、CF ₄ And Ar at a gas flow ratio of 10 ₂ 、NF ₃ And Ar at a gas flow ratio of 10, from 30 to 10, at a temperature in the range of 10 ℃ to 60 ℃, at a power in the range of 30W to 200W, and at a pressure in the range of 50 mtorr to 300 mtorr.

21. The method of forming a semiconductor structure of claim 12, wherein the first epitaxial layer comprises a first region and a second region, and wherein the fin structures comprise: a number of first fins located on the first region, a number of second fins located on the second region, the first fins and the second fins being of different materials.

22. The method of forming a semiconductor structure of claim 21, wherein the first fin and the second fin further extend into a first epitaxial layer, the first fin comprising a first strain relaxed buffer layer and a first top layer on the first strain relaxed buffer layer, the second fin comprising a second strain relaxed buffer layer and a second top layer on the second strain relaxed buffer layer, the first strain relaxed buffer layer being the portion of the first fin that extends into the first epitaxial layer, the second strain relaxed buffer layer being the portion of the second fin that extends into the first epitaxial layer.

23. The method of forming a semiconductor structure of claim 22, wherein forming a plurality of fin structures comprises: forming a second epitaxial layer on the top surface of the first epitaxial layer on the first region and the second region; forming a first opening in the second epitaxial layer, wherein the first opening exposes the surface of the first epitaxial layer on the second region; forming a third epitaxial layer in the first opening, wherein the first opening is filled with the third epitaxial layer; forming a plurality of fin mask structures which are mutually separated on the second epitaxial layer and the third epitaxial layer; and etching the second epitaxial layer on the first region and the third epitaxial layer on the second region by taking the fin part mask structure as a mask until part of the first epitaxial layer is etched.

24. The method of forming a semiconductor structure of claim 23, wherein the material of the first epitaxial layer and the material of the third epitaxial layer comprise silicon germanium, the material of the second epitaxial layer comprises silicon, and the content of germanium in the material of the third epitaxial layer is greater than the content of germanium in the material of the first epitaxial layer.

25. The method of forming a semiconductor structure of claim 23, wherein the process of forming the third epitaxial layer comprises an epitaxial growth process, and the parameters of the epitaxial growth process comprise: the reaction gas comprises GeH ₄ And SiH ₄ Or SiH ₂ Cl ₂ The deposition temperature is 600-900 ℃, and GeH ₄ The percentage concentration of the gas is 40-65%.

26. The method of forming a semiconductor structure of claim 23, wherein the thickness of the second epitaxial layer ranges from 40 nanometers to 100 nanometers.

27. The method of forming a semiconductor structure of claim 12, further comprising: and forming a metal wiring layer on the exposed surface of the first conductive plug.