CN115881562A - Method and system for monitoring and controlling semiconductor process - Google Patents

Abstract

The invention provides a method and a system for monitoring and controlling a semiconductor process. The method comprises the following steps: forming at least one active area on a substrate; after forming at least one active area, forming a first patterned photoresist layer for defining at least two word lines on the at least one active area; detecting and measuring the position and the size of at least one active region and the first patterned photoresist layer, and calculating the estimated area of at least two estimated contact windows in at least one active region according to the predefined position of at least one bit line; adjusting the predefined position of at least one bit line according to the estimated areas of at least two estimated contact windows in at least one active region; and forming a second patterned photoresist layer on the substrate, the second patterned photoresist layer corresponding to the predefined location of the adjusted bit line.

Description

Method and system for monitoring and controlling semiconductor process

Technical Field

The invention relates to a method and a system for monitoring and controlling a semiconductor process.

Background

Photolithography (lithography) is a critical step in semiconductor processing that is used to define the location of individual components on a substrate. Therefore, photolithography is often the bottleneck of semiconductor processing. In photolithography, good alignment and control of critical dimensions of circuits have a significant impact on the yield of the product.

Therefore, in semiconductor manufacturing, it is important to examine whether an unexpected overlay phenomenon occurs in a device in accordance with a process step, and then to adopt a corresponding correction method.

Disclosure of Invention

The invention aims at a method and a system for monitoring and controlling a semiconductor process, which can achieve the uniform configuration of the contact areas of two contact windows in two memory cells sharing one active region.

According to an embodiment of the present invention, a method for monitoring and controlling a semiconductor process includes the following steps. Forming at least one active region on a substrate; forming a first patterned photoresist layer (photoresist layer) for defining at least two word lines on the at least one active region after the at least one active region is formed; detecting and measuring the position and the size of at least one active region and the first patterned photoresist layer, and calculating the estimated area of at least two estimated contact windows in at least one active region according to the predefined position of at least one bit line; adjusting the predefined position of at least one bit line according to the estimated areas of at least two estimated contact windows in at least one active region; and forming a second patterned photoresist layer on the substrate, wherein the second patterned photoresist layer corresponds to the predefined location of the adjusted at least one bit line.

According to an embodiment of the present invention, a system for monitoring and controlling a semiconductor process includes a semiconductor manufacturing apparatus and a controller. Semiconductor fabrication equipment is used to fabricate integrated circuits on a substrate. The controller is coupled to the semiconductor manufacturing equipment. The controller controls the semiconductor manufacturing apparatus: forming at least one active region on a substrate; after forming the at least one active region, forming a first patterned photoresist layer for defining at least two word lines on the at least one active region; detecting and measuring the position and the size of at least one active region and the first patterned photoresist layer, and calculating the estimated area of at least two estimated contact windows in at least one active region according to the predefined position of at least one bit line; adjusting the predefined position of at least one bit line according to the estimated areas of at least two estimated contact windows in at least one active region; and forming a second patterned photoresist layer on the substrate, wherein the second patterned photoresist layer corresponds to the predefined location of the adjusted at least one bit line.

Drawings

FIG. 1 is a layout diagram of active areas, word lines and bit lines of a dynamic random access memory according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a relationship between a resistance Rc and a turn-on voltage Ion of a contact according to an embodiment of the invention;

FIG. 3 is a schematic diagram illustrating the contact area of a contact in an active region versus an overlay measurement of word lines and bit lines, in accordance with one embodiment of the present invention;

FIG. 4 is a block diagram of a system for monitoring and controlling a semiconductor process in accordance with one embodiment of the present invention;

FIG. 5 is a flow chart of a method of monitoring and controlling a semiconductor process in accordance with one embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating adjusting a contact area of a contact by moving a predefined position of a bit line according to an embodiment of the present invention;

FIG. 7 is a graph of the shift k parameter and the difference in the turn-on voltages of the contacts on both sides of the memory cell.

Description of the reference numerals

310A, 310B, 310C: an arrow;

400: a system for monitoring and controlling a semiconductor process;

410: a semiconductor manufacturing apparatus;

415: a controller;

420: a lithographic apparatus;

430: a measuring device;

440: a thin film deposition device;

450: etching equipment;

500: methods of monitoring and controlling semiconductor processes;

s510 to S595: methods of monitoring and controlling semiconductor processes;

x: an X axis;

y: a Y axis;

WL, WL 1-WL 4: a word line;

BL: a bit line;

AA. AA1: an active region;

t1, T2: a switching transistor;

CC1, CC2, A1-A4, B1-B4, CC1B, CC2B, CC1C, CC C, CC1D, CC2D, CC1A, CC A: a contact window;

IonD: the difference between the conduction voltages of the contact windows on the two sides;

k: and (4) displacement k parameter.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a layout diagram of active areas, word lines and bit lines of a dynamic random access memory according to an embodiment of the invention. In the layout of the dram in this embodiment, two memory cells share one bit line BL, and the two memory cells are controlled by two word lines WL respectively. When manufacturing the dram, the areas of the contacts CC1 and CC2 corresponding to the two word lines WL in the two memory cells may not be uniformly arranged due to the inaccuracy of the photolithography technique, so that the bridge margin of the contacts is further reduced.

The present embodiment is illustrated in the structure of fig. 1 in conjunction with photolithography in semiconductor processing. First, shallow Trench Isolation (STI) is used to form a plurality of active areas AA1 separated from each other on a substrate, and the active areas AA1 are arranged in a stripe shape and arranged in an array. After the active area AA1 is formed, a patterned photoresist layer for defining the word lines WL is formed on the substrate using a photolithography technique, thereby being prepared for forming the word lines WL. Then, an etching process is performed to form word lines WL in the substrate. The word lines WL are present in a vertical column (column) direction. After the word lines WL are formed, a patterned photoresist layer for defining the bit lines BL is formed on the substrate using a photolithography technique in preparation for forming the bit lines BL. Then, an etching process is performed to form the bit line BL on the substrate. The bit lines BL are present in the row (row) direction. Based on the foregoing process, two memory cells share the active area AA1, and two word lines WL cross the active area AA1, thereby generating two switching transistors T1 and T2, so that the capacitor elements of the respective memory cells can be connected to the bit line BL through the contact windows CC1 and CC2 and the switching transistors T1 and T2, respectively.

If the connection between the contact windows CC1 and CC2 and the corresponding capacitor devices is known, it is necessary to measure the areas of the contact windows CC1 and CC2 by an electron microscope after the semiconductor process is sequentially stacked in the order of forming the active regions, the word lines WL and the bit lines BL. However, after the connection condition of the contacts CC1 and CC2 is known, the positions of the word line WL and the bit line BL in the present semiconductor process cannot be adjusted in real time.

FIG. 2 is a diagram illustrating a relationship between the resistance Rc and the on-voltage Ion of the contact according to an embodiment of the invention. The horizontal axis represents the magnitude of the resistance Rc of the contact window, and k Ω is taken as a unit. The vertical axis represents the magnitude of the on-current Ion between the contact and the capacitor element, and is expressed in μ a. When the area of the contact window with the capacitor assembly is larger, the resistance value Rc of the contact window is smaller, and the conduction current Ion between the contact window and the capacitor assembly is larger; on the contrary, as the contact area with the capacitor device is smaller, the resistance Rc of the contact is larger, and the on-current Ion between the contact and the capacitor device is smaller. Therefore, it is desirable to make the contact windows CC1 and CC2 in the same active area AA1 have similar areas, so that the on-currents of the capacitor elements of each memory cell connected to the bit line BL through the switching transistors T1 and T2 in the active area AA1 can be uniform.

FIG. 3 is a diagram illustrating an overlay measurement of the contact area of the contacts CC1, CC2 in the active area AA1 with respect to the word line WL and bit line BL, according to an embodiment of the present invention. Fig. 3 (a) is a schematic diagram of the active area AA1 and the contacts CC1 and CC2 in fig. 1. Fig. 3 (B) shows a schematic diagram of the word line WL covering position of fig. 3 (a) shifted to the right (i.e., positive direction of X axis) by 3nm, as indicated by arrow 310B. Through the calculation of the present embodiment, the contact CC2B has an area reduced by about 8.5% compared to the contact CC 1B. FIG. 3 (C) shows a schematic diagram of the displacement of the location of the covering of the bit line BL of FIG. 3 (A) by 3nm downward (i.e., in the negative direction of the Y-axis), as indicated by arrow 310C. Through the calculation of the present embodiment, the contact CC2C is reduced by about 18% in area compared to the contact CC 1C. Fig. 3 (D) shows a schematic diagram in which the covering position of the word line WL in fig. 3 (a) is shifted to the right (i.e., positive direction of X axis) by 3nm (as indicated by arrow 310B) and the covering position of the bit line BL is shifted to the lower (i.e., negative direction of Y axis) by 3nm (as indicated by arrow 310C). Through the calculation of the present embodiment, the contact CC2D is reduced by about 25% in area compared to the contact CC 1D.

FIG. 4 is a block diagram of a system for monitoring and controlling a semiconductor process 400 according to one embodiment of the present invention, wherein the system for monitoring and controlling a semiconductor process 400 comprises a semiconductor manufacturing facility 410, a metrology facility 430, and a controller 415, and wherein the semiconductor manufacturing facility 410 comprises a lithography facility 420, a thin film deposition facility 440, an etching facility 450, and related facilities. Semiconductor manufacturing apparatus 410 is used to fabricate integrated circuits on a substrate by a number of apparatuses (e.g., apparatuses 420, 440, 450, etc.). The controller 415 is coupled to each of the devices 420, 440, 450 of the semiconductor manufacturing apparatus 410 and is configured to implement the method for monitoring and controlling the semiconductor process according to the embodiment. In some embodiments, the controller 415 is primarily configured to control various steps in the lithographic apparatus 420, and may also be located within the lithographic apparatus 420 of the semiconductor manufacturing apparatus 410. Measuring device 430 includes at least measuring the Critical Dimension (CD) and overlay Registration (RG) of each structure or photoresist layer on the substrate to know the location and dimensions of each structure or photoresist layer.

Fig. 5 is a flow chart of a method of monitoring and controlling a semiconductor process in accordance with an embodiment of the present invention. Referring to fig. 4 and 5, the semiconductor manufacturing apparatus 410 forms at least one active region on a substrate (step S510). After forming the active area, in step S520, the lithography apparatus 420 forms a first patterned photoresist layer for defining at least two word lines on the active area. The word lines WL extend in a first direction, the bit lines BL extend in a second direction, and the first direction and the second direction are not parallel to each other. In the present embodiment, the first direction and the second direction are perpendicular to each other.

In step S530, the measuring apparatus 430 detects and measures the position and size of at least one active region (e.g., the active region AA1 shown in fig. 1) and the first patterned photoresist layer on the substrate. In step S535, the controller 415 calculates estimated areas of at least two estimated contacts (e.g., the contacts CC1 and CC2 shown in fig. 1) in the active region according to the predefined position of the at least one bit line BL. In other words, the controller 415 simulates and calculates the estimated area of the estimated contact window based on the positions and sizes of the active region and the first patterned photoresist layer formed on the substrate and the position where the bit line BL is expected to be disposed (i.e., the aforementioned "predefined position"). The metrology tool 430 of this embodiment calculates an estimated area of the estimated contact window based on the Critical Dimension (CD) and the over-dose pattern (OVL) of the active region/first patterned photoresist layer. Since the lithography apparatus 420 still inevitably generates some errors when forming the first patterned photoresist layer, the measurement apparatus 430 detects and measures the positions and sizes of the active region and the first patterned photoresist layer in step S530, so as to interpret the errors generated by the lithography apparatus 420 in forming the first patterned photoresist layer, and calculate the estimated areas of the two estimated contact windows.

In step S540, the controller 415 adjusts the predefined position of the bit line BL according to the estimated areas of at least two estimated contact windows in the active region. Before step S550, the etching apparatus 450 in the semiconductor manufacturing apparatus 410 forms the word line WL through the aforementioned first patterned photoresist layer and thin film deposition apparatus 440. In step S550, the controller 415 controls the lithography apparatus 420 to form a second patterned photoresist layer on the substrate, where the second patterned photoresist layer corresponds to the predefined position of the adjusted bit line BL, so that the two estimated contact areas are close to the same.

FIG. 6 is a schematic diagram illustrating the adjustment of the contact area of the contact by moving the predefined position of the bit line according to an embodiment of the present invention. As can be seen from the upper part of fig. 6, due to the error of the photolithography technique, the word line WL is shifted to the left by 4nm (as indicated by arrow 310A), resulting in the area of the contact CC1A being slightly smaller than the area of the contact CC 2A. Therefore, the embodiment adjusts the predefined position of the bit line BL in the lower half of fig. 6 on the premise that the word line WL has been shifted to the left by 4nm, so that the bit line BL is shifted downward by 2.5nm (as shown by the arrow 310B) to try to make the area of the contact CC1B closer to the area of the contact CC 2B.

Referring again to fig. 5, since the adjusted predefined positions of the bit lines BL are inevitably slightly wrong when formed on the substrate in the form of the second patterned photoresist layer by the lithography apparatus 420, the embodiment can also detect and measure the position and size of the second patterned photoresist layer by the measuring apparatus 430 to detect the adjusted predefined positions in step S560. In step S570, the controller 415 calculates the estimated area of the estimated contact window in the active region again according to the position and size of the formed word line and the position and size of the second patterned photoresist layer. Then, in step S580, the controller 415 determines whether to adjust the position of the second patterned photoresist layer according to the estimated area of the estimated contact window in the active region. If the controller 415 determines in step S580 that the position of the second patterned photoresist layer does not need to be adjusted (i.e., no in step S580), then step S585 is performed. In contrast, if the controller 415 determines that the position of the second patterned photoresist layer needs to be adjusted in step S580 (i.e., yes in step S580), the second patterned photoresist layer that has been configured before is removed, and the process returns to step S550. In step S550, a second patterned photoresist layer is newly formed, wherein the second patterned photoresist layer corresponds to the predefined position of the adjusted bit line BL.

The present embodiment may repeatedly perform steps S550 to S580 for performing the fine adjustment of the second patterned photoresist layer multiple times according to the requirements of the application of the present embodiment, or evaluate whether various parameters in the semiconductor process are modified according to the detection and measurement results in step S560, so as to compensate the problem of insufficient contact area of the contact window in the memory cell caused by the error of the scaling technique by adjusting the predefined position of the bit line BL, thereby increasing the product yield in the semiconductor process.

After the second patterned photoresist layer is formed, in step S585, the etching apparatus 450 of the semiconductor manufacturing apparatus 410 forms the bit line BL through the second patterned photoresist layer. In step S590, the semiconductor manufacturing apparatus 410 configures contact holes on two contact windows in the active region, so as to couple with corresponding capacitor elements of the memory cells, thereby completing the random access memory structure. In step S595, wafer Acceptance Test (WAT) is performed on the completed integrated circuit to obtain the relevant electrical parameters of the integrated circuit, and to determine whether the integrated circuit manufactured by the semiconductor process is normal and can operate stably. In this embodiment, the resistance Rc and the on-current Ion of the contacts CC1 and CC2 in fig. 1 can be obtained through step S595, so as to determine whether the method 500 in fig. 5 indeed improves the product quality.

In some embodiments consistent with the present invention, the controller 415 may return to step S520 to adjust the first patterned photoresist layer multiple times before step S550, in addition to adjusting the position of the second patterned photoresist layer multiple times in steps S550-S580. In detail, if the controller 415 determines in step S535 that the first patterned photoresist layer needs to be adjusted to align the predefined position of the word line WL, the first patterned photoresist layer configured in step S520 needs to be eliminated, and then a new first patterned photoresist layer is formed, and the rest of the steps are continued from step S520.

In some embodiments consistent with the present invention, in addition to calculating the estimated areas of the at least two estimated contact windows in the active region in step S535 by detecting and measuring the positions and sizes of the at least one active region and the first patterned photoresist layer on the substrate in step S530, one employing the present embodiment may also detect and measure the positions and sizes of the at least one active region and the etched (i.e., formed) word line on the substrate to calculate the estimated areas of the at least two estimated contact windows in the active region.

In this embodiment, it is desirable that the estimated areas of the two estimated contact windows are close to balance the two estimated contact windows. In particular, the present embodiment desirably decouples both the bit line displacement k parameter ("BL OVL-Yshift k") in the covered y-axis and the optimized covered y-axis parameter ("OVL-Yoptimum"). The optimized overclotting Y-axis parameter ("OVL-Yoptimum") is calculated by an equation, and the displacement k parameter ("BL OVL-Y shift k") is optimized by a Wafer Acceptance Test (WAT). If the shift k parameter ("BL OVL-Y shift k") is still correlated with the area balance of the two estimated contacts, the user needs to adjust the shift k parameter ("BL OVL-Y shift k") to make the area balance of the two estimated contacts independent of the shift k parameter ("BL OVL-Y shift k").

FIG. 7 is a graph of the shift k parameter ("BL OVL-Y shift k") versus the difference in the conduction voltages of the contacts on both sides of the memory cell. The X axis represents a displacement k parameter ("BL OVL-Y shift k"), and the Y axis represents a difference IonD between the conduction voltages of the contacts on the two sides in the memory cell. Fig. 7 (a) shows that there is still a positive correlation between the difference ion d between the turn-on voltages and the displacement k parameter, and the present embodiment can be applied to optimize the displacement k parameter through a Wafer Acceptance Test (WAT), so that the difference ion d between the turn-on voltages and the displacement k parameter gradually adjusts from the positive correlation of fig. 7 (a) to the slightly positive correlation of fig. 7 (B) until becoming the non-correlation of fig. 7 (C). Therefore, the present embodiment can also optimize the shift k parameter through a Wafer Acceptance Test (WAT), so as to reduce the correlation between the shift k parameter and the conducting voltage difference of the contact windows on both sides of the memory cell.

In summary, the method and system for monitoring and controlling a semiconductor process according to the embodiments of the invention can estimate the area of the contact window for connecting to the capacitor device by monitoring the position and size of the active region and the first patterned photoresist layer for defining the word line (or the position and size of the formed word line), so as to correspondingly adjust the second patterned photoresist layer for defining the bit line, so as to make the areas of the two contact windows corresponding to the two memory cells in the same active region as close as possible, thereby increasing the yield of the semiconductor process.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A method of monitoring and controlling a semiconductor process, comprising:

forming at least one active region on a substrate;

after forming at least one of the active regions, forming a first patterned photoresist layer for defining at least two word lines on at least one of the active regions;

detecting and measuring the position and the size of at least one active region and the first patterned photoresist layer, and calculating the estimated area of at least two estimated contact windows in at least one active region according to the predefined position of at least one bit line;

adjusting the predefined position of at least one bit line according to the estimated areas of at least two estimated contact windows in at least one active region; and

forming a second patterned photoresist layer on the substrate, wherein the second patterned photoresist layer corresponds to the predefined location of the adjusted at least one of the bit lines.

2. The method of claim 1, further comprising:

forming the at least two word lines through the first patterned photoresist layer before forming the second patterned photoresist layer.

3. The method of claim 2, further comprising:

detecting and measuring a position and a dimension of the second patterned photoresist layer to detect the adjusted predefined position;

calculating the estimated areas of the at least two estimated contact windows in at least one active region again according to the positions of the at least two word lines and the positions and the sizes of the second patterned photoresist layer; and

reforming the second patterned photoresist layer according to the estimated areas of at least two estimated contact windows in at least one of the active regions, wherein the second patterned photoresist layer corresponds to the predefined position of the adjusted at least one of the bit lines.

4. The method of claim 2, further comprising:

detecting and measuring the position and the size of at least one active region and the position and the size of at least two word lines, and calculating the estimated area of at least two estimated contact windows in at least one active region according to the predefined position of at least one bit line;

adjusting the predefined position of at least one of the bit lines according to the estimated areas of at least two estimated contacts in at least one of the active regions.

5. The method of claim 1, wherein the at least two word lines cross at least one of the active regions, and wherein at least one of the active regions comprises two switch transistors, each switch transistor comprising one of the at least two contact windows,

wherein at least two contact windows in at least one active region are provided with contact holes,

wherein the at least two word lines are arranged along a first direction and at least one of the bit lines is arranged along a second direction, wherein the first direction and the second direction are not parallel to each other.

6. The method of claim 1, further comprising:

the first patterned photoresist layer is eliminated and a new first patterned photoresist layer is formed to align the predefined locations of the at least two word lines.

7. A system for monitoring and controlling a semiconductor process, comprising:

semiconductor manufacturing equipment for manufacturing an integrated circuit on a substrate; and

a controller coupled to the semiconductor manufacturing equipment,

wherein the controller controls the semiconductor manufacturing apparatus to:

forming at least one active region on the substrate;

after forming at least one of the active regions, forming a first patterned photoresist layer for defining at least two word lines on at least one of the active regions;

detecting and measuring the position and the size of at least one active region and the first patterned photoresist layer, and calculating the estimated area of at least two estimated contact windows in at least one active region according to the predefined position of at least one bit line;

adjusting the predefined position of at least one of the bit lines according to the estimated areas of at least two estimated contact windows in at least one of the active regions; and

forming a second patterned photoresist layer on the substrate, wherein the second patterned photoresist layer corresponds to the predefined location of the adjusted at least one of the bit lines.

8. The system of claim 7, wherein the controller is further configured to:

forming the at least two word lines through the first patterned photoresist layer before forming the second patterned photoresist layer.

9. The system of claim 8, wherein the controller is further configured to:

detecting and measuring a position and a dimension of the second patterned photoresist layer to detect the adjusted predefined position;

calculating the estimated areas of the at least two estimated contact windows in at least one active region again according to the positions of the at least two word lines and the positions and the sizes of the second patterned photoresist layer; and

reforming a second patterned photoresist layer according to the estimated areas of at least two estimated contact windows in at least one of the active regions, wherein the second patterned photoresist layer corresponds to the predefined position of the adjusted at least one of the bit lines.

10. The system of claim 7, wherein the at least two word lines cross at least one of the active regions, and at least one of the active regions comprises two switch transistors, each switch transistor comprising one of the at least two contact windows,

wherein at least two contact windows in at least one of the active regions are provided with contact holes,

wherein the at least two word lines are arranged along a first direction and at least one of the bit lines is arranged along a second direction, wherein the first direction and the second direction are not parallel to each other.

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